imxrt_ral/blocks/imxrt1011/
adc_etc.rs
1#[doc = "ADC_ETC"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "ADC_ETC Global Control Register"]
5 pub CTRL: crate::RWRegister<u32>,
6 #[doc = "ETC DONE0 and DONE1 IRQ State Register"]
7 pub DONE0_1_IRQ: crate::RWRegister<u32>,
8 #[doc = "ETC DONE_2 and DONE_ERR IRQ State Register"]
9 pub DONE2_ERR_IRQ: crate::RWRegister<u32>,
10 #[doc = "ETC DMA control Register"]
11 pub DMA_CTRL: crate::RWRegister<u32>,
12 #[doc = "ETC_TRIG Control Register"]
13 pub TRIG0_CTRL: crate::RWRegister<u32>,
14 #[doc = "ETC_TRIG Counter Register"]
15 pub TRIG0_COUNTER: crate::RWRegister<u32>,
16 #[doc = "ETC_TRIG Chain 0/1 Register"]
17 pub TRIG0_CHAIN_1_0: crate::RWRegister<u32>,
18 #[doc = "ETC_TRIG Chain 2/3 Register"]
19 pub TRIG0_CHAIN_3_2: crate::RWRegister<u32>,
20 #[doc = "ETC_TRIG Chain 4/5 Register"]
21 pub TRIG0_CHAIN_5_4: crate::RWRegister<u32>,
22 #[doc = "ETC_TRIG Chain 6/7 Register"]
23 pub TRIG0_CHAIN_7_6: crate::RWRegister<u32>,
24 #[doc = "ETC_TRIG Result Data 1/0 Register"]
25 pub TRIG0_RESULT_1_0: crate::RORegister<u32>,
26 #[doc = "ETC_TRIG Result Data 3/2 Register"]
27 pub TRIG0_RESULT_3_2: crate::RORegister<u32>,
28 #[doc = "ETC_TRIG Result Data 5/4 Register"]
29 pub TRIG0_RESULT_5_4: crate::RORegister<u32>,
30 #[doc = "ETC_TRIG Result Data 7/6 Register"]
31 pub TRIG0_RESULT_7_6: crate::RORegister<u32>,
32 #[doc = "ETC_TRIG Control Register"]
33 pub TRIG1_CTRL: crate::RWRegister<u32>,
34 #[doc = "ETC_TRIG Counter Register"]
35 pub TRIG1_COUNTER: crate::RWRegister<u32>,
36 #[doc = "ETC_TRIG Chain 0/1 Register"]
37 pub TRIG1_CHAIN_1_0: crate::RWRegister<u32>,
38 #[doc = "ETC_TRIG Chain 2/3 Register"]
39 pub TRIG1_CHAIN_3_2: crate::RWRegister<u32>,
40 #[doc = "ETC_TRIG Chain 4/5 Register"]
41 pub TRIG1_CHAIN_5_4: crate::RWRegister<u32>,
42 #[doc = "ETC_TRIG Chain 6/7 Register"]
43 pub TRIG1_CHAIN_7_6: crate::RWRegister<u32>,
44 #[doc = "ETC_TRIG Result Data 1/0 Register"]
45 pub TRIG1_RESULT_1_0: crate::RORegister<u32>,
46 #[doc = "ETC_TRIG Result Data 3/2 Register"]
47 pub TRIG1_RESULT_3_2: crate::RORegister<u32>,
48 #[doc = "ETC_TRIG Result Data 5/4 Register"]
49 pub TRIG1_RESULT_5_4: crate::RORegister<u32>,
50 #[doc = "ETC_TRIG Result Data 7/6 Register"]
51 pub TRIG1_RESULT_7_6: crate::RORegister<u32>,
52 #[doc = "ETC_TRIG Control Register"]
53 pub TRIG2_CTRL: crate::RWRegister<u32>,
54 #[doc = "ETC_TRIG Counter Register"]
55 pub TRIG2_COUNTER: crate::RWRegister<u32>,
56 #[doc = "ETC_TRIG Chain 0/1 Register"]
57 pub TRIG2_CHAIN_1_0: crate::RWRegister<u32>,
58 #[doc = "ETC_TRIG Chain 2/3 Register"]
59 pub TRIG2_CHAIN_3_2: crate::RWRegister<u32>,
60 #[doc = "ETC_TRIG Chain 4/5 Register"]
61 pub TRIG2_CHAIN_5_4: crate::RWRegister<u32>,
62 #[doc = "ETC_TRIG Chain 6/7 Register"]
63 pub TRIG2_CHAIN_7_6: crate::RWRegister<u32>,
64 #[doc = "ETC_TRIG Result Data 1/0 Register"]
65 pub TRIG2_RESULT_1_0: crate::RORegister<u32>,
66 #[doc = "ETC_TRIG Result Data 3/2 Register"]
67 pub TRIG2_RESULT_3_2: crate::RORegister<u32>,
68 #[doc = "ETC_TRIG Result Data 5/4 Register"]
69 pub TRIG2_RESULT_5_4: crate::RORegister<u32>,
70 #[doc = "ETC_TRIG Result Data 7/6 Register"]
71 pub TRIG2_RESULT_7_6: crate::RORegister<u32>,
72 #[doc = "ETC_TRIG Control Register"]
73 pub TRIG3_CTRL: crate::RWRegister<u32>,
74 #[doc = "ETC_TRIG Counter Register"]
75 pub TRIG3_COUNTER: crate::RWRegister<u32>,
76 #[doc = "ETC_TRIG Chain 0/1 Register"]
77 pub TRIG3_CHAIN_1_0: crate::RWRegister<u32>,
78 #[doc = "ETC_TRIG Chain 2/3 Register"]
79 pub TRIG3_CHAIN_3_2: crate::RWRegister<u32>,
80 #[doc = "ETC_TRIG Chain 4/5 Register"]
81 pub TRIG3_CHAIN_5_4: crate::RWRegister<u32>,
82 #[doc = "ETC_TRIG Chain 6/7 Register"]
83 pub TRIG3_CHAIN_7_6: crate::RWRegister<u32>,
84 #[doc = "ETC_TRIG Result Data 1/0 Register"]
85 pub TRIG3_RESULT_1_0: crate::RORegister<u32>,
86 #[doc = "ETC_TRIG Result Data 3/2 Register"]
87 pub TRIG3_RESULT_3_2: crate::RORegister<u32>,
88 #[doc = "ETC_TRIG Result Data 5/4 Register"]
89 pub TRIG3_RESULT_5_4: crate::RORegister<u32>,
90 #[doc = "ETC_TRIG Result Data 7/6 Register"]
91 pub TRIG3_RESULT_7_6: crate::RORegister<u32>,
92}
93#[doc = "ADC_ETC Global Control Register"]
94pub mod CTRL {
95 #[doc = "TRIG enable register"]
96 pub mod TRIG_ENABLE {
97 pub const offset: u32 = 0;
98 pub const mask: u32 = 0xff << offset;
99 pub mod R {}
100 pub mod W {}
101 pub mod RW {}
102 }
103 #[doc = "TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger."]
104 pub mod EXT0_TRIG_ENABLE {
105 pub const offset: u32 = 8;
106 pub const mask: u32 = 0x01 << offset;
107 pub mod R {}
108 pub mod W {}
109 pub mod RW {}
110 }
111 #[doc = "External TSC0 trigger priority, 7 is Highest, 0 is lowest ."]
112 pub mod EXT0_TRIG_PRIORITY {
113 pub const offset: u32 = 9;
114 pub const mask: u32 = 0x07 << offset;
115 pub mod R {}
116 pub mod W {}
117 pub mod RW {}
118 }
119 #[doc = "TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger."]
120 pub mod EXT1_TRIG_ENABLE {
121 pub const offset: u32 = 12;
122 pub const mask: u32 = 0x01 << offset;
123 pub mod R {}
124 pub mod W {}
125 pub mod RW {}
126 }
127 #[doc = "External TSC1 trigger priority, 7 is Highest, 0 is lowest ."]
128 pub mod EXT1_TRIG_PRIORITY {
129 pub const offset: u32 = 13;
130 pub const mask: u32 = 0x07 << offset;
131 pub mod R {}
132 pub mod W {}
133 pub mod RW {}
134 }
135 #[doc = "Pre-divider for trig delay and interval ."]
136 pub mod PRE_DIVIDER {
137 pub const offset: u32 = 16;
138 pub const mask: u32 = 0xff << offset;
139 pub mod R {}
140 pub mod W {}
141 pub mod RW {}
142 }
143 #[doc = "1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared"]
144 pub mod DMA_MODE_SEL {
145 pub const offset: u32 = 29;
146 pub const mask: u32 = 0x01 << offset;
147 pub mod R {}
148 pub mod W {}
149 pub mod RW {}
150 }
151 #[doc = "1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared."]
152 pub mod TSC_BYPASS {
153 pub const offset: u32 = 30;
154 pub const mask: u32 = 0x01 << offset;
155 pub mod R {}
156 pub mod W {}
157 pub mod RW {}
158 }
159 #[doc = "Software reset, high active. When write 1 ,all logical will be reset."]
160 pub mod SOFTRST {
161 pub const offset: u32 = 31;
162 pub const mask: u32 = 0x01 << offset;
163 pub mod R {}
164 pub mod W {}
165 pub mod RW {}
166 }
167}
168#[doc = "ETC DONE0 and DONE1 IRQ State Register"]
169pub mod DONE0_1_IRQ {
170 #[doc = "TRIG0 done0 interrupt detection"]
171 pub mod TRIG0_DONE0 {
172 pub const offset: u32 = 0;
173 pub const mask: u32 = 0x01 << offset;
174 pub mod R {}
175 pub mod W {}
176 pub mod RW {}
177 }
178 #[doc = "TRIG1 done0 interrupt detection"]
179 pub mod TRIG1_DONE0 {
180 pub const offset: u32 = 1;
181 pub const mask: u32 = 0x01 << offset;
182 pub mod R {}
183 pub mod W {}
184 pub mod RW {}
185 }
186 #[doc = "TRIG2 done0 interrupt detection"]
187 pub mod TRIG2_DONE0 {
188 pub const offset: u32 = 2;
189 pub const mask: u32 = 0x01 << offset;
190 pub mod R {}
191 pub mod W {}
192 pub mod RW {}
193 }
194 #[doc = "TRIG3 done0 interrupt detection"]
195 pub mod TRIG3_DONE0 {
196 pub const offset: u32 = 3;
197 pub const mask: u32 = 0x01 << offset;
198 pub mod R {}
199 pub mod W {}
200 pub mod RW {}
201 }
202 #[doc = "TRIG4 done0 interrupt detection"]
203 pub mod TRIG4_DONE0 {
204 pub const offset: u32 = 4;
205 pub const mask: u32 = 0x01 << offset;
206 pub mod R {}
207 pub mod W {}
208 pub mod RW {}
209 }
210 #[doc = "TRIG5 done0 interrupt detection"]
211 pub mod TRIG5_DONE0 {
212 pub const offset: u32 = 5;
213 pub const mask: u32 = 0x01 << offset;
214 pub mod R {}
215 pub mod W {}
216 pub mod RW {}
217 }
218 #[doc = "TRIG6 done0 interrupt detection"]
219 pub mod TRIG6_DONE0 {
220 pub const offset: u32 = 6;
221 pub const mask: u32 = 0x01 << offset;
222 pub mod R {}
223 pub mod W {}
224 pub mod RW {}
225 }
226 #[doc = "TRIG7 done0 interrupt detection"]
227 pub mod TRIG7_DONE0 {
228 pub const offset: u32 = 7;
229 pub const mask: u32 = 0x01 << offset;
230 pub mod R {}
231 pub mod W {}
232 pub mod RW {}
233 }
234 #[doc = "TRIG0 done1 interrupt detection"]
235 pub mod TRIG0_DONE1 {
236 pub const offset: u32 = 16;
237 pub const mask: u32 = 0x01 << offset;
238 pub mod R {}
239 pub mod W {}
240 pub mod RW {}
241 }
242 #[doc = "TRIG1 done1 interrupt detection"]
243 pub mod TRIG1_DONE1 {
244 pub const offset: u32 = 17;
245 pub const mask: u32 = 0x01 << offset;
246 pub mod R {}
247 pub mod W {}
248 pub mod RW {}
249 }
250 #[doc = "TRIG2 done1 interrupt detection"]
251 pub mod TRIG2_DONE1 {
252 pub const offset: u32 = 18;
253 pub const mask: u32 = 0x01 << offset;
254 pub mod R {}
255 pub mod W {}
256 pub mod RW {}
257 }
258 #[doc = "TRIG3 done1 interrupt detection"]
259 pub mod TRIG3_DONE1 {
260 pub const offset: u32 = 19;
261 pub const mask: u32 = 0x01 << offset;
262 pub mod R {}
263 pub mod W {}
264 pub mod RW {}
265 }
266 #[doc = "TRIG4 done1 interrupt detection"]
267 pub mod TRIG4_DONE1 {
268 pub const offset: u32 = 20;
269 pub const mask: u32 = 0x01 << offset;
270 pub mod R {}
271 pub mod W {}
272 pub mod RW {}
273 }
274 #[doc = "TRIG5 done1 interrupt detection"]
275 pub mod TRIG5_DONE1 {
276 pub const offset: u32 = 21;
277 pub const mask: u32 = 0x01 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {}
281 }
282 #[doc = "TRIG6 done1 interrupt detection"]
283 pub mod TRIG6_DONE1 {
284 pub const offset: u32 = 22;
285 pub const mask: u32 = 0x01 << offset;
286 pub mod R {}
287 pub mod W {}
288 pub mod RW {}
289 }
290 #[doc = "TRIG7 done1 interrupt detection"]
291 pub mod TRIG7_DONE1 {
292 pub const offset: u32 = 23;
293 pub const mask: u32 = 0x01 << offset;
294 pub mod R {}
295 pub mod W {}
296 pub mod RW {}
297 }
298}
299#[doc = "ETC DONE_2 and DONE_ERR IRQ State Register"]
300pub mod DONE2_ERR_IRQ {
301 #[doc = "TRIG0 done2 interrupt detection"]
302 pub mod TRIG0_DONE2 {
303 pub const offset: u32 = 0;
304 pub const mask: u32 = 0x01 << offset;
305 pub mod R {}
306 pub mod W {}
307 pub mod RW {}
308 }
309 #[doc = "TRIG1 done2 interrupt detection"]
310 pub mod TRIG1_DONE2 {
311 pub const offset: u32 = 1;
312 pub const mask: u32 = 0x01 << offset;
313 pub mod R {}
314 pub mod W {}
315 pub mod RW {}
316 }
317 #[doc = "TRIG2 done2 interrupt detection"]
318 pub mod TRIG2_DONE2 {
319 pub const offset: u32 = 2;
320 pub const mask: u32 = 0x01 << offset;
321 pub mod R {}
322 pub mod W {}
323 pub mod RW {}
324 }
325 #[doc = "TRIG3 done2 interrupt detection"]
326 pub mod TRIG3_DONE2 {
327 pub const offset: u32 = 3;
328 pub const mask: u32 = 0x01 << offset;
329 pub mod R {}
330 pub mod W {}
331 pub mod RW {}
332 }
333 #[doc = "TRIG4 done2 interrupt detection"]
334 pub mod TRIG4_DONE2 {
335 pub const offset: u32 = 4;
336 pub const mask: u32 = 0x01 << offset;
337 pub mod R {}
338 pub mod W {}
339 pub mod RW {}
340 }
341 #[doc = "TRIG5 done2 interrupt detection"]
342 pub mod TRIG5_DONE2 {
343 pub const offset: u32 = 5;
344 pub const mask: u32 = 0x01 << offset;
345 pub mod R {}
346 pub mod W {}
347 pub mod RW {}
348 }
349 #[doc = "TRIG6 done2 interrupt detection"]
350 pub mod TRIG6_DONE2 {
351 pub const offset: u32 = 6;
352 pub const mask: u32 = 0x01 << offset;
353 pub mod R {}
354 pub mod W {}
355 pub mod RW {}
356 }
357 #[doc = "TRIG7 done2 interrupt detection"]
358 pub mod TRIG7_DONE2 {
359 pub const offset: u32 = 7;
360 pub const mask: u32 = 0x01 << offset;
361 pub mod R {}
362 pub mod W {}
363 pub mod RW {}
364 }
365 #[doc = "TRIG0 done3 interrupt detection"]
366 pub mod TRIG0_DONE3 {
367 pub const offset: u32 = 8;
368 pub const mask: u32 = 0x01 << offset;
369 pub mod R {}
370 pub mod W {}
371 pub mod RW {}
372 }
373 #[doc = "TRIG1 done3 interrupt detection"]
374 pub mod TRIG1_DONE3 {
375 pub const offset: u32 = 9;
376 pub const mask: u32 = 0x01 << offset;
377 pub mod R {}
378 pub mod W {}
379 pub mod RW {}
380 }
381 #[doc = "TRIG2 done3 interrupt detection"]
382 pub mod TRIG2_DONE3 {
383 pub const offset: u32 = 10;
384 pub const mask: u32 = 0x01 << offset;
385 pub mod R {}
386 pub mod W {}
387 pub mod RW {}
388 }
389 #[doc = "TRIG3 done3 interrupt detection"]
390 pub mod TRIG3_DONE3 {
391 pub const offset: u32 = 11;
392 pub const mask: u32 = 0x01 << offset;
393 pub mod R {}
394 pub mod W {}
395 pub mod RW {}
396 }
397 #[doc = "TRIG4 done3 interrupt detection"]
398 pub mod TRIG4_DONE3 {
399 pub const offset: u32 = 12;
400 pub const mask: u32 = 0x01 << offset;
401 pub mod R {}
402 pub mod W {}
403 pub mod RW {}
404 }
405 #[doc = "TRIG5 done3 interrupt detection"]
406 pub mod TRIG5_DONE3 {
407 pub const offset: u32 = 13;
408 pub const mask: u32 = 0x01 << offset;
409 pub mod R {}
410 pub mod W {}
411 pub mod RW {}
412 }
413 #[doc = "TRIG6 done3 interrupt detection"]
414 pub mod TRIG6_DONE3 {
415 pub const offset: u32 = 14;
416 pub const mask: u32 = 0x01 << offset;
417 pub mod R {}
418 pub mod W {}
419 pub mod RW {}
420 }
421 #[doc = "TRIG7 done3 interrupt detection"]
422 pub mod TRIG7_DONE3 {
423 pub const offset: u32 = 15;
424 pub const mask: u32 = 0x01 << offset;
425 pub mod R {}
426 pub mod W {}
427 pub mod RW {}
428 }
429 #[doc = "TRIG0 error interrupt detection"]
430 pub mod TRIG0_ERR {
431 pub const offset: u32 = 16;
432 pub const mask: u32 = 0x01 << offset;
433 pub mod R {}
434 pub mod W {}
435 pub mod RW {}
436 }
437 #[doc = "TRIG1 error interrupt detection"]
438 pub mod TRIG1_ERR {
439 pub const offset: u32 = 17;
440 pub const mask: u32 = 0x01 << offset;
441 pub mod R {}
442 pub mod W {}
443 pub mod RW {}
444 }
445 #[doc = "TRIG2 error interrupt detection"]
446 pub mod TRIG2_ERR {
447 pub const offset: u32 = 18;
448 pub const mask: u32 = 0x01 << offset;
449 pub mod R {}
450 pub mod W {}
451 pub mod RW {}
452 }
453 #[doc = "TRIG3 error interrupt detection"]
454 pub mod TRIG3_ERR {
455 pub const offset: u32 = 19;
456 pub const mask: u32 = 0x01 << offset;
457 pub mod R {}
458 pub mod W {}
459 pub mod RW {}
460 }
461 #[doc = "TRIG4 error interrupt detection"]
462 pub mod TRIG4_ERR {
463 pub const offset: u32 = 20;
464 pub const mask: u32 = 0x01 << offset;
465 pub mod R {}
466 pub mod W {}
467 pub mod RW {}
468 }
469 #[doc = "TRIG5 error interrupt detection"]
470 pub mod TRIG5_ERR {
471 pub const offset: u32 = 21;
472 pub const mask: u32 = 0x01 << offset;
473 pub mod R {}
474 pub mod W {}
475 pub mod RW {}
476 }
477 #[doc = "TRIG6 error interrupt detection"]
478 pub mod TRIG6_ERR {
479 pub const offset: u32 = 22;
480 pub const mask: u32 = 0x01 << offset;
481 pub mod R {}
482 pub mod W {}
483 pub mod RW {}
484 }
485 #[doc = "TRIG7 error interrupt detection"]
486 pub mod TRIG7_ERR {
487 pub const offset: u32 = 23;
488 pub const mask: u32 = 0x01 << offset;
489 pub mod R {}
490 pub mod W {}
491 pub mod RW {}
492 }
493}
494#[doc = "ETC DMA control Register"]
495pub mod DMA_CTRL {
496 #[doc = "When TRIG0 done enable DMA request"]
497 pub mod TRIG0_ENABLE {
498 pub const offset: u32 = 0;
499 pub const mask: u32 = 0x01 << offset;
500 pub mod R {}
501 pub mod W {}
502 pub mod RW {}
503 }
504 #[doc = "When TRIG1 done enable DMA request"]
505 pub mod TRIG1_ENABLE {
506 pub const offset: u32 = 1;
507 pub const mask: u32 = 0x01 << offset;
508 pub mod R {}
509 pub mod W {}
510 pub mod RW {}
511 }
512 #[doc = "When TRIG2 done enable DMA request"]
513 pub mod TRIG2_ENABLE {
514 pub const offset: u32 = 2;
515 pub const mask: u32 = 0x01 << offset;
516 pub mod R {}
517 pub mod W {}
518 pub mod RW {}
519 }
520 #[doc = "When TRIG3 done enable DMA request"]
521 pub mod TRIG3_ENABLE {
522 pub const offset: u32 = 3;
523 pub const mask: u32 = 0x01 << offset;
524 pub mod R {}
525 pub mod W {}
526 pub mod RW {}
527 }
528 #[doc = "When TRIG4 done enable DMA request"]
529 pub mod TRIG4_ENABLE {
530 pub const offset: u32 = 4;
531 pub const mask: u32 = 0x01 << offset;
532 pub mod R {}
533 pub mod W {}
534 pub mod RW {}
535 }
536 #[doc = "When TRIG5 done enable DMA request"]
537 pub mod TRIG5_ENABLE {
538 pub const offset: u32 = 5;
539 pub const mask: u32 = 0x01 << offset;
540 pub mod R {}
541 pub mod W {}
542 pub mod RW {}
543 }
544 #[doc = "When TRIG6 done enable DMA request"]
545 pub mod TRIG6_ENABLE {
546 pub const offset: u32 = 6;
547 pub const mask: u32 = 0x01 << offset;
548 pub mod R {}
549 pub mod W {}
550 pub mod RW {}
551 }
552 #[doc = "When TRIG7 done enable DMA request"]
553 pub mod TRIG7_ENABLE {
554 pub const offset: u32 = 7;
555 pub const mask: u32 = 0x01 << offset;
556 pub mod R {}
557 pub mod W {}
558 pub mod RW {}
559 }
560 #[doc = "When TRIG0 done DMA request detection"]
561 pub mod TRIG0_REQ {
562 pub const offset: u32 = 16;
563 pub const mask: u32 = 0x01 << offset;
564 pub mod R {}
565 pub mod W {}
566 pub mod RW {}
567 }
568 #[doc = "When TRIG1 done DMA request detection"]
569 pub mod TRIG1_REQ {
570 pub const offset: u32 = 17;
571 pub const mask: u32 = 0x01 << offset;
572 pub mod R {}
573 pub mod W {}
574 pub mod RW {}
575 }
576 #[doc = "When TRIG2 done DMA request detection"]
577 pub mod TRIG2_REQ {
578 pub const offset: u32 = 18;
579 pub const mask: u32 = 0x01 << offset;
580 pub mod R {}
581 pub mod W {}
582 pub mod RW {}
583 }
584 #[doc = "When TRIG3 done DMA request detection"]
585 pub mod TRIG3_REQ {
586 pub const offset: u32 = 19;
587 pub const mask: u32 = 0x01 << offset;
588 pub mod R {}
589 pub mod W {}
590 pub mod RW {}
591 }
592 #[doc = "When TRIG4 done DMA request detection"]
593 pub mod TRIG4_REQ {
594 pub const offset: u32 = 20;
595 pub const mask: u32 = 0x01 << offset;
596 pub mod R {}
597 pub mod W {}
598 pub mod RW {}
599 }
600 #[doc = "When TRIG5 done DMA request detection"]
601 pub mod TRIG5_REQ {
602 pub const offset: u32 = 21;
603 pub const mask: u32 = 0x01 << offset;
604 pub mod R {}
605 pub mod W {}
606 pub mod RW {}
607 }
608 #[doc = "When TRIG6 done DMA request detection"]
609 pub mod TRIG6_REQ {
610 pub const offset: u32 = 22;
611 pub const mask: u32 = 0x01 << offset;
612 pub mod R {}
613 pub mod W {}
614 pub mod RW {}
615 }
616 #[doc = "When TRIG7 done DMA request detection"]
617 pub mod TRIG7_REQ {
618 pub const offset: u32 = 23;
619 pub const mask: u32 = 0x01 << offset;
620 pub mod R {}
621 pub mod W {}
622 pub mod RW {}
623 }
624}
625#[doc = "ETC_TRIG Control Register"]
626pub mod TRIG0_CTRL {
627 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
628 pub mod SW_TRIG {
629 pub const offset: u32 = 0;
630 pub const mask: u32 = 0x01 << offset;
631 pub mod R {}
632 pub mod W {}
633 pub mod RW {}
634 }
635 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
636 pub mod TRIG_MODE {
637 pub const offset: u32 = 4;
638 pub const mask: u32 = 0x01 << offset;
639 pub mod R {}
640 pub mod W {}
641 pub mod RW {}
642 }
643 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
644 pub mod TRIG_CHAIN {
645 pub const offset: u32 = 8;
646 pub const mask: u32 = 0x07 << offset;
647 pub mod R {}
648 pub mod W {}
649 pub mod RW {}
650 }
651 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
652 pub mod TRIG_PRIORITY {
653 pub const offset: u32 = 12;
654 pub const mask: u32 = 0x07 << offset;
655 pub mod R {}
656 pub mod W {}
657 pub mod RW {}
658 }
659 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
660 pub mod SYNC_MODE {
661 pub const offset: u32 = 16;
662 pub const mask: u32 = 0x01 << offset;
663 pub mod R {}
664 pub mod W {}
665 pub mod RW {}
666 }
667 #[doc = "CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits"]
668 pub mod CHAINX_DONE {
669 pub const offset: u32 = 24;
670 pub const mask: u32 = 0xff << offset;
671 pub mod R {}
672 pub mod W {}
673 pub mod RW {}
674 }
675}
676#[doc = "ETC_TRIG Counter Register"]
677pub mod TRIG0_COUNTER {
678 #[doc = "TRIGGER initial delay counter"]
679 pub mod INIT_DELAY {
680 pub const offset: u32 = 0;
681 pub const mask: u32 = 0xffff << offset;
682 pub mod R {}
683 pub mod W {}
684 pub mod RW {}
685 }
686 #[doc = "TRIGGER sampling interval counter"]
687 pub mod SAMPLE_INTERVAL {
688 pub const offset: u32 = 16;
689 pub const mask: u32 = 0xffff << offset;
690 pub mod R {}
691 pub mod W {}
692 pub mod RW {}
693 }
694}
695#[doc = "ETC_TRIG Chain 0/1 Register"]
696pub mod TRIG0_CHAIN_1_0 {
697 #[doc = "CHAIN0 CSEL ADC channel selection"]
698 pub mod CSEL0 {
699 pub const offset: u32 = 0;
700 pub const mask: u32 = 0x0f << offset;
701 pub mod R {}
702 pub mod W {}
703 pub mod RW {}
704 }
705 #[doc = "CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
706 pub mod HWTS0 {
707 pub const offset: u32 = 4;
708 pub const mask: u32 = 0xff << offset;
709 pub mod R {}
710 pub mod W {}
711 pub mod RW {}
712 }
713 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
714 pub mod B2B0 {
715 pub const offset: u32 = 12;
716 pub const mask: u32 = 0x01 << offset;
717 pub mod R {}
718 pub mod W {}
719 pub mod RW {}
720 }
721 #[doc = "CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
722 pub mod IE0 {
723 pub const offset: u32 = 13;
724 pub const mask: u32 = 0x03 << offset;
725 pub mod R {}
726 pub mod W {}
727 pub mod RW {}
728 }
729 #[doc = "IRQ enable"]
730 pub mod IE0_EN {
731 pub const offset: u32 = 15;
732 pub const mask: u32 = 0x01 << offset;
733 pub mod R {}
734 pub mod W {}
735 pub mod RW {}
736 }
737 #[doc = "CHAIN1 CSEL ADC channel selection"]
738 pub mod CSEL1 {
739 pub const offset: u32 = 16;
740 pub const mask: u32 = 0x0f << offset;
741 pub mod R {}
742 pub mod W {}
743 pub mod RW {}
744 }
745 #[doc = "CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
746 pub mod HWTS1 {
747 pub const offset: u32 = 20;
748 pub const mask: u32 = 0xff << offset;
749 pub mod R {}
750 pub mod W {}
751 pub mod RW {}
752 }
753 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
754 pub mod B2B1 {
755 pub const offset: u32 = 28;
756 pub const mask: u32 = 0x01 << offset;
757 pub mod R {}
758 pub mod W {}
759 pub mod RW {}
760 }
761 #[doc = "CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
762 pub mod IE1 {
763 pub const offset: u32 = 29;
764 pub const mask: u32 = 0x03 << offset;
765 pub mod R {}
766 pub mod W {}
767 pub mod RW {}
768 }
769 #[doc = "IRQ enable"]
770 pub mod IE1_EN {
771 pub const offset: u32 = 31;
772 pub const mask: u32 = 0x01 << offset;
773 pub mod R {}
774 pub mod W {}
775 pub mod RW {}
776 }
777}
778#[doc = "ETC_TRIG Chain 2/3 Register"]
779pub mod TRIG0_CHAIN_3_2 {
780 #[doc = "CHAIN2 CSEL"]
781 pub mod CSEL2 {
782 pub const offset: u32 = 0;
783 pub const mask: u32 = 0x0f << offset;
784 pub mod R {}
785 pub mod W {}
786 pub mod RW {}
787 }
788 #[doc = "CHAIN2 HWTS"]
789 pub mod HWTS2 {
790 pub const offset: u32 = 4;
791 pub const mask: u32 = 0xff << offset;
792 pub mod R {}
793 pub mod W {}
794 pub mod RW {}
795 }
796 #[doc = "CHAIN2 B2B"]
797 pub mod B2B2 {
798 pub const offset: u32 = 12;
799 pub const mask: u32 = 0x01 << offset;
800 pub mod R {}
801 pub mod W {}
802 pub mod RW {}
803 }
804 #[doc = "CHAIN2 IE"]
805 pub mod IE2 {
806 pub const offset: u32 = 13;
807 pub const mask: u32 = 0x03 << offset;
808 pub mod R {}
809 pub mod W {}
810 pub mod RW {}
811 }
812 #[doc = "IRQ enable"]
813 pub mod IE2_EN {
814 pub const offset: u32 = 15;
815 pub const mask: u32 = 0x01 << offset;
816 pub mod R {}
817 pub mod W {}
818 pub mod RW {}
819 }
820 #[doc = "CHAIN3 CSEL"]
821 pub mod CSEL3 {
822 pub const offset: u32 = 16;
823 pub const mask: u32 = 0x0f << offset;
824 pub mod R {}
825 pub mod W {}
826 pub mod RW {}
827 }
828 #[doc = "CHAIN3 HWTS"]
829 pub mod HWTS3 {
830 pub const offset: u32 = 20;
831 pub const mask: u32 = 0xff << offset;
832 pub mod R {}
833 pub mod W {}
834 pub mod RW {}
835 }
836 #[doc = "CHAIN3 B2B"]
837 pub mod B2B3 {
838 pub const offset: u32 = 28;
839 pub const mask: u32 = 0x01 << offset;
840 pub mod R {}
841 pub mod W {}
842 pub mod RW {}
843 }
844 #[doc = "CHAIN3 IE"]
845 pub mod IE3 {
846 pub const offset: u32 = 29;
847 pub const mask: u32 = 0x03 << offset;
848 pub mod R {}
849 pub mod W {}
850 pub mod RW {}
851 }
852 #[doc = "IRQ enable"]
853 pub mod IE3_EN {
854 pub const offset: u32 = 31;
855 pub const mask: u32 = 0x01 << offset;
856 pub mod R {}
857 pub mod W {}
858 pub mod RW {}
859 }
860}
861#[doc = "ETC_TRIG Chain 4/5 Register"]
862pub mod TRIG0_CHAIN_5_4 {
863 #[doc = "CHAIN4 CSEL"]
864 pub mod CSEL4 {
865 pub const offset: u32 = 0;
866 pub const mask: u32 = 0x0f << offset;
867 pub mod R {}
868 pub mod W {}
869 pub mod RW {}
870 }
871 #[doc = "CHAIN4 HWTS"]
872 pub mod HWTS4 {
873 pub const offset: u32 = 4;
874 pub const mask: u32 = 0xff << offset;
875 pub mod R {}
876 pub mod W {}
877 pub mod RW {}
878 }
879 #[doc = "CHAIN4 B2B"]
880 pub mod B2B4 {
881 pub const offset: u32 = 12;
882 pub const mask: u32 = 0x01 << offset;
883 pub mod R {}
884 pub mod W {}
885 pub mod RW {}
886 }
887 #[doc = "CHAIN4 IE"]
888 pub mod IE4 {
889 pub const offset: u32 = 13;
890 pub const mask: u32 = 0x03 << offset;
891 pub mod R {}
892 pub mod W {}
893 pub mod RW {}
894 }
895 #[doc = "IRQ enable"]
896 pub mod IE4_EN {
897 pub const offset: u32 = 15;
898 pub const mask: u32 = 0x01 << offset;
899 pub mod R {}
900 pub mod W {}
901 pub mod RW {}
902 }
903 #[doc = "CHAIN5 CSEL"]
904 pub mod CSEL5 {
905 pub const offset: u32 = 16;
906 pub const mask: u32 = 0x0f << offset;
907 pub mod R {}
908 pub mod W {}
909 pub mod RW {}
910 }
911 #[doc = "CHAIN5 HWTS"]
912 pub mod HWTS5 {
913 pub const offset: u32 = 20;
914 pub const mask: u32 = 0xff << offset;
915 pub mod R {}
916 pub mod W {}
917 pub mod RW {}
918 }
919 #[doc = "CHAIN5 B2B"]
920 pub mod B2B5 {
921 pub const offset: u32 = 28;
922 pub const mask: u32 = 0x01 << offset;
923 pub mod R {}
924 pub mod W {}
925 pub mod RW {}
926 }
927 #[doc = "CHAIN5 IE"]
928 pub mod IE5 {
929 pub const offset: u32 = 29;
930 pub const mask: u32 = 0x03 << offset;
931 pub mod R {}
932 pub mod W {}
933 pub mod RW {}
934 }
935 #[doc = "IRQ enable"]
936 pub mod IE5_EN {
937 pub const offset: u32 = 31;
938 pub const mask: u32 = 0x01 << offset;
939 pub mod R {}
940 pub mod W {}
941 pub mod RW {}
942 }
943}
944#[doc = "ETC_TRIG Chain 6/7 Register"]
945pub mod TRIG0_CHAIN_7_6 {
946 #[doc = "CHAIN6 CSEL"]
947 pub mod CSEL6 {
948 pub const offset: u32 = 0;
949 pub const mask: u32 = 0x0f << offset;
950 pub mod R {}
951 pub mod W {}
952 pub mod RW {}
953 }
954 #[doc = "CHAIN6 HWTS"]
955 pub mod HWTS6 {
956 pub const offset: u32 = 4;
957 pub const mask: u32 = 0xff << offset;
958 pub mod R {}
959 pub mod W {}
960 pub mod RW {}
961 }
962 #[doc = "CHAIN6 B2B"]
963 pub mod B2B6 {
964 pub const offset: u32 = 12;
965 pub const mask: u32 = 0x01 << offset;
966 pub mod R {}
967 pub mod W {}
968 pub mod RW {}
969 }
970 #[doc = "CHAIN6 IE"]
971 pub mod IE6 {
972 pub const offset: u32 = 13;
973 pub const mask: u32 = 0x03 << offset;
974 pub mod R {}
975 pub mod W {}
976 pub mod RW {}
977 }
978 #[doc = "IRQ enable"]
979 pub mod IE6_EN {
980 pub const offset: u32 = 15;
981 pub const mask: u32 = 0x01 << offset;
982 pub mod R {}
983 pub mod W {}
984 pub mod RW {}
985 }
986 #[doc = "CHAIN7 CSEL"]
987 pub mod CSEL7 {
988 pub const offset: u32 = 16;
989 pub const mask: u32 = 0x0f << offset;
990 pub mod R {}
991 pub mod W {}
992 pub mod RW {}
993 }
994 #[doc = "CHAIN7 HWTS"]
995 pub mod HWTS7 {
996 pub const offset: u32 = 20;
997 pub const mask: u32 = 0xff << offset;
998 pub mod R {}
999 pub mod W {}
1000 pub mod RW {}
1001 }
1002 #[doc = "CHAIN7 B2B"]
1003 pub mod B2B7 {
1004 pub const offset: u32 = 28;
1005 pub const mask: u32 = 0x01 << offset;
1006 pub mod R {}
1007 pub mod W {}
1008 pub mod RW {}
1009 }
1010 #[doc = "CHAIN7 IE"]
1011 pub mod IE7 {
1012 pub const offset: u32 = 29;
1013 pub const mask: u32 = 0x03 << offset;
1014 pub mod R {}
1015 pub mod W {}
1016 pub mod RW {}
1017 }
1018 #[doc = "IRQ enable"]
1019 pub mod IE7_EN {
1020 pub const offset: u32 = 31;
1021 pub const mask: u32 = 0x01 << offset;
1022 pub mod R {}
1023 pub mod W {}
1024 pub mod RW {}
1025 }
1026}
1027#[doc = "ETC_TRIG Result Data 1/0 Register"]
1028pub mod TRIG0_RESULT_1_0 {
1029 #[doc = "Result DATA0"]
1030 pub mod DATA0 {
1031 pub const offset: u32 = 0;
1032 pub const mask: u32 = 0x0fff << offset;
1033 pub mod R {}
1034 pub mod W {}
1035 pub mod RW {}
1036 }
1037 #[doc = "Result DATA1"]
1038 pub mod DATA1 {
1039 pub const offset: u32 = 16;
1040 pub const mask: u32 = 0x0fff << offset;
1041 pub mod R {}
1042 pub mod W {}
1043 pub mod RW {}
1044 }
1045}
1046#[doc = "ETC_TRIG Result Data 3/2 Register"]
1047pub mod TRIG0_RESULT_3_2 {
1048 #[doc = "Result DATA2"]
1049 pub mod DATA2 {
1050 pub const offset: u32 = 0;
1051 pub const mask: u32 = 0x0fff << offset;
1052 pub mod R {}
1053 pub mod W {}
1054 pub mod RW {}
1055 }
1056 #[doc = "Result DATA3"]
1057 pub mod DATA3 {
1058 pub const offset: u32 = 16;
1059 pub const mask: u32 = 0x0fff << offset;
1060 pub mod R {}
1061 pub mod W {}
1062 pub mod RW {}
1063 }
1064}
1065#[doc = "ETC_TRIG Result Data 5/4 Register"]
1066pub mod TRIG0_RESULT_5_4 {
1067 #[doc = "Result DATA4"]
1068 pub mod DATA4 {
1069 pub const offset: u32 = 0;
1070 pub const mask: u32 = 0x0fff << offset;
1071 pub mod R {}
1072 pub mod W {}
1073 pub mod RW {}
1074 }
1075 #[doc = "Result DATA5"]
1076 pub mod DATA5 {
1077 pub const offset: u32 = 16;
1078 pub const mask: u32 = 0x0fff << offset;
1079 pub mod R {}
1080 pub mod W {}
1081 pub mod RW {}
1082 }
1083}
1084#[doc = "ETC_TRIG Result Data 7/6 Register"]
1085pub mod TRIG0_RESULT_7_6 {
1086 #[doc = "Result DATA6"]
1087 pub mod DATA6 {
1088 pub const offset: u32 = 0;
1089 pub const mask: u32 = 0x0fff << offset;
1090 pub mod R {}
1091 pub mod W {}
1092 pub mod RW {}
1093 }
1094 #[doc = "Result DATA7"]
1095 pub mod DATA7 {
1096 pub const offset: u32 = 16;
1097 pub const mask: u32 = 0x0fff << offset;
1098 pub mod R {}
1099 pub mod W {}
1100 pub mod RW {}
1101 }
1102}
1103#[doc = "ETC_TRIG Control Register"]
1104pub mod TRIG1_CTRL {
1105 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
1106 pub mod SW_TRIG {
1107 pub const offset: u32 = 0;
1108 pub const mask: u32 = 0x01 << offset;
1109 pub mod R {}
1110 pub mod W {}
1111 pub mod RW {}
1112 }
1113 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
1114 pub mod TRIG_MODE {
1115 pub const offset: u32 = 4;
1116 pub const mask: u32 = 0x01 << offset;
1117 pub mod R {}
1118 pub mod W {}
1119 pub mod RW {}
1120 }
1121 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
1122 pub mod TRIG_CHAIN {
1123 pub const offset: u32 = 8;
1124 pub const mask: u32 = 0x07 << offset;
1125 pub mod R {}
1126 pub mod W {}
1127 pub mod RW {}
1128 }
1129 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
1130 pub mod TRIG_PRIORITY {
1131 pub const offset: u32 = 12;
1132 pub const mask: u32 = 0x07 << offset;
1133 pub mod R {}
1134 pub mod W {}
1135 pub mod RW {}
1136 }
1137 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
1138 pub mod SYNC_MODE {
1139 pub const offset: u32 = 16;
1140 pub const mask: u32 = 0x01 << offset;
1141 pub mod R {}
1142 pub mod W {}
1143 pub mod RW {}
1144 }
1145 #[doc = "CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits"]
1146 pub mod CHAINX_DONE {
1147 pub const offset: u32 = 24;
1148 pub const mask: u32 = 0xff << offset;
1149 pub mod R {}
1150 pub mod W {}
1151 pub mod RW {}
1152 }
1153}
1154#[doc = "ETC_TRIG Counter Register"]
1155pub mod TRIG1_COUNTER {
1156 #[doc = "TRIGGER initial delay counter"]
1157 pub mod INIT_DELAY {
1158 pub const offset: u32 = 0;
1159 pub const mask: u32 = 0xffff << offset;
1160 pub mod R {}
1161 pub mod W {}
1162 pub mod RW {}
1163 }
1164 #[doc = "TRIGGER sampling interval counter"]
1165 pub mod SAMPLE_INTERVAL {
1166 pub const offset: u32 = 16;
1167 pub const mask: u32 = 0xffff << offset;
1168 pub mod R {}
1169 pub mod W {}
1170 pub mod RW {}
1171 }
1172}
1173#[doc = "ETC_TRIG Chain 0/1 Register"]
1174pub mod TRIG1_CHAIN_1_0 {
1175 #[doc = "CHAIN0 CSEL ADC channel selection"]
1176 pub mod CSEL0 {
1177 pub const offset: u32 = 0;
1178 pub const mask: u32 = 0x0f << offset;
1179 pub mod R {}
1180 pub mod W {}
1181 pub mod RW {}
1182 }
1183 #[doc = "CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
1184 pub mod HWTS0 {
1185 pub const offset: u32 = 4;
1186 pub const mask: u32 = 0xff << offset;
1187 pub mod R {}
1188 pub mod W {}
1189 pub mod RW {}
1190 }
1191 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1192 pub mod B2B0 {
1193 pub const offset: u32 = 12;
1194 pub const mask: u32 = 0x01 << offset;
1195 pub mod R {}
1196 pub mod W {}
1197 pub mod RW {}
1198 }
1199 #[doc = "CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
1200 pub mod IE0 {
1201 pub const offset: u32 = 13;
1202 pub const mask: u32 = 0x03 << offset;
1203 pub mod R {}
1204 pub mod W {}
1205 pub mod RW {}
1206 }
1207 #[doc = "IRQ enable"]
1208 pub mod IE0_EN {
1209 pub const offset: u32 = 15;
1210 pub const mask: u32 = 0x01 << offset;
1211 pub mod R {}
1212 pub mod W {}
1213 pub mod RW {}
1214 }
1215 #[doc = "CHAIN1 CSEL ADC channel selection"]
1216 pub mod CSEL1 {
1217 pub const offset: u32 = 16;
1218 pub const mask: u32 = 0x0f << offset;
1219 pub mod R {}
1220 pub mod W {}
1221 pub mod RW {}
1222 }
1223 #[doc = "CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
1224 pub mod HWTS1 {
1225 pub const offset: u32 = 20;
1226 pub const mask: u32 = 0xff << offset;
1227 pub mod R {}
1228 pub mod W {}
1229 pub mod RW {}
1230 }
1231 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1232 pub mod B2B1 {
1233 pub const offset: u32 = 28;
1234 pub const mask: u32 = 0x01 << offset;
1235 pub mod R {}
1236 pub mod W {}
1237 pub mod RW {}
1238 }
1239 #[doc = "CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
1240 pub mod IE1 {
1241 pub const offset: u32 = 29;
1242 pub const mask: u32 = 0x03 << offset;
1243 pub mod R {}
1244 pub mod W {}
1245 pub mod RW {}
1246 }
1247 #[doc = "IRQ enable"]
1248 pub mod IE1_EN {
1249 pub const offset: u32 = 31;
1250 pub const mask: u32 = 0x01 << offset;
1251 pub mod R {}
1252 pub mod W {}
1253 pub mod RW {}
1254 }
1255}
1256#[doc = "ETC_TRIG Chain 2/3 Register"]
1257pub mod TRIG1_CHAIN_3_2 {
1258 #[doc = "CHAIN2 CSEL"]
1259 pub mod CSEL2 {
1260 pub const offset: u32 = 0;
1261 pub const mask: u32 = 0x0f << offset;
1262 pub mod R {}
1263 pub mod W {}
1264 pub mod RW {}
1265 }
1266 #[doc = "CHAIN2 HWTS"]
1267 pub mod HWTS2 {
1268 pub const offset: u32 = 4;
1269 pub const mask: u32 = 0xff << offset;
1270 pub mod R {}
1271 pub mod W {}
1272 pub mod RW {}
1273 }
1274 #[doc = "CHAIN2 B2B"]
1275 pub mod B2B2 {
1276 pub const offset: u32 = 12;
1277 pub const mask: u32 = 0x01 << offset;
1278 pub mod R {}
1279 pub mod W {}
1280 pub mod RW {}
1281 }
1282 #[doc = "CHAIN2 IE"]
1283 pub mod IE2 {
1284 pub const offset: u32 = 13;
1285 pub const mask: u32 = 0x03 << offset;
1286 pub mod R {}
1287 pub mod W {}
1288 pub mod RW {}
1289 }
1290 #[doc = "IRQ enable"]
1291 pub mod IE2_EN {
1292 pub const offset: u32 = 15;
1293 pub const mask: u32 = 0x01 << offset;
1294 pub mod R {}
1295 pub mod W {}
1296 pub mod RW {}
1297 }
1298 #[doc = "CHAIN3 CSEL"]
1299 pub mod CSEL3 {
1300 pub const offset: u32 = 16;
1301 pub const mask: u32 = 0x0f << offset;
1302 pub mod R {}
1303 pub mod W {}
1304 pub mod RW {}
1305 }
1306 #[doc = "CHAIN3 HWTS"]
1307 pub mod HWTS3 {
1308 pub const offset: u32 = 20;
1309 pub const mask: u32 = 0xff << offset;
1310 pub mod R {}
1311 pub mod W {}
1312 pub mod RW {}
1313 }
1314 #[doc = "CHAIN3 B2B"]
1315 pub mod B2B3 {
1316 pub const offset: u32 = 28;
1317 pub const mask: u32 = 0x01 << offset;
1318 pub mod R {}
1319 pub mod W {}
1320 pub mod RW {}
1321 }
1322 #[doc = "CHAIN3 IE"]
1323 pub mod IE3 {
1324 pub const offset: u32 = 29;
1325 pub const mask: u32 = 0x03 << offset;
1326 pub mod R {}
1327 pub mod W {}
1328 pub mod RW {}
1329 }
1330 #[doc = "IRQ enable"]
1331 pub mod IE3_EN {
1332 pub const offset: u32 = 31;
1333 pub const mask: u32 = 0x01 << offset;
1334 pub mod R {}
1335 pub mod W {}
1336 pub mod RW {}
1337 }
1338}
1339#[doc = "ETC_TRIG Chain 4/5 Register"]
1340pub mod TRIG1_CHAIN_5_4 {
1341 #[doc = "CHAIN4 CSEL"]
1342 pub mod CSEL4 {
1343 pub const offset: u32 = 0;
1344 pub const mask: u32 = 0x0f << offset;
1345 pub mod R {}
1346 pub mod W {}
1347 pub mod RW {}
1348 }
1349 #[doc = "CHAIN4 HWTS"]
1350 pub mod HWTS4 {
1351 pub const offset: u32 = 4;
1352 pub const mask: u32 = 0xff << offset;
1353 pub mod R {}
1354 pub mod W {}
1355 pub mod RW {}
1356 }
1357 #[doc = "CHAIN4 B2B"]
1358 pub mod B2B4 {
1359 pub const offset: u32 = 12;
1360 pub const mask: u32 = 0x01 << offset;
1361 pub mod R {}
1362 pub mod W {}
1363 pub mod RW {}
1364 }
1365 #[doc = "CHAIN4 IE"]
1366 pub mod IE4 {
1367 pub const offset: u32 = 13;
1368 pub const mask: u32 = 0x03 << offset;
1369 pub mod R {}
1370 pub mod W {}
1371 pub mod RW {}
1372 }
1373 #[doc = "IRQ enable"]
1374 pub mod IE4_EN {
1375 pub const offset: u32 = 15;
1376 pub const mask: u32 = 0x01 << offset;
1377 pub mod R {}
1378 pub mod W {}
1379 pub mod RW {}
1380 }
1381 #[doc = "CHAIN5 CSEL"]
1382 pub mod CSEL5 {
1383 pub const offset: u32 = 16;
1384 pub const mask: u32 = 0x0f << offset;
1385 pub mod R {}
1386 pub mod W {}
1387 pub mod RW {}
1388 }
1389 #[doc = "CHAIN5 HWTS"]
1390 pub mod HWTS5 {
1391 pub const offset: u32 = 20;
1392 pub const mask: u32 = 0xff << offset;
1393 pub mod R {}
1394 pub mod W {}
1395 pub mod RW {}
1396 }
1397 #[doc = "CHAIN5 B2B"]
1398 pub mod B2B5 {
1399 pub const offset: u32 = 28;
1400 pub const mask: u32 = 0x01 << offset;
1401 pub mod R {}
1402 pub mod W {}
1403 pub mod RW {}
1404 }
1405 #[doc = "CHAIN5 IE"]
1406 pub mod IE5 {
1407 pub const offset: u32 = 29;
1408 pub const mask: u32 = 0x03 << offset;
1409 pub mod R {}
1410 pub mod W {}
1411 pub mod RW {}
1412 }
1413 #[doc = "IRQ enable"]
1414 pub mod IE5_EN {
1415 pub const offset: u32 = 31;
1416 pub const mask: u32 = 0x01 << offset;
1417 pub mod R {}
1418 pub mod W {}
1419 pub mod RW {}
1420 }
1421}
1422#[doc = "ETC_TRIG Chain 6/7 Register"]
1423pub mod TRIG1_CHAIN_7_6 {
1424 #[doc = "CHAIN6 CSEL"]
1425 pub mod CSEL6 {
1426 pub const offset: u32 = 0;
1427 pub const mask: u32 = 0x0f << offset;
1428 pub mod R {}
1429 pub mod W {}
1430 pub mod RW {}
1431 }
1432 #[doc = "CHAIN6 HWTS"]
1433 pub mod HWTS6 {
1434 pub const offset: u32 = 4;
1435 pub const mask: u32 = 0xff << offset;
1436 pub mod R {}
1437 pub mod W {}
1438 pub mod RW {}
1439 }
1440 #[doc = "CHAIN6 B2B"]
1441 pub mod B2B6 {
1442 pub const offset: u32 = 12;
1443 pub const mask: u32 = 0x01 << offset;
1444 pub mod R {}
1445 pub mod W {}
1446 pub mod RW {}
1447 }
1448 #[doc = "CHAIN6 IE"]
1449 pub mod IE6 {
1450 pub const offset: u32 = 13;
1451 pub const mask: u32 = 0x03 << offset;
1452 pub mod R {}
1453 pub mod W {}
1454 pub mod RW {}
1455 }
1456 #[doc = "IRQ enable"]
1457 pub mod IE6_EN {
1458 pub const offset: u32 = 15;
1459 pub const mask: u32 = 0x01 << offset;
1460 pub mod R {}
1461 pub mod W {}
1462 pub mod RW {}
1463 }
1464 #[doc = "CHAIN7 CSEL"]
1465 pub mod CSEL7 {
1466 pub const offset: u32 = 16;
1467 pub const mask: u32 = 0x0f << offset;
1468 pub mod R {}
1469 pub mod W {}
1470 pub mod RW {}
1471 }
1472 #[doc = "CHAIN7 HWTS"]
1473 pub mod HWTS7 {
1474 pub const offset: u32 = 20;
1475 pub const mask: u32 = 0xff << offset;
1476 pub mod R {}
1477 pub mod W {}
1478 pub mod RW {}
1479 }
1480 #[doc = "CHAIN7 B2B"]
1481 pub mod B2B7 {
1482 pub const offset: u32 = 28;
1483 pub const mask: u32 = 0x01 << offset;
1484 pub mod R {}
1485 pub mod W {}
1486 pub mod RW {}
1487 }
1488 #[doc = "CHAIN7 IE"]
1489 pub mod IE7 {
1490 pub const offset: u32 = 29;
1491 pub const mask: u32 = 0x03 << offset;
1492 pub mod R {}
1493 pub mod W {}
1494 pub mod RW {}
1495 }
1496 #[doc = "IRQ enable"]
1497 pub mod IE7_EN {
1498 pub const offset: u32 = 31;
1499 pub const mask: u32 = 0x01 << offset;
1500 pub mod R {}
1501 pub mod W {}
1502 pub mod RW {}
1503 }
1504}
1505#[doc = "ETC_TRIG Result Data 1/0 Register"]
1506pub mod TRIG1_RESULT_1_0 {
1507 #[doc = "Result DATA0"]
1508 pub mod DATA0 {
1509 pub const offset: u32 = 0;
1510 pub const mask: u32 = 0x0fff << offset;
1511 pub mod R {}
1512 pub mod W {}
1513 pub mod RW {}
1514 }
1515 #[doc = "Result DATA1"]
1516 pub mod DATA1 {
1517 pub const offset: u32 = 16;
1518 pub const mask: u32 = 0x0fff << offset;
1519 pub mod R {}
1520 pub mod W {}
1521 pub mod RW {}
1522 }
1523}
1524#[doc = "ETC_TRIG Result Data 3/2 Register"]
1525pub mod TRIG1_RESULT_3_2 {
1526 #[doc = "Result DATA2"]
1527 pub mod DATA2 {
1528 pub const offset: u32 = 0;
1529 pub const mask: u32 = 0x0fff << offset;
1530 pub mod R {}
1531 pub mod W {}
1532 pub mod RW {}
1533 }
1534 #[doc = "Result DATA3"]
1535 pub mod DATA3 {
1536 pub const offset: u32 = 16;
1537 pub const mask: u32 = 0x0fff << offset;
1538 pub mod R {}
1539 pub mod W {}
1540 pub mod RW {}
1541 }
1542}
1543#[doc = "ETC_TRIG Result Data 5/4 Register"]
1544pub mod TRIG1_RESULT_5_4 {
1545 #[doc = "Result DATA4"]
1546 pub mod DATA4 {
1547 pub const offset: u32 = 0;
1548 pub const mask: u32 = 0x0fff << offset;
1549 pub mod R {}
1550 pub mod W {}
1551 pub mod RW {}
1552 }
1553 #[doc = "Result DATA5"]
1554 pub mod DATA5 {
1555 pub const offset: u32 = 16;
1556 pub const mask: u32 = 0x0fff << offset;
1557 pub mod R {}
1558 pub mod W {}
1559 pub mod RW {}
1560 }
1561}
1562#[doc = "ETC_TRIG Result Data 7/6 Register"]
1563pub mod TRIG1_RESULT_7_6 {
1564 #[doc = "Result DATA6"]
1565 pub mod DATA6 {
1566 pub const offset: u32 = 0;
1567 pub const mask: u32 = 0x0fff << offset;
1568 pub mod R {}
1569 pub mod W {}
1570 pub mod RW {}
1571 }
1572 #[doc = "Result DATA7"]
1573 pub mod DATA7 {
1574 pub const offset: u32 = 16;
1575 pub const mask: u32 = 0x0fff << offset;
1576 pub mod R {}
1577 pub mod W {}
1578 pub mod RW {}
1579 }
1580}
1581#[doc = "ETC_TRIG Control Register"]
1582pub mod TRIG2_CTRL {
1583 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
1584 pub mod SW_TRIG {
1585 pub const offset: u32 = 0;
1586 pub const mask: u32 = 0x01 << offset;
1587 pub mod R {}
1588 pub mod W {}
1589 pub mod RW {}
1590 }
1591 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
1592 pub mod TRIG_MODE {
1593 pub const offset: u32 = 4;
1594 pub const mask: u32 = 0x01 << offset;
1595 pub mod R {}
1596 pub mod W {}
1597 pub mod RW {}
1598 }
1599 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
1600 pub mod TRIG_CHAIN {
1601 pub const offset: u32 = 8;
1602 pub const mask: u32 = 0x07 << offset;
1603 pub mod R {}
1604 pub mod W {}
1605 pub mod RW {}
1606 }
1607 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
1608 pub mod TRIG_PRIORITY {
1609 pub const offset: u32 = 12;
1610 pub const mask: u32 = 0x07 << offset;
1611 pub mod R {}
1612 pub mod W {}
1613 pub mod RW {}
1614 }
1615 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
1616 pub mod SYNC_MODE {
1617 pub const offset: u32 = 16;
1618 pub const mask: u32 = 0x01 << offset;
1619 pub mod R {}
1620 pub mod W {}
1621 pub mod RW {}
1622 }
1623 #[doc = "CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits"]
1624 pub mod CHAINX_DONE {
1625 pub const offset: u32 = 24;
1626 pub const mask: u32 = 0xff << offset;
1627 pub mod R {}
1628 pub mod W {}
1629 pub mod RW {}
1630 }
1631}
1632#[doc = "ETC_TRIG Counter Register"]
1633pub mod TRIG2_COUNTER {
1634 #[doc = "TRIGGER initial delay counter"]
1635 pub mod INIT_DELAY {
1636 pub const offset: u32 = 0;
1637 pub const mask: u32 = 0xffff << offset;
1638 pub mod R {}
1639 pub mod W {}
1640 pub mod RW {}
1641 }
1642 #[doc = "TRIGGER sampling interval counter"]
1643 pub mod SAMPLE_INTERVAL {
1644 pub const offset: u32 = 16;
1645 pub const mask: u32 = 0xffff << offset;
1646 pub mod R {}
1647 pub mod W {}
1648 pub mod RW {}
1649 }
1650}
1651#[doc = "ETC_TRIG Chain 0/1 Register"]
1652pub mod TRIG2_CHAIN_1_0 {
1653 #[doc = "CHAIN0 CSEL ADC channel selection"]
1654 pub mod CSEL0 {
1655 pub const offset: u32 = 0;
1656 pub const mask: u32 = 0x0f << offset;
1657 pub mod R {}
1658 pub mod W {}
1659 pub mod RW {}
1660 }
1661 #[doc = "CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
1662 pub mod HWTS0 {
1663 pub const offset: u32 = 4;
1664 pub const mask: u32 = 0xff << offset;
1665 pub mod R {}
1666 pub mod W {}
1667 pub mod RW {}
1668 }
1669 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1670 pub mod B2B0 {
1671 pub const offset: u32 = 12;
1672 pub const mask: u32 = 0x01 << offset;
1673 pub mod R {}
1674 pub mod W {}
1675 pub mod RW {}
1676 }
1677 #[doc = "CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
1678 pub mod IE0 {
1679 pub const offset: u32 = 13;
1680 pub const mask: u32 = 0x03 << offset;
1681 pub mod R {}
1682 pub mod W {}
1683 pub mod RW {}
1684 }
1685 #[doc = "IRQ enable"]
1686 pub mod IE0_EN {
1687 pub const offset: u32 = 15;
1688 pub const mask: u32 = 0x01 << offset;
1689 pub mod R {}
1690 pub mod W {}
1691 pub mod RW {}
1692 }
1693 #[doc = "CHAIN1 CSEL ADC channel selection"]
1694 pub mod CSEL1 {
1695 pub const offset: u32 = 16;
1696 pub const mask: u32 = 0x0f << offset;
1697 pub mod R {}
1698 pub mod W {}
1699 pub mod RW {}
1700 }
1701 #[doc = "CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
1702 pub mod HWTS1 {
1703 pub const offset: u32 = 20;
1704 pub const mask: u32 = 0xff << offset;
1705 pub mod R {}
1706 pub mod W {}
1707 pub mod RW {}
1708 }
1709 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1710 pub mod B2B1 {
1711 pub const offset: u32 = 28;
1712 pub const mask: u32 = 0x01 << offset;
1713 pub mod R {}
1714 pub mod W {}
1715 pub mod RW {}
1716 }
1717 #[doc = "CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
1718 pub mod IE1 {
1719 pub const offset: u32 = 29;
1720 pub const mask: u32 = 0x03 << offset;
1721 pub mod R {}
1722 pub mod W {}
1723 pub mod RW {}
1724 }
1725 #[doc = "IRQ enable"]
1726 pub mod IE1_EN {
1727 pub const offset: u32 = 31;
1728 pub const mask: u32 = 0x01 << offset;
1729 pub mod R {}
1730 pub mod W {}
1731 pub mod RW {}
1732 }
1733}
1734#[doc = "ETC_TRIG Chain 2/3 Register"]
1735pub mod TRIG2_CHAIN_3_2 {
1736 #[doc = "CHAIN2 CSEL"]
1737 pub mod CSEL2 {
1738 pub const offset: u32 = 0;
1739 pub const mask: u32 = 0x0f << offset;
1740 pub mod R {}
1741 pub mod W {}
1742 pub mod RW {}
1743 }
1744 #[doc = "CHAIN2 HWTS"]
1745 pub mod HWTS2 {
1746 pub const offset: u32 = 4;
1747 pub const mask: u32 = 0xff << offset;
1748 pub mod R {}
1749 pub mod W {}
1750 pub mod RW {}
1751 }
1752 #[doc = "CHAIN2 B2B"]
1753 pub mod B2B2 {
1754 pub const offset: u32 = 12;
1755 pub const mask: u32 = 0x01 << offset;
1756 pub mod R {}
1757 pub mod W {}
1758 pub mod RW {}
1759 }
1760 #[doc = "CHAIN2 IE"]
1761 pub mod IE2 {
1762 pub const offset: u32 = 13;
1763 pub const mask: u32 = 0x03 << offset;
1764 pub mod R {}
1765 pub mod W {}
1766 pub mod RW {}
1767 }
1768 #[doc = "IRQ enable"]
1769 pub mod IE2_EN {
1770 pub const offset: u32 = 15;
1771 pub const mask: u32 = 0x01 << offset;
1772 pub mod R {}
1773 pub mod W {}
1774 pub mod RW {}
1775 }
1776 #[doc = "CHAIN3 CSEL"]
1777 pub mod CSEL3 {
1778 pub const offset: u32 = 16;
1779 pub const mask: u32 = 0x0f << offset;
1780 pub mod R {}
1781 pub mod W {}
1782 pub mod RW {}
1783 }
1784 #[doc = "CHAIN3 HWTS"]
1785 pub mod HWTS3 {
1786 pub const offset: u32 = 20;
1787 pub const mask: u32 = 0xff << offset;
1788 pub mod R {}
1789 pub mod W {}
1790 pub mod RW {}
1791 }
1792 #[doc = "CHAIN3 B2B"]
1793 pub mod B2B3 {
1794 pub const offset: u32 = 28;
1795 pub const mask: u32 = 0x01 << offset;
1796 pub mod R {}
1797 pub mod W {}
1798 pub mod RW {}
1799 }
1800 #[doc = "CHAIN3 IE"]
1801 pub mod IE3 {
1802 pub const offset: u32 = 29;
1803 pub const mask: u32 = 0x03 << offset;
1804 pub mod R {}
1805 pub mod W {}
1806 pub mod RW {}
1807 }
1808 #[doc = "IRQ enable"]
1809 pub mod IE3_EN {
1810 pub const offset: u32 = 31;
1811 pub const mask: u32 = 0x01 << offset;
1812 pub mod R {}
1813 pub mod W {}
1814 pub mod RW {}
1815 }
1816}
1817#[doc = "ETC_TRIG Chain 4/5 Register"]
1818pub mod TRIG2_CHAIN_5_4 {
1819 #[doc = "CHAIN4 CSEL"]
1820 pub mod CSEL4 {
1821 pub const offset: u32 = 0;
1822 pub const mask: u32 = 0x0f << offset;
1823 pub mod R {}
1824 pub mod W {}
1825 pub mod RW {}
1826 }
1827 #[doc = "CHAIN4 HWTS"]
1828 pub mod HWTS4 {
1829 pub const offset: u32 = 4;
1830 pub const mask: u32 = 0xff << offset;
1831 pub mod R {}
1832 pub mod W {}
1833 pub mod RW {}
1834 }
1835 #[doc = "CHAIN4 B2B"]
1836 pub mod B2B4 {
1837 pub const offset: u32 = 12;
1838 pub const mask: u32 = 0x01 << offset;
1839 pub mod R {}
1840 pub mod W {}
1841 pub mod RW {}
1842 }
1843 #[doc = "CHAIN4 IE"]
1844 pub mod IE4 {
1845 pub const offset: u32 = 13;
1846 pub const mask: u32 = 0x03 << offset;
1847 pub mod R {}
1848 pub mod W {}
1849 pub mod RW {}
1850 }
1851 #[doc = "IRQ enable"]
1852 pub mod IE4_EN {
1853 pub const offset: u32 = 15;
1854 pub const mask: u32 = 0x01 << offset;
1855 pub mod R {}
1856 pub mod W {}
1857 pub mod RW {}
1858 }
1859 #[doc = "CHAIN5 CSEL"]
1860 pub mod CSEL5 {
1861 pub const offset: u32 = 16;
1862 pub const mask: u32 = 0x0f << offset;
1863 pub mod R {}
1864 pub mod W {}
1865 pub mod RW {}
1866 }
1867 #[doc = "CHAIN5 HWTS"]
1868 pub mod HWTS5 {
1869 pub const offset: u32 = 20;
1870 pub const mask: u32 = 0xff << offset;
1871 pub mod R {}
1872 pub mod W {}
1873 pub mod RW {}
1874 }
1875 #[doc = "CHAIN5 B2B"]
1876 pub mod B2B5 {
1877 pub const offset: u32 = 28;
1878 pub const mask: u32 = 0x01 << offset;
1879 pub mod R {}
1880 pub mod W {}
1881 pub mod RW {}
1882 }
1883 #[doc = "CHAIN5 IE"]
1884 pub mod IE5 {
1885 pub const offset: u32 = 29;
1886 pub const mask: u32 = 0x03 << offset;
1887 pub mod R {}
1888 pub mod W {}
1889 pub mod RW {}
1890 }
1891 #[doc = "IRQ enable"]
1892 pub mod IE5_EN {
1893 pub const offset: u32 = 31;
1894 pub const mask: u32 = 0x01 << offset;
1895 pub mod R {}
1896 pub mod W {}
1897 pub mod RW {}
1898 }
1899}
1900#[doc = "ETC_TRIG Chain 6/7 Register"]
1901pub mod TRIG2_CHAIN_7_6 {
1902 #[doc = "CHAIN6 CSEL"]
1903 pub mod CSEL6 {
1904 pub const offset: u32 = 0;
1905 pub const mask: u32 = 0x0f << offset;
1906 pub mod R {}
1907 pub mod W {}
1908 pub mod RW {}
1909 }
1910 #[doc = "CHAIN6 HWTS"]
1911 pub mod HWTS6 {
1912 pub const offset: u32 = 4;
1913 pub const mask: u32 = 0xff << offset;
1914 pub mod R {}
1915 pub mod W {}
1916 pub mod RW {}
1917 }
1918 #[doc = "CHAIN6 B2B"]
1919 pub mod B2B6 {
1920 pub const offset: u32 = 12;
1921 pub const mask: u32 = 0x01 << offset;
1922 pub mod R {}
1923 pub mod W {}
1924 pub mod RW {}
1925 }
1926 #[doc = "CHAIN6 IE"]
1927 pub mod IE6 {
1928 pub const offset: u32 = 13;
1929 pub const mask: u32 = 0x03 << offset;
1930 pub mod R {}
1931 pub mod W {}
1932 pub mod RW {}
1933 }
1934 #[doc = "IRQ enable"]
1935 pub mod IE6_EN {
1936 pub const offset: u32 = 15;
1937 pub const mask: u32 = 0x01 << offset;
1938 pub mod R {}
1939 pub mod W {}
1940 pub mod RW {}
1941 }
1942 #[doc = "CHAIN7 CSEL"]
1943 pub mod CSEL7 {
1944 pub const offset: u32 = 16;
1945 pub const mask: u32 = 0x0f << offset;
1946 pub mod R {}
1947 pub mod W {}
1948 pub mod RW {}
1949 }
1950 #[doc = "CHAIN7 HWTS"]
1951 pub mod HWTS7 {
1952 pub const offset: u32 = 20;
1953 pub const mask: u32 = 0xff << offset;
1954 pub mod R {}
1955 pub mod W {}
1956 pub mod RW {}
1957 }
1958 #[doc = "CHAIN7 B2B"]
1959 pub mod B2B7 {
1960 pub const offset: u32 = 28;
1961 pub const mask: u32 = 0x01 << offset;
1962 pub mod R {}
1963 pub mod W {}
1964 pub mod RW {}
1965 }
1966 #[doc = "CHAIN7 IE"]
1967 pub mod IE7 {
1968 pub const offset: u32 = 29;
1969 pub const mask: u32 = 0x03 << offset;
1970 pub mod R {}
1971 pub mod W {}
1972 pub mod RW {}
1973 }
1974 #[doc = "IRQ enable"]
1975 pub mod IE7_EN {
1976 pub const offset: u32 = 31;
1977 pub const mask: u32 = 0x01 << offset;
1978 pub mod R {}
1979 pub mod W {}
1980 pub mod RW {}
1981 }
1982}
1983#[doc = "ETC_TRIG Result Data 1/0 Register"]
1984pub mod TRIG2_RESULT_1_0 {
1985 #[doc = "Result DATA0"]
1986 pub mod DATA0 {
1987 pub const offset: u32 = 0;
1988 pub const mask: u32 = 0x0fff << offset;
1989 pub mod R {}
1990 pub mod W {}
1991 pub mod RW {}
1992 }
1993 #[doc = "Result DATA1"]
1994 pub mod DATA1 {
1995 pub const offset: u32 = 16;
1996 pub const mask: u32 = 0x0fff << offset;
1997 pub mod R {}
1998 pub mod W {}
1999 pub mod RW {}
2000 }
2001}
2002#[doc = "ETC_TRIG Result Data 3/2 Register"]
2003pub mod TRIG2_RESULT_3_2 {
2004 #[doc = "Result DATA2"]
2005 pub mod DATA2 {
2006 pub const offset: u32 = 0;
2007 pub const mask: u32 = 0x0fff << offset;
2008 pub mod R {}
2009 pub mod W {}
2010 pub mod RW {}
2011 }
2012 #[doc = "Result DATA3"]
2013 pub mod DATA3 {
2014 pub const offset: u32 = 16;
2015 pub const mask: u32 = 0x0fff << offset;
2016 pub mod R {}
2017 pub mod W {}
2018 pub mod RW {}
2019 }
2020}
2021#[doc = "ETC_TRIG Result Data 5/4 Register"]
2022pub mod TRIG2_RESULT_5_4 {
2023 #[doc = "Result DATA4"]
2024 pub mod DATA4 {
2025 pub const offset: u32 = 0;
2026 pub const mask: u32 = 0x0fff << offset;
2027 pub mod R {}
2028 pub mod W {}
2029 pub mod RW {}
2030 }
2031 #[doc = "Result DATA5"]
2032 pub mod DATA5 {
2033 pub const offset: u32 = 16;
2034 pub const mask: u32 = 0x0fff << offset;
2035 pub mod R {}
2036 pub mod W {}
2037 pub mod RW {}
2038 }
2039}
2040#[doc = "ETC_TRIG Result Data 7/6 Register"]
2041pub mod TRIG2_RESULT_7_6 {
2042 #[doc = "Result DATA6"]
2043 pub mod DATA6 {
2044 pub const offset: u32 = 0;
2045 pub const mask: u32 = 0x0fff << offset;
2046 pub mod R {}
2047 pub mod W {}
2048 pub mod RW {}
2049 }
2050 #[doc = "Result DATA7"]
2051 pub mod DATA7 {
2052 pub const offset: u32 = 16;
2053 pub const mask: u32 = 0x0fff << offset;
2054 pub mod R {}
2055 pub mod W {}
2056 pub mod RW {}
2057 }
2058}
2059#[doc = "ETC_TRIG Control Register"]
2060pub mod TRIG3_CTRL {
2061 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
2062 pub mod SW_TRIG {
2063 pub const offset: u32 = 0;
2064 pub const mask: u32 = 0x01 << offset;
2065 pub mod R {}
2066 pub mod W {}
2067 pub mod RW {}
2068 }
2069 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
2070 pub mod TRIG_MODE {
2071 pub const offset: u32 = 4;
2072 pub const mask: u32 = 0x01 << offset;
2073 pub mod R {}
2074 pub mod W {}
2075 pub mod RW {}
2076 }
2077 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
2078 pub mod TRIG_CHAIN {
2079 pub const offset: u32 = 8;
2080 pub const mask: u32 = 0x07 << offset;
2081 pub mod R {}
2082 pub mod W {}
2083 pub mod RW {}
2084 }
2085 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
2086 pub mod TRIG_PRIORITY {
2087 pub const offset: u32 = 12;
2088 pub const mask: u32 = 0x07 << offset;
2089 pub mod R {}
2090 pub mod W {}
2091 pub mod RW {}
2092 }
2093 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
2094 pub mod SYNC_MODE {
2095 pub const offset: u32 = 16;
2096 pub const mask: u32 = 0x01 << offset;
2097 pub mod R {}
2098 pub mod W {}
2099 pub mod RW {}
2100 }
2101 #[doc = "CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits"]
2102 pub mod CHAINX_DONE {
2103 pub const offset: u32 = 24;
2104 pub const mask: u32 = 0xff << offset;
2105 pub mod R {}
2106 pub mod W {}
2107 pub mod RW {}
2108 }
2109}
2110#[doc = "ETC_TRIG Counter Register"]
2111pub mod TRIG3_COUNTER {
2112 #[doc = "TRIGGER initial delay counter"]
2113 pub mod INIT_DELAY {
2114 pub const offset: u32 = 0;
2115 pub const mask: u32 = 0xffff << offset;
2116 pub mod R {}
2117 pub mod W {}
2118 pub mod RW {}
2119 }
2120 #[doc = "TRIGGER sampling interval counter"]
2121 pub mod SAMPLE_INTERVAL {
2122 pub const offset: u32 = 16;
2123 pub const mask: u32 = 0xffff << offset;
2124 pub mod R {}
2125 pub mod W {}
2126 pub mod RW {}
2127 }
2128}
2129#[doc = "ETC_TRIG Chain 0/1 Register"]
2130pub mod TRIG3_CHAIN_1_0 {
2131 #[doc = "CHAIN0 CSEL ADC channel selection"]
2132 pub mod CSEL0 {
2133 pub const offset: u32 = 0;
2134 pub const mask: u32 = 0x0f << offset;
2135 pub mod R {}
2136 pub mod W {}
2137 pub mod RW {}
2138 }
2139 #[doc = "CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
2140 pub mod HWTS0 {
2141 pub const offset: u32 = 4;
2142 pub const mask: u32 = 0xff << offset;
2143 pub mod R {}
2144 pub mod W {}
2145 pub mod RW {}
2146 }
2147 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
2148 pub mod B2B0 {
2149 pub const offset: u32 = 12;
2150 pub const mask: u32 = 0x01 << offset;
2151 pub mod R {}
2152 pub mod W {}
2153 pub mod RW {}
2154 }
2155 #[doc = "CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
2156 pub mod IE0 {
2157 pub const offset: u32 = 13;
2158 pub const mask: u32 = 0x03 << offset;
2159 pub mod R {}
2160 pub mod W {}
2161 pub mod RW {}
2162 }
2163 #[doc = "IRQ enable"]
2164 pub mod IE0_EN {
2165 pub const offset: u32 = 15;
2166 pub const mask: u32 = 0x01 << offset;
2167 pub mod R {}
2168 pub mod W {}
2169 pub mod RW {}
2170 }
2171 #[doc = "CHAIN1 CSEL ADC channel selection"]
2172 pub mod CSEL1 {
2173 pub const offset: u32 = 16;
2174 pub const mask: u32 = 0x0f << offset;
2175 pub mod R {}
2176 pub mod W {}
2177 pub mod RW {}
2178 }
2179 #[doc = "CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
2180 pub mod HWTS1 {
2181 pub const offset: u32 = 20;
2182 pub const mask: u32 = 0xff << offset;
2183 pub mod R {}
2184 pub mod W {}
2185 pub mod RW {}
2186 }
2187 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
2188 pub mod B2B1 {
2189 pub const offset: u32 = 28;
2190 pub const mask: u32 = 0x01 << offset;
2191 pub mod R {}
2192 pub mod W {}
2193 pub mod RW {}
2194 }
2195 #[doc = "CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3"]
2196 pub mod IE1 {
2197 pub const offset: u32 = 29;
2198 pub const mask: u32 = 0x03 << offset;
2199 pub mod R {}
2200 pub mod W {}
2201 pub mod RW {}
2202 }
2203 #[doc = "IRQ enable"]
2204 pub mod IE1_EN {
2205 pub const offset: u32 = 31;
2206 pub const mask: u32 = 0x01 << offset;
2207 pub mod R {}
2208 pub mod W {}
2209 pub mod RW {}
2210 }
2211}
2212#[doc = "ETC_TRIG Chain 2/3 Register"]
2213pub mod TRIG3_CHAIN_3_2 {
2214 #[doc = "CHAIN2 CSEL"]
2215 pub mod CSEL2 {
2216 pub const offset: u32 = 0;
2217 pub const mask: u32 = 0x0f << offset;
2218 pub mod R {}
2219 pub mod W {}
2220 pub mod RW {}
2221 }
2222 #[doc = "CHAIN2 HWTS"]
2223 pub mod HWTS2 {
2224 pub const offset: u32 = 4;
2225 pub const mask: u32 = 0xff << offset;
2226 pub mod R {}
2227 pub mod W {}
2228 pub mod RW {}
2229 }
2230 #[doc = "CHAIN2 B2B"]
2231 pub mod B2B2 {
2232 pub const offset: u32 = 12;
2233 pub const mask: u32 = 0x01 << offset;
2234 pub mod R {}
2235 pub mod W {}
2236 pub mod RW {}
2237 }
2238 #[doc = "CHAIN2 IE"]
2239 pub mod IE2 {
2240 pub const offset: u32 = 13;
2241 pub const mask: u32 = 0x03 << offset;
2242 pub mod R {}
2243 pub mod W {}
2244 pub mod RW {}
2245 }
2246 #[doc = "IRQ enable"]
2247 pub mod IE2_EN {
2248 pub const offset: u32 = 15;
2249 pub const mask: u32 = 0x01 << offset;
2250 pub mod R {}
2251 pub mod W {}
2252 pub mod RW {}
2253 }
2254 #[doc = "CHAIN3 CSEL"]
2255 pub mod CSEL3 {
2256 pub const offset: u32 = 16;
2257 pub const mask: u32 = 0x0f << offset;
2258 pub mod R {}
2259 pub mod W {}
2260 pub mod RW {}
2261 }
2262 #[doc = "CHAIN3 HWTS"]
2263 pub mod HWTS3 {
2264 pub const offset: u32 = 20;
2265 pub const mask: u32 = 0xff << offset;
2266 pub mod R {}
2267 pub mod W {}
2268 pub mod RW {}
2269 }
2270 #[doc = "CHAIN3 B2B"]
2271 pub mod B2B3 {
2272 pub const offset: u32 = 28;
2273 pub const mask: u32 = 0x01 << offset;
2274 pub mod R {}
2275 pub mod W {}
2276 pub mod RW {}
2277 }
2278 #[doc = "CHAIN3 IE"]
2279 pub mod IE3 {
2280 pub const offset: u32 = 29;
2281 pub const mask: u32 = 0x03 << offset;
2282 pub mod R {}
2283 pub mod W {}
2284 pub mod RW {}
2285 }
2286 #[doc = "IRQ enable"]
2287 pub mod IE3_EN {
2288 pub const offset: u32 = 31;
2289 pub const mask: u32 = 0x01 << offset;
2290 pub mod R {}
2291 pub mod W {}
2292 pub mod RW {}
2293 }
2294}
2295#[doc = "ETC_TRIG Chain 4/5 Register"]
2296pub mod TRIG3_CHAIN_5_4 {
2297 #[doc = "CHAIN4 CSEL"]
2298 pub mod CSEL4 {
2299 pub const offset: u32 = 0;
2300 pub const mask: u32 = 0x0f << offset;
2301 pub mod R {}
2302 pub mod W {}
2303 pub mod RW {}
2304 }
2305 #[doc = "CHAIN4 HWTS"]
2306 pub mod HWTS4 {
2307 pub const offset: u32 = 4;
2308 pub const mask: u32 = 0xff << offset;
2309 pub mod R {}
2310 pub mod W {}
2311 pub mod RW {}
2312 }
2313 #[doc = "CHAIN4 B2B"]
2314 pub mod B2B4 {
2315 pub const offset: u32 = 12;
2316 pub const mask: u32 = 0x01 << offset;
2317 pub mod R {}
2318 pub mod W {}
2319 pub mod RW {}
2320 }
2321 #[doc = "CHAIN4 IE"]
2322 pub mod IE4 {
2323 pub const offset: u32 = 13;
2324 pub const mask: u32 = 0x03 << offset;
2325 pub mod R {}
2326 pub mod W {}
2327 pub mod RW {}
2328 }
2329 #[doc = "IRQ enable"]
2330 pub mod IE4_EN {
2331 pub const offset: u32 = 15;
2332 pub const mask: u32 = 0x01 << offset;
2333 pub mod R {}
2334 pub mod W {}
2335 pub mod RW {}
2336 }
2337 #[doc = "CHAIN5 CSEL"]
2338 pub mod CSEL5 {
2339 pub const offset: u32 = 16;
2340 pub const mask: u32 = 0x0f << offset;
2341 pub mod R {}
2342 pub mod W {}
2343 pub mod RW {}
2344 }
2345 #[doc = "CHAIN5 HWTS"]
2346 pub mod HWTS5 {
2347 pub const offset: u32 = 20;
2348 pub const mask: u32 = 0xff << offset;
2349 pub mod R {}
2350 pub mod W {}
2351 pub mod RW {}
2352 }
2353 #[doc = "CHAIN5 B2B"]
2354 pub mod B2B5 {
2355 pub const offset: u32 = 28;
2356 pub const mask: u32 = 0x01 << offset;
2357 pub mod R {}
2358 pub mod W {}
2359 pub mod RW {}
2360 }
2361 #[doc = "CHAIN5 IE"]
2362 pub mod IE5 {
2363 pub const offset: u32 = 29;
2364 pub const mask: u32 = 0x03 << offset;
2365 pub mod R {}
2366 pub mod W {}
2367 pub mod RW {}
2368 }
2369 #[doc = "IRQ enable"]
2370 pub mod IE5_EN {
2371 pub const offset: u32 = 31;
2372 pub const mask: u32 = 0x01 << offset;
2373 pub mod R {}
2374 pub mod W {}
2375 pub mod RW {}
2376 }
2377}
2378#[doc = "ETC_TRIG Chain 6/7 Register"]
2379pub mod TRIG3_CHAIN_7_6 {
2380 #[doc = "CHAIN6 CSEL"]
2381 pub mod CSEL6 {
2382 pub const offset: u32 = 0;
2383 pub const mask: u32 = 0x0f << offset;
2384 pub mod R {}
2385 pub mod W {}
2386 pub mod RW {}
2387 }
2388 #[doc = "CHAIN6 HWTS"]
2389 pub mod HWTS6 {
2390 pub const offset: u32 = 4;
2391 pub const mask: u32 = 0xff << offset;
2392 pub mod R {}
2393 pub mod W {}
2394 pub mod RW {}
2395 }
2396 #[doc = "CHAIN6 B2B"]
2397 pub mod B2B6 {
2398 pub const offset: u32 = 12;
2399 pub const mask: u32 = 0x01 << offset;
2400 pub mod R {}
2401 pub mod W {}
2402 pub mod RW {}
2403 }
2404 #[doc = "CHAIN6 IE"]
2405 pub mod IE6 {
2406 pub const offset: u32 = 13;
2407 pub const mask: u32 = 0x03 << offset;
2408 pub mod R {}
2409 pub mod W {}
2410 pub mod RW {}
2411 }
2412 #[doc = "IRQ enable"]
2413 pub mod IE6_EN {
2414 pub const offset: u32 = 15;
2415 pub const mask: u32 = 0x01 << offset;
2416 pub mod R {}
2417 pub mod W {}
2418 pub mod RW {}
2419 }
2420 #[doc = "CHAIN7 CSEL"]
2421 pub mod CSEL7 {
2422 pub const offset: u32 = 16;
2423 pub const mask: u32 = 0x0f << offset;
2424 pub mod R {}
2425 pub mod W {}
2426 pub mod RW {}
2427 }
2428 #[doc = "CHAIN7 HWTS"]
2429 pub mod HWTS7 {
2430 pub const offset: u32 = 20;
2431 pub const mask: u32 = 0xff << offset;
2432 pub mod R {}
2433 pub mod W {}
2434 pub mod RW {}
2435 }
2436 #[doc = "CHAIN7 B2B"]
2437 pub mod B2B7 {
2438 pub const offset: u32 = 28;
2439 pub const mask: u32 = 0x01 << offset;
2440 pub mod R {}
2441 pub mod W {}
2442 pub mod RW {}
2443 }
2444 #[doc = "CHAIN7 IE"]
2445 pub mod IE7 {
2446 pub const offset: u32 = 29;
2447 pub const mask: u32 = 0x03 << offset;
2448 pub mod R {}
2449 pub mod W {}
2450 pub mod RW {}
2451 }
2452 #[doc = "IRQ enable"]
2453 pub mod IE7_EN {
2454 pub const offset: u32 = 31;
2455 pub const mask: u32 = 0x01 << offset;
2456 pub mod R {}
2457 pub mod W {}
2458 pub mod RW {}
2459 }
2460}
2461#[doc = "ETC_TRIG Result Data 1/0 Register"]
2462pub mod TRIG3_RESULT_1_0 {
2463 #[doc = "Result DATA0"]
2464 pub mod DATA0 {
2465 pub const offset: u32 = 0;
2466 pub const mask: u32 = 0x0fff << offset;
2467 pub mod R {}
2468 pub mod W {}
2469 pub mod RW {}
2470 }
2471 #[doc = "Result DATA1"]
2472 pub mod DATA1 {
2473 pub const offset: u32 = 16;
2474 pub const mask: u32 = 0x0fff << offset;
2475 pub mod R {}
2476 pub mod W {}
2477 pub mod RW {}
2478 }
2479}
2480#[doc = "ETC_TRIG Result Data 3/2 Register"]
2481pub mod TRIG3_RESULT_3_2 {
2482 #[doc = "Result DATA2"]
2483 pub mod DATA2 {
2484 pub const offset: u32 = 0;
2485 pub const mask: u32 = 0x0fff << offset;
2486 pub mod R {}
2487 pub mod W {}
2488 pub mod RW {}
2489 }
2490 #[doc = "Result DATA3"]
2491 pub mod DATA3 {
2492 pub const offset: u32 = 16;
2493 pub const mask: u32 = 0x0fff << offset;
2494 pub mod R {}
2495 pub mod W {}
2496 pub mod RW {}
2497 }
2498}
2499#[doc = "ETC_TRIG Result Data 5/4 Register"]
2500pub mod TRIG3_RESULT_5_4 {
2501 #[doc = "Result DATA4"]
2502 pub mod DATA4 {
2503 pub const offset: u32 = 0;
2504 pub const mask: u32 = 0x0fff << offset;
2505 pub mod R {}
2506 pub mod W {}
2507 pub mod RW {}
2508 }
2509 #[doc = "Result DATA5"]
2510 pub mod DATA5 {
2511 pub const offset: u32 = 16;
2512 pub const mask: u32 = 0x0fff << offset;
2513 pub mod R {}
2514 pub mod W {}
2515 pub mod RW {}
2516 }
2517}
2518#[doc = "ETC_TRIG Result Data 7/6 Register"]
2519pub mod TRIG3_RESULT_7_6 {
2520 #[doc = "Result DATA6"]
2521 pub mod DATA6 {
2522 pub const offset: u32 = 0;
2523 pub const mask: u32 = 0x0fff << offset;
2524 pub mod R {}
2525 pub mod W {}
2526 pub mod RW {}
2527 }
2528 #[doc = "Result DATA7"]
2529 pub mod DATA7 {
2530 pub const offset: u32 = 16;
2531 pub const mask: u32 = 0x0fff << offset;
2532 pub mod R {}
2533 pub mod W {}
2534 pub mod RW {}
2535 }
2536}