1#[doc = "PWM"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Cluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, SM?CTRL, SM?VAL0, SM?FRACVAL1, SM?VAL1, SM?FRACVAL2, SM?VAL2, SM?FRACVAL3, SM?VAL3, SM?FRACVAL4, SM?VAL4, SM?FRACVAL5, SM?VAL5, SM?FRCTRL, SM?OCTRL, SM?STS, SM?INTEN, SM?DMAEN, SM?TCTRL, SM?DISMAP0, SM?DISMAP1, SM?DTCNT0, SM?DTCNT1, SM?CAPTCTRLA, SM?CAPTCOMPA, SM?CAPTCTRLB, SM?CAPTCOMPB, SM?CAPTCTRLX, SM?CAPTCOMPX, SM?CVAL0, SM?CVAL0CYC, SM?CVAL1, SM?CVAL1CYC, SM?CVAL2, SM?CVAL2CYC, SM?CVAL3, SM?CVAL3CYC, SM?CVAL4, SM?CVAL4CYC, SM?CVAL5, SM?CVAL5CYC, SM?PHASEDLY"]
5 pub SM: [sm::RegisterBlock; 4usize],
6 #[doc = "Output Enable Register"]
7 pub OUTEN: crate::RWRegister<u16>,
8 #[doc = "Mask Register"]
9 pub MASK: crate::RWRegister<u16>,
10 #[doc = "Software Controlled Output Register"]
11 pub SWCOUT: crate::RWRegister<u16>,
12 #[doc = "PWM Source Select Register"]
13 pub DTSRCSEL: crate::RWRegister<u16>,
14 #[doc = "Master Control Register"]
15 pub MCTRL: crate::RWRegister<u16>,
16 #[doc = "Master Control 2 Register"]
17 pub MCTRL2: crate::RWRegister<u16>,
18 #[doc = "Fault Control Register"]
19 pub FCTRL0: crate::RWRegister<u16>,
20 #[doc = "Fault Status Register"]
21 pub FSTS0: crate::RWRegister<u16>,
22 #[doc = "Fault Filter Register"]
23 pub FFILT0: crate::RWRegister<u16>,
24 #[doc = "Fault Test Register"]
25 pub FTST0: crate::RWRegister<u16>,
26 #[doc = "Fault Control 2 Register"]
27 pub FCTRL20: crate::RWRegister<u16>,
28}
29#[doc = "Output Enable Register"]
30pub mod OUTEN {
31 #[doc = "PWM_X Output Enables"]
32 pub mod PWMX_EN {
33 pub const offset: u16 = 0;
34 pub const mask: u16 = 0x0f << offset;
35 pub mod R {}
36 pub mod W {}
37 pub mod RW {
38 #[doc = "PWM_X output disabled."]
39 pub const PWMX_EN_0: u16 = 0;
40 #[doc = "PWM_X output enabled."]
41 pub const PWMX_EN_1: u16 = 0x01;
42 }
43 }
44 #[doc = "PWM_B Output Enables"]
45 pub mod PWMB_EN {
46 pub const offset: u16 = 4;
47 pub const mask: u16 = 0x0f << offset;
48 pub mod R {}
49 pub mod W {}
50 pub mod RW {
51 #[doc = "PWM_B output disabled."]
52 pub const PWMB_EN_0: u16 = 0;
53 #[doc = "PWM_B output enabled."]
54 pub const PWMB_EN_1: u16 = 0x01;
55 }
56 }
57 #[doc = "PWM_A Output Enables"]
58 pub mod PWMA_EN {
59 pub const offset: u16 = 8;
60 pub const mask: u16 = 0x0f << offset;
61 pub mod R {}
62 pub mod W {}
63 pub mod RW {
64 #[doc = "PWM_A output disabled."]
65 pub const PWMA_EN_0: u16 = 0;
66 #[doc = "PWM_A output enabled."]
67 pub const PWMA_EN_1: u16 = 0x01;
68 }
69 }
70}
71#[doc = "Mask Register"]
72pub mod MASK {
73 #[doc = "PWM_X Masks"]
74 pub mod MASKX {
75 pub const offset: u16 = 0;
76 pub const mask: u16 = 0x0f << offset;
77 pub mod R {}
78 pub mod W {}
79 pub mod RW {
80 #[doc = "PWM_X output normal."]
81 pub const MASKX_0: u16 = 0;
82 #[doc = "PWM_X output masked."]
83 pub const MASKX_1: u16 = 0x01;
84 }
85 }
86 #[doc = "PWM_B Masks"]
87 pub mod MASKB {
88 pub const offset: u16 = 4;
89 pub const mask: u16 = 0x0f << offset;
90 pub mod R {}
91 pub mod W {}
92 pub mod RW {
93 #[doc = "PWM_B output normal."]
94 pub const MASKB_0: u16 = 0;
95 #[doc = "PWM_B output masked."]
96 pub const MASKB_1: u16 = 0x01;
97 }
98 }
99 #[doc = "PWM_A Masks"]
100 pub mod MASKA {
101 pub const offset: u16 = 8;
102 pub const mask: u16 = 0x0f << offset;
103 pub mod R {}
104 pub mod W {}
105 pub mod RW {
106 #[doc = "PWM_A output normal."]
107 pub const MASKA_0: u16 = 0;
108 #[doc = "PWM_A output masked."]
109 pub const MASKA_1: u16 = 0x01;
110 }
111 }
112 #[doc = "Update Mask Bits Immediately"]
113 pub mod UPDATE_MASK {
114 pub const offset: u16 = 12;
115 pub const mask: u16 = 0x0f << offset;
116 pub mod R {}
117 pub mod W {}
118 pub mod RW {
119 #[doc = "Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule."]
120 pub const UPDATE_MASK_0: u16 = 0;
121 #[doc = "Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit."]
122 pub const UPDATE_MASK_1: u16 = 0x01;
123 }
124 }
125}
126#[doc = "Software Controlled Output Register"]
127pub mod SWCOUT {
128 #[doc = "Submodule 0 Software Controlled Output 45"]
129 pub mod SM0OUT45 {
130 pub const offset: u16 = 0;
131 pub const mask: u16 = 0x01 << offset;
132 pub mod R {}
133 pub mod W {}
134 pub mod RW {
135 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."]
136 pub const SM0OUT45_0: u16 = 0;
137 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."]
138 pub const SM0OUT45_1: u16 = 0x01;
139 }
140 }
141 #[doc = "Submodule 0 Software Controlled Output 23"]
142 pub mod SM0OUT23 {
143 pub const offset: u16 = 1;
144 pub const mask: u16 = 0x01 << offset;
145 pub mod R {}
146 pub mod W {}
147 pub mod RW {
148 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."]
149 pub const SM0OUT23_0: u16 = 0;
150 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."]
151 pub const SM0OUT23_1: u16 = 0x01;
152 }
153 }
154 #[doc = "Submodule 1 Software Controlled Output 45"]
155 pub mod SM1OUT45 {
156 pub const offset: u16 = 2;
157 pub const mask: u16 = 0x01 << offset;
158 pub mod R {}
159 pub mod W {}
160 pub mod RW {
161 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."]
162 pub const SM1OUT45_0: u16 = 0;
163 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."]
164 pub const SM1OUT45_1: u16 = 0x01;
165 }
166 }
167 #[doc = "Submodule 1 Software Controlled Output 23"]
168 pub mod SM1OUT23 {
169 pub const offset: u16 = 3;
170 pub const mask: u16 = 0x01 << offset;
171 pub mod R {}
172 pub mod W {}
173 pub mod RW {
174 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."]
175 pub const SM1OUT23_0: u16 = 0;
176 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."]
177 pub const SM1OUT23_1: u16 = 0x01;
178 }
179 }
180 #[doc = "Submodule 2 Software Controlled Output 45"]
181 pub mod SM2OUT45 {
182 pub const offset: u16 = 4;
183 pub const mask: u16 = 0x01 << offset;
184 pub mod R {}
185 pub mod W {}
186 pub mod RW {
187 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."]
188 pub const SM2OUT45_0: u16 = 0;
189 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."]
190 pub const SM2OUT45_1: u16 = 0x01;
191 }
192 }
193 #[doc = "Submodule 2 Software Controlled Output 23"]
194 pub mod SM2OUT23 {
195 pub const offset: u16 = 5;
196 pub const mask: u16 = 0x01 << offset;
197 pub mod R {}
198 pub mod W {}
199 pub mod RW {
200 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."]
201 pub const SM2OUT23_0: u16 = 0;
202 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."]
203 pub const SM2OUT23_1: u16 = 0x01;
204 }
205 }
206 #[doc = "Submodule 3 Software Controlled Output 45"]
207 pub mod SM3OUT45 {
208 pub const offset: u16 = 6;
209 pub const mask: u16 = 0x01 << offset;
210 pub mod R {}
211 pub mod W {}
212 pub mod RW {
213 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."]
214 pub const SM3OUT45_0: u16 = 0;
215 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."]
216 pub const SM3OUT45_1: u16 = 0x01;
217 }
218 }
219 #[doc = "Submodule 3 Software Controlled Output 23"]
220 pub mod SM3OUT23 {
221 pub const offset: u16 = 7;
222 pub const mask: u16 = 0x01 << offset;
223 pub mod R {}
224 pub mod W {}
225 pub mod RW {
226 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."]
227 pub const SM3OUT23_0: u16 = 0;
228 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."]
229 pub const SM3OUT23_1: u16 = 0x01;
230 }
231 }
232}
233#[doc = "PWM Source Select Register"]
234pub mod DTSRCSEL {
235 #[doc = "Submodule 0 PWM45 Control Select"]
236 pub mod SM0SEL45 {
237 pub const offset: u16 = 0;
238 pub const mask: u16 = 0x03 << offset;
239 pub mod R {}
240 pub mod W {}
241 pub mod RW {
242 #[doc = "Generated SM0PWM45 signal is used by the deadtime logic."]
243 pub const SM0SEL45_0: u16 = 0;
244 #[doc = "Inverted generated SM0PWM45 signal is used by the deadtime logic."]
245 pub const SM0SEL45_1: u16 = 0x01;
246 #[doc = "SWCOUT\\[SM0OUT45\\] is used by the deadtime logic."]
247 pub const SM0SEL45_2: u16 = 0x02;
248 #[doc = "PWM0_EXTB signal is used by the deadtime logic."]
249 pub const SM0SEL45_3: u16 = 0x03;
250 }
251 }
252 #[doc = "Submodule 0 PWM23 Control Select"]
253 pub mod SM0SEL23 {
254 pub const offset: u16 = 2;
255 pub const mask: u16 = 0x03 << offset;
256 pub mod R {}
257 pub mod W {}
258 pub mod RW {
259 #[doc = "Generated SM0PWM23 signal is used by the deadtime logic."]
260 pub const SM0SEL23_0: u16 = 0;
261 #[doc = "Inverted generated SM0PWM23 signal is used by the deadtime logic."]
262 pub const SM0SEL23_1: u16 = 0x01;
263 #[doc = "SWCOUT\\[SM0OUT23\\] is used by the deadtime logic."]
264 pub const SM0SEL23_2: u16 = 0x02;
265 #[doc = "PWM0_EXTA signal is used by the deadtime logic."]
266 pub const SM0SEL23_3: u16 = 0x03;
267 }
268 }
269 #[doc = "Submodule 1 PWM45 Control Select"]
270 pub mod SM1SEL45 {
271 pub const offset: u16 = 4;
272 pub const mask: u16 = 0x03 << offset;
273 pub mod R {}
274 pub mod W {}
275 pub mod RW {
276 #[doc = "Generated SM1PWM45 signal is used by the deadtime logic."]
277 pub const SM1SEL45_0: u16 = 0;
278 #[doc = "Inverted generated SM1PWM45 signal is used by the deadtime logic."]
279 pub const SM1SEL45_1: u16 = 0x01;
280 #[doc = "SWCOUT\\[SM1OUT45\\] is used by the deadtime logic."]
281 pub const SM1SEL45_2: u16 = 0x02;
282 #[doc = "PWM1_EXTB signal is used by the deadtime logic."]
283 pub const SM1SEL45_3: u16 = 0x03;
284 }
285 }
286 #[doc = "Submodule 1 PWM23 Control Select"]
287 pub mod SM1SEL23 {
288 pub const offset: u16 = 6;
289 pub const mask: u16 = 0x03 << offset;
290 pub mod R {}
291 pub mod W {}
292 pub mod RW {
293 #[doc = "Generated SM1PWM23 signal is used by the deadtime logic."]
294 pub const SM1SEL23_0: u16 = 0;
295 #[doc = "Inverted generated SM1PWM23 signal is used by the deadtime logic."]
296 pub const SM1SEL23_1: u16 = 0x01;
297 #[doc = "SWCOUT\\[SM1OUT23\\] is used by the deadtime logic."]
298 pub const SM1SEL23_2: u16 = 0x02;
299 #[doc = "PWM1_EXTA signal is used by the deadtime logic."]
300 pub const SM1SEL23_3: u16 = 0x03;
301 }
302 }
303 #[doc = "Submodule 2 PWM45 Control Select"]
304 pub mod SM2SEL45 {
305 pub const offset: u16 = 8;
306 pub const mask: u16 = 0x03 << offset;
307 pub mod R {}
308 pub mod W {}
309 pub mod RW {
310 #[doc = "Generated SM2PWM45 signal is used by the deadtime logic."]
311 pub const SM2SEL45_0: u16 = 0;
312 #[doc = "Inverted generated SM2PWM45 signal is used by the deadtime logic."]
313 pub const SM2SEL45_1: u16 = 0x01;
314 #[doc = "SWCOUT\\[SM2OUT45\\] is used by the deadtime logic."]
315 pub const SM2SEL45_2: u16 = 0x02;
316 #[doc = "PWM2_EXTB signal is used by the deadtime logic."]
317 pub const SM2SEL45_3: u16 = 0x03;
318 }
319 }
320 #[doc = "Submodule 2 PWM23 Control Select"]
321 pub mod SM2SEL23 {
322 pub const offset: u16 = 10;
323 pub const mask: u16 = 0x03 << offset;
324 pub mod R {}
325 pub mod W {}
326 pub mod RW {
327 #[doc = "Generated SM2PWM23 signal is used by the deadtime logic."]
328 pub const SM2SEL23_0: u16 = 0;
329 #[doc = "Inverted generated SM2PWM23 signal is used by the deadtime logic."]
330 pub const SM2SEL23_1: u16 = 0x01;
331 #[doc = "SWCOUT\\[SM2OUT23\\] is used by the deadtime logic."]
332 pub const SM2SEL23_2: u16 = 0x02;
333 #[doc = "PWM2_EXTA signal is used by the deadtime logic."]
334 pub const SM2SEL23_3: u16 = 0x03;
335 }
336 }
337 #[doc = "Submodule 3 PWM45 Control Select"]
338 pub mod SM3SEL45 {
339 pub const offset: u16 = 12;
340 pub const mask: u16 = 0x03 << offset;
341 pub mod R {}
342 pub mod W {}
343 pub mod RW {
344 #[doc = "Generated SM3PWM45 signal is used by the deadtime logic."]
345 pub const SM3SEL45_0: u16 = 0;
346 #[doc = "Inverted generated SM3PWM45 signal is used by the deadtime logic."]
347 pub const SM3SEL45_1: u16 = 0x01;
348 #[doc = "SWCOUT\\[SM3OUT45\\] is used by the deadtime logic."]
349 pub const SM3SEL45_2: u16 = 0x02;
350 #[doc = "PWM3_EXTB signal is used by the deadtime logic."]
351 pub const SM3SEL45_3: u16 = 0x03;
352 }
353 }
354 #[doc = "Submodule 3 PWM23 Control Select"]
355 pub mod SM3SEL23 {
356 pub const offset: u16 = 14;
357 pub const mask: u16 = 0x03 << offset;
358 pub mod R {}
359 pub mod W {}
360 pub mod RW {
361 #[doc = "Generated SM3PWM23 signal is used by the deadtime logic."]
362 pub const SM3SEL23_0: u16 = 0;
363 #[doc = "Inverted generated SM3PWM23 signal is used by the deadtime logic."]
364 pub const SM3SEL23_1: u16 = 0x01;
365 #[doc = "SWCOUT\\[SM3OUT23\\] is used by the deadtime logic."]
366 pub const SM3SEL23_2: u16 = 0x02;
367 #[doc = "PWM3_EXTA signal is used by the deadtime logic."]
368 pub const SM3SEL23_3: u16 = 0x03;
369 }
370 }
371}
372#[doc = "Master Control Register"]
373pub mod MCTRL {
374 #[doc = "Load Okay"]
375 pub mod LDOK {
376 pub const offset: u16 = 0;
377 pub const mask: u16 = 0x0f << offset;
378 pub mod R {}
379 pub mod W {}
380 pub mod RW {
381 #[doc = "Do not load new values."]
382 pub const LDOK_0: u16 = 0;
383 #[doc = "Load prescaler, modulus, and PWM values of the corresponding submodule."]
384 pub const LDOK_1: u16 = 0x01;
385 }
386 }
387 #[doc = "Clear Load Okay"]
388 pub mod CLDOK {
389 pub const offset: u16 = 4;
390 pub const mask: u16 = 0x0f << offset;
391 pub mod R {}
392 pub mod W {}
393 pub mod RW {}
394 }
395 #[doc = "Run"]
396 pub mod RUN {
397 pub const offset: u16 = 8;
398 pub const mask: u16 = 0x0f << offset;
399 pub mod R {}
400 pub mod W {}
401 pub mod RW {
402 #[doc = "PWM generator is disabled in the corresponding submodule."]
403 pub const RUN_0: u16 = 0;
404 #[doc = "PWM generator is enabled in the corresponding submodule."]
405 pub const RUN_1: u16 = 0x01;
406 }
407 }
408 #[doc = "Current Polarity"]
409 pub mod IPOL {
410 pub const offset: u16 = 12;
411 pub const mask: u16 = 0x0f << offset;
412 pub mod R {}
413 pub mod W {}
414 pub mod RW {
415 #[doc = "PWM23 is used to generate complementary PWM pair in the corresponding submodule."]
416 pub const IPOL_0: u16 = 0;
417 #[doc = "PWM45 is used to generate complementary PWM pair in the corresponding submodule."]
418 pub const IPOL_1: u16 = 0x01;
419 }
420 }
421}
422#[doc = "Master Control 2 Register"]
423pub mod MCTRL2 {
424 #[doc = "Monitor PLL State"]
425 pub mod MONPLL {
426 pub const offset: u16 = 0;
427 pub const mask: u16 = 0x03 << offset;
428 pub mod R {}
429 pub mod W {}
430 pub mod RW {
431 #[doc = "Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software."]
432 pub const MONPLL_0: u16 = 0;
433 #[doc = "Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems."]
434 pub const MONPLL_1: u16 = 0x01;
435 #[doc = "Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset."]
436 pub const MONPLL_2: u16 = 0x02;
437 #[doc = "Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset."]
438 pub const MONPLL_3: u16 = 0x03;
439 }
440 }
441}
442#[doc = "Fault Control Register"]
443pub mod FCTRL0 {
444 #[doc = "Fault Interrupt Enables"]
445 pub mod FIE {
446 pub const offset: u16 = 0;
447 pub const mask: u16 = 0x0f << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {
451 #[doc = "FAULTx CPU interrupt requests disabled."]
452 pub const FIE_0: u16 = 0;
453 #[doc = "FAULTx CPU interrupt requests enabled."]
454 pub const FIE_1: u16 = 0x01;
455 }
456 }
457 #[doc = "Fault Safety Mode"]
458 pub mod FSAFE {
459 pub const offset: u16 = 4;
460 pub const mask: u16 = 0x0f << offset;
461 pub mod R {}
462 pub mod W {}
463 pub mod RW {
464 #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is setm then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."]
465 pub const FSAFE_0: u16 = 0;
466 #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."]
467 pub const FSAFE_1: u16 = 0x01;
468 }
469 }
470 #[doc = "Automatic Fault Clearing"]
471 pub mod FAUTO {
472 pub const offset: u16 = 8;
473 pub const mask: u16 = 0x0f << offset;
474 pub mod R {}
475 pub mod W {}
476 pub mod RW {
477 #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."]
478 pub const FAUTO_0: u16 = 0;
479 #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."]
480 pub const FAUTO_1: u16 = 0x01;
481 }
482 }
483 #[doc = "Fault Level"]
484 pub mod FLVL {
485 pub const offset: u16 = 12;
486 pub const mask: u16 = 0x0f << offset;
487 pub mod R {}
488 pub mod W {}
489 pub mod RW {
490 #[doc = "A logic 0 on the fault input indicates a fault condition."]
491 pub const FLVL_0: u16 = 0;
492 #[doc = "A logic 1 on the fault input indicates a fault condition."]
493 pub const FLVL_1: u16 = 0x01;
494 }
495 }
496}
497#[doc = "Fault Status Register"]
498pub mod FSTS0 {
499 #[doc = "Fault Flags"]
500 pub mod FFLAG {
501 pub const offset: u16 = 0;
502 pub const mask: u16 = 0x0f << offset;
503 pub mod R {}
504 pub mod W {}
505 pub mod RW {
506 #[doc = "No fault on the FAULTx pin."]
507 pub const FFLAG_0: u16 = 0;
508 #[doc = "Fault on the FAULTx pin."]
509 pub const FFLAG_1: u16 = 0x01;
510 }
511 }
512 #[doc = "Full Cycle"]
513 pub mod FFULL {
514 pub const offset: u16 = 4;
515 pub const mask: u16 = 0x0f << offset;
516 pub mod R {}
517 pub mod W {}
518 pub mod RW {
519 #[doc = "PWM outputs are not re-enabled at the start of a full cycle"]
520 pub const FFULL_0: u16 = 0;
521 #[doc = "PWM outputs are re-enabled at the start of a full cycle"]
522 pub const FFULL_1: u16 = 0x01;
523 }
524 }
525 #[doc = "Filtered Fault Pins"]
526 pub mod FFPIN {
527 pub const offset: u16 = 8;
528 pub const mask: u16 = 0x0f << offset;
529 pub mod R {}
530 pub mod W {}
531 pub mod RW {}
532 }
533 #[doc = "Half Cycle Fault Recovery"]
534 pub mod FHALF {
535 pub const offset: u16 = 12;
536 pub const mask: u16 = 0x0f << offset;
537 pub mod R {}
538 pub mod W {}
539 pub mod RW {
540 #[doc = "PWM outputs are not re-enabled at the start of a half cycle."]
541 pub const FHALF_0: u16 = 0;
542 #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."]
543 pub const FHALF_1: u16 = 0x01;
544 }
545 }
546}
547#[doc = "Fault Filter Register"]
548pub mod FFILT0 {
549 #[doc = "Fault Filter Period"]
550 pub mod FILT_PER {
551 pub const offset: u16 = 0;
552 pub const mask: u16 = 0xff << offset;
553 pub mod R {}
554 pub mod W {}
555 pub mod RW {}
556 }
557 #[doc = "Fault Filter Count"]
558 pub mod FILT_CNT {
559 pub const offset: u16 = 8;
560 pub const mask: u16 = 0x07 << offset;
561 pub mod R {}
562 pub mod W {}
563 pub mod RW {}
564 }
565 #[doc = "Fault Glitch Stretch Enable"]
566 pub mod GSTR {
567 pub const offset: u16 = 15;
568 pub const mask: u16 = 0x01 << offset;
569 pub mod R {}
570 pub mod W {}
571 pub mod RW {
572 #[doc = "Fault input glitch stretching is disabled."]
573 pub const GSTR_0: u16 = 0;
574 #[doc = "Input fault signals will be stretched to at least 2 IPBus clock cycles."]
575 pub const GSTR_1: u16 = 0x01;
576 }
577 }
578}
579#[doc = "Fault Test Register"]
580pub mod FTST0 {
581 #[doc = "Fault Test"]
582 pub mod FTEST {
583 pub const offset: u16 = 0;
584 pub const mask: u16 = 0x01 << offset;
585 pub mod R {}
586 pub mod W {}
587 pub mod RW {
588 #[doc = "No fault"]
589 pub const FTEST_0: u16 = 0;
590 #[doc = "Cause a simulated fault"]
591 pub const FTEST_1: u16 = 0x01;
592 }
593 }
594}
595#[doc = "Fault Control 2 Register"]
596pub mod FCTRL20 {
597 #[doc = "No Combinational Path From Fault Input To PWM Output"]
598 pub mod NOCOMB {
599 pub const offset: u16 = 0;
600 pub const mask: u16 = 0x0f << offset;
601 pub mod R {}
602 pub mod W {}
603 pub mod RW {
604 #[doc = "There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."]
605 pub const NOCOMB_0: u16 = 0;
606 #[doc = "The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."]
607 pub const NOCOMB_1: u16 = 0x01;
608 }
609 }
610}
611pub mod sm {
612 #[doc = "Cluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, SM?CTRL, SM?VAL0, SM?FRACVAL1, SM?VAL1, SM?FRACVAL2, SM?VAL2, SM?FRACVAL3, SM?VAL3, SM?FRACVAL4, SM?VAL4, SM?FRACVAL5, SM?VAL5, SM?FRCTRL, SM?OCTRL, SM?STS, SM?INTEN, SM?DMAEN, SM?TCTRL, SM?DISMAP0, SM?DISMAP1, SM?DTCNT0, SM?DTCNT1, SM?CAPTCTRLA, SM?CAPTCOMPA, SM?CAPTCTRLB, SM?CAPTCOMPB, SM?CAPTCTRLX, SM?CAPTCOMPX, SM?CVAL0, SM?CVAL0CYC, SM?CVAL1, SM?CVAL1CYC, SM?CVAL2, SM?CVAL2CYC, SM?CVAL3, SM?CVAL3CYC, SM?CVAL4, SM?CVAL4CYC, SM?CVAL5, SM?CVAL5CYC, SM?PHASEDLY"]
613 #[repr(C)]
614 pub struct RegisterBlock {
615 #[doc = "Counter Register"]
616 pub SMCNT: crate::RORegister<u16>,
617 #[doc = "Initial Count Register"]
618 pub SMINIT: crate::RWRegister<u16>,
619 #[doc = "Control 2 Register"]
620 pub SMCTRL2: crate::RWRegister<u16>,
621 #[doc = "Control Register"]
622 pub SMCTRL: crate::RWRegister<u16>,
623 _reserved0: [u8; 0x02],
624 #[doc = "Value Register 0"]
625 pub SMVAL0: crate::RWRegister<u16>,
626 #[doc = "Fractional Value Register 1"]
627 pub SMFRACVAL1: crate::RWRegister<u16>,
628 #[doc = "Value Register 1"]
629 pub SMVAL1: crate::RWRegister<u16>,
630 #[doc = "Fractional Value Register 2"]
631 pub SMFRACVAL2: crate::RWRegister<u16>,
632 #[doc = "Value Register 2"]
633 pub SMVAL2: crate::RWRegister<u16>,
634 #[doc = "Fractional Value Register 3"]
635 pub SMFRACVAL3: crate::RWRegister<u16>,
636 #[doc = "Value Register 3"]
637 pub SMVAL3: crate::RWRegister<u16>,
638 #[doc = "Fractional Value Register 4"]
639 pub SMFRACVAL4: crate::RWRegister<u16>,
640 #[doc = "Value Register 4"]
641 pub SMVAL4: crate::RWRegister<u16>,
642 #[doc = "Fractional Value Register 5"]
643 pub SMFRACVAL5: crate::RWRegister<u16>,
644 #[doc = "Value Register 5"]
645 pub SMVAL5: crate::RWRegister<u16>,
646 #[doc = "Fractional Control Register"]
647 pub SMFRCTRL: crate::RWRegister<u16>,
648 #[doc = "Output Control Register"]
649 pub SMOCTRL: crate::RWRegister<u16>,
650 #[doc = "Status Register"]
651 pub SMSTS: crate::RWRegister<u16>,
652 #[doc = "Interrupt Enable Register"]
653 pub SMINTEN: crate::RWRegister<u16>,
654 #[doc = "DMA Enable Register"]
655 pub SMDMAEN: crate::RWRegister<u16>,
656 #[doc = "Output Trigger Control Register"]
657 pub SMTCTRL: crate::RWRegister<u16>,
658 #[doc = "Fault Disable Mapping Register 0"]
659 pub SMDISMAP0: crate::RWRegister<u16>,
660 #[doc = "Fault Disable Mapping Register 1"]
661 pub SMDISMAP1: crate::RWRegister<u16>,
662 #[doc = "Deadtime Count Register 0"]
663 pub SMDTCNT0: crate::RWRegister<u16>,
664 #[doc = "Deadtime Count Register 1"]
665 pub SMDTCNT1: crate::RWRegister<u16>,
666 #[doc = "Capture Control A Register"]
667 pub SMCAPTCTRLA: crate::RWRegister<u16>,
668 #[doc = "Capture Compare A Register"]
669 pub SMCAPTCOMPA: crate::RWRegister<u16>,
670 #[doc = "Capture Control B Register"]
671 pub SMCAPTCTRLB: crate::RWRegister<u16>,
672 #[doc = "Capture Compare B Register"]
673 pub SMCAPTCOMPB: crate::RWRegister<u16>,
674 #[doc = "Capture Control X Register"]
675 pub SMCAPTCTRLX: crate::RWRegister<u16>,
676 #[doc = "Capture Compare X Register"]
677 pub SMCAPTCOMPX: crate::RWRegister<u16>,
678 #[doc = "Capture Value 0 Register"]
679 pub SMCVAL0: crate::RORegister<u16>,
680 #[doc = "Capture Value 0 Cycle Register"]
681 pub SMCVAL0CYC: crate::RORegister<u16>,
682 #[doc = "Capture Value 1 Register"]
683 pub SMCVAL1: crate::RORegister<u16>,
684 #[doc = "Capture Value 1 Cycle Register"]
685 pub SMCVAL1CYC: crate::RORegister<u16>,
686 #[doc = "Capture Value 2 Register"]
687 pub SMCVAL2: crate::RORegister<u16>,
688 #[doc = "Capture Value 2 Cycle Register"]
689 pub SMCVAL2CYC: crate::RORegister<u16>,
690 #[doc = "Capture Value 3 Register"]
691 pub SMCVAL3: crate::RORegister<u16>,
692 #[doc = "Capture Value 3 Cycle Register"]
693 pub SMCVAL3CYC: crate::RORegister<u16>,
694 #[doc = "Capture Value 4 Register"]
695 pub SMCVAL4: crate::RORegister<u16>,
696 #[doc = "Capture Value 4 Cycle Register"]
697 pub SMCVAL4CYC: crate::RORegister<u16>,
698 #[doc = "Capture Value 5 Register"]
699 pub SMCVAL5: crate::RORegister<u16>,
700 #[doc = "Capture Value 5 Cycle Register"]
701 pub SMCVAL5CYC: crate::RORegister<u16>,
702 #[doc = "Phase Delay Register"]
703 pub SMPHASEDLY: crate::RWRegister<u16>,
704 _reserved1: [u8; 0x06],
705 }
706 #[doc = "Counter Register"]
707 pub mod SMCNT {
708 #[doc = "Counter Register Bits"]
709 pub mod CNT {
710 pub const offset: u16 = 0;
711 pub const mask: u16 = 0xffff << offset;
712 pub mod R {}
713 pub mod W {}
714 pub mod RW {}
715 }
716 }
717 #[doc = "Initial Count Register"]
718 pub mod SMINIT {
719 #[doc = "Initial Count Register Bits"]
720 pub mod INIT {
721 pub const offset: u16 = 0;
722 pub const mask: u16 = 0xffff << offset;
723 pub mod R {}
724 pub mod W {}
725 pub mod RW {}
726 }
727 }
728 #[doc = "Control 2 Register"]
729 pub mod SMCTRL2 {
730 #[doc = "Clock Source Select"]
731 pub mod CLK_SEL {
732 pub const offset: u16 = 0;
733 pub const mask: u16 = 0x03 << offset;
734 pub mod R {}
735 pub mod W {}
736 pub mod RW {
737 #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."]
738 pub const CLK_SEL_0: u16 = 0;
739 #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."]
740 pub const CLK_SEL_1: u16 = 0x01;
741 #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0."]
742 pub const CLK_SEL_2: u16 = 0x02;
743 }
744 }
745 #[doc = "Reload Source Select"]
746 pub mod RELOAD_SEL {
747 pub const offset: u16 = 2;
748 pub const mask: u16 = 0x01 << offset;
749 pub mod R {}
750 pub mod W {}
751 pub mod RW {
752 #[doc = "The local RELOAD signal is used to reload registers."]
753 pub const RELOAD_SEL_0: u16 = 0;
754 #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0."]
755 pub const RELOAD_SEL_1: u16 = 0x01;
756 }
757 }
758 #[doc = "This read/write bit determines the source of the FORCE OUTPUT signal for this submodule."]
759 pub mod FORCE_SEL {
760 pub const offset: u16 = 3;
761 pub const mask: u16 = 0x07 << offset;
762 pub mod R {}
763 pub mod W {}
764 pub mod RW {
765 #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."]
766 pub const FORCE_SEL_0: u16 = 0;
767 #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0."]
768 pub const FORCE_SEL_1: u16 = 0x01;
769 #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."]
770 pub const FORCE_SEL_2: u16 = 0x02;
771 #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0."]
772 pub const FORCE_SEL_3: u16 = 0x03;
773 #[doc = "The local sync signal from this submodule is used to force updates."]
774 pub const FORCE_SEL_4: u16 = 0x04;
775 #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0."]
776 pub const FORCE_SEL_5: u16 = 0x05;
777 #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."]
778 pub const FORCE_SEL_6: u16 = 0x06;
779 #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."]
780 pub const FORCE_SEL_7: u16 = 0x07;
781 }
782 }
783 #[doc = "Force Initialization"]
784 pub mod FORCE {
785 pub const offset: u16 = 6;
786 pub const mask: u16 = 0x01 << offset;
787 pub mod R {}
788 pub mod W {}
789 pub mod RW {}
790 }
791 #[doc = "FRCEN"]
792 pub mod FRCEN {
793 pub const offset: u16 = 7;
794 pub const mask: u16 = 0x01 << offset;
795 pub mod R {}
796 pub mod W {}
797 pub mod RW {
798 #[doc = "Initialization from a FORCE_OUT is disabled."]
799 pub const FRCEN_0: u16 = 0;
800 #[doc = "Initialization from a FORCE_OUT is enabled."]
801 pub const FRCEN_1: u16 = 0x01;
802 }
803 }
804 #[doc = "Initialization Control Select"]
805 pub mod INIT_SEL {
806 pub const offset: u16 = 8;
807 pub const mask: u16 = 0x03 << offset;
808 pub mod R {}
809 pub mod W {}
810 pub mod RW {
811 #[doc = "Local sync (PWM_X) causes initialization."]
812 pub const INIT_SEL_0: u16 = 0;
813 #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs."]
814 pub const INIT_SEL_1: u16 = 0x01;
815 #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0."]
816 pub const INIT_SEL_2: u16 = 0x02;
817 #[doc = "EXT_SYNC causes initialization."]
818 pub const INIT_SEL_3: u16 = 0x03;
819 }
820 }
821 #[doc = "PWM_X Initial Value"]
822 pub mod PWMX_INIT {
823 pub const offset: u16 = 10;
824 pub const mask: u16 = 0x01 << offset;
825 pub mod R {}
826 pub mod W {}
827 pub mod RW {}
828 }
829 #[doc = "PWM45 Initial Value"]
830 pub mod PWM45_INIT {
831 pub const offset: u16 = 11;
832 pub const mask: u16 = 0x01 << offset;
833 pub mod R {}
834 pub mod W {}
835 pub mod RW {}
836 }
837 #[doc = "PWM23 Initial Value"]
838 pub mod PWM23_INIT {
839 pub const offset: u16 = 12;
840 pub const mask: u16 = 0x01 << offset;
841 pub mod R {}
842 pub mod W {}
843 pub mod RW {}
844 }
845 #[doc = "Independent or Complementary Pair Operation"]
846 pub mod INDEP {
847 pub const offset: u16 = 13;
848 pub const mask: u16 = 0x01 << offset;
849 pub mod R {}
850 pub mod W {}
851 pub mod RW {
852 #[doc = "PWM_A and PWM_B form a complementary PWM pair."]
853 pub const INDEP_0: u16 = 0;
854 #[doc = "PWM_A and PWM_B outputs are independent PWMs."]
855 pub const INDEP_1: u16 = 0x01;
856 }
857 }
858 #[doc = "WAIT Enable"]
859 pub mod WAITEN {
860 pub const offset: u16 = 14;
861 pub const mask: u16 = 0x01 << offset;
862 pub mod R {}
863 pub mod W {}
864 pub mod RW {}
865 }
866 #[doc = "Debug Enable"]
867 pub mod DBGEN {
868 pub const offset: u16 = 15;
869 pub const mask: u16 = 0x01 << offset;
870 pub mod R {}
871 pub mod W {}
872 pub mod RW {}
873 }
874 }
875 #[doc = "Control Register"]
876 pub mod SMCTRL {
877 #[doc = "Double Switching Enable"]
878 pub mod DBLEN {
879 pub const offset: u16 = 0;
880 pub const mask: u16 = 0x01 << offset;
881 pub mod R {}
882 pub mod W {}
883 pub mod RW {
884 #[doc = "Double switching disabled."]
885 pub const DBLEN_0: u16 = 0;
886 #[doc = "Double switching enabled."]
887 pub const DBLEN_1: u16 = 0x01;
888 }
889 }
890 #[doc = "PWMX Double Switching Enable"]
891 pub mod DBLX {
892 pub const offset: u16 = 1;
893 pub const mask: u16 = 0x01 << offset;
894 pub mod R {}
895 pub mod W {}
896 pub mod RW {
897 #[doc = "PWMX double pulse disabled."]
898 pub const DBLX_0: u16 = 0;
899 #[doc = "PWMX double pulse enabled."]
900 pub const DBLX_1: u16 = 0x01;
901 }
902 }
903 #[doc = "Load Mode Select"]
904 pub mod LDMOD {
905 pub const offset: u16 = 2;
906 pub const mask: u16 = 0x01 << offset;
907 pub mod R {}
908 pub mod W {}
909 pub mod RW {
910 #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."]
911 pub const LDMOD_0: u16 = 0;
912 #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."]
913 pub const LDMOD_1: u16 = 0x01;
914 }
915 }
916 #[doc = "Split the DBLPWM signal to PWMA and PWMB"]
917 pub mod SPLIT {
918 pub const offset: u16 = 3;
919 pub const mask: u16 = 0x01 << offset;
920 pub mod R {}
921 pub mod W {}
922 pub mod RW {
923 #[doc = "DBLPWM is not split. PWMA and PWMB each have double pulses."]
924 pub const SPLIT_0: u16 = 0;
925 #[doc = "DBLPWM is split to PWMA and PWMB."]
926 pub const SPLIT_1: u16 = 0x01;
927 }
928 }
929 #[doc = "Prescaler"]
930 pub mod PRSC {
931 pub const offset: u16 = 4;
932 pub const mask: u16 = 0x07 << offset;
933 pub mod R {}
934 pub mod W {}
935 pub mod RW {
936 #[doc = "PWM clock frequency = fclk"]
937 pub const PRSC_0: u16 = 0;
938 #[doc = "PWM clock frequency = fclk/2"]
939 pub const PRSC_1: u16 = 0x01;
940 #[doc = "PWM clock frequency = fclk/4"]
941 pub const PRSC_2: u16 = 0x02;
942 #[doc = "PWM clock frequency = fclk/8"]
943 pub const PRSC_3: u16 = 0x03;
944 #[doc = "PWM clock frequency = fclk/16"]
945 pub const PRSC_4: u16 = 0x04;
946 #[doc = "PWM clock frequency = fclk/32"]
947 pub const PRSC_5: u16 = 0x05;
948 #[doc = "PWM clock frequency = fclk/64"]
949 pub const PRSC_6: u16 = 0x06;
950 #[doc = "PWM clock frequency = fclk/128"]
951 pub const PRSC_7: u16 = 0x07;
952 }
953 }
954 #[doc = "Compare Mode"]
955 pub mod COMPMODE {
956 pub const offset: u16 = 7;
957 pub const mask: u16 = 0x01 << offset;
958 pub mod R {}
959 pub mod W {}
960 pub mod RW {
961 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period."]
962 pub const COMPMODE_0: u16 = 0;
963 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."]
964 pub const COMPMODE_1: u16 = 0x01;
965 }
966 }
967 #[doc = "Deadtime"]
968 pub mod DT {
969 pub const offset: u16 = 8;
970 pub const mask: u16 = 0x03 << offset;
971 pub mod R {}
972 pub mod W {}
973 pub mod RW {}
974 }
975 #[doc = "Full Cycle Reload"]
976 pub mod FULL {
977 pub const offset: u16 = 10;
978 pub const mask: u16 = 0x01 << offset;
979 pub mod R {}
980 pub mod W {}
981 pub mod RW {
982 #[doc = "Full-cycle reloads disabled."]
983 pub const FULL_0: u16 = 0;
984 #[doc = "Full-cycle reloads enabled."]
985 pub const FULL_1: u16 = 0x01;
986 }
987 }
988 #[doc = "Half Cycle Reload"]
989 pub mod HALF {
990 pub const offset: u16 = 11;
991 pub const mask: u16 = 0x01 << offset;
992 pub mod R {}
993 pub mod W {}
994 pub mod RW {
995 #[doc = "Half-cycle reloads disabled."]
996 pub const HALF_0: u16 = 0;
997 #[doc = "Half-cycle reloads enabled."]
998 pub const HALF_1: u16 = 0x01;
999 }
1000 }
1001 #[doc = "Load Frequency"]
1002 pub mod LDFQ {
1003 pub const offset: u16 = 12;
1004 pub const mask: u16 = 0x0f << offset;
1005 pub mod R {}
1006 pub mod W {}
1007 pub mod RW {
1008 #[doc = "Every PWM opportunity"]
1009 pub const LDFQ_0: u16 = 0;
1010 #[doc = "Every 2 PWM opportunities"]
1011 pub const LDFQ_1: u16 = 0x01;
1012 #[doc = "Every 3 PWM opportunities"]
1013 pub const LDFQ_2: u16 = 0x02;
1014 #[doc = "Every 4 PWM opportunities"]
1015 pub const LDFQ_3: u16 = 0x03;
1016 #[doc = "Every 5 PWM opportunities"]
1017 pub const LDFQ_4: u16 = 0x04;
1018 #[doc = "Every 6 PWM opportunities"]
1019 pub const LDFQ_5: u16 = 0x05;
1020 #[doc = "Every 7 PWM opportunities"]
1021 pub const LDFQ_6: u16 = 0x06;
1022 #[doc = "Every 8 PWM opportunities"]
1023 pub const LDFQ_7: u16 = 0x07;
1024 #[doc = "Every 9 PWM opportunities"]
1025 pub const LDFQ_8: u16 = 0x08;
1026 #[doc = "Every 10 PWM opportunities"]
1027 pub const LDFQ_9: u16 = 0x09;
1028 #[doc = "Every 11 PWM opportunities"]
1029 pub const LDFQ_10: u16 = 0x0a;
1030 #[doc = "Every 12 PWM opportunities"]
1031 pub const LDFQ_11: u16 = 0x0b;
1032 #[doc = "Every 13 PWM opportunities"]
1033 pub const LDFQ_12: u16 = 0x0c;
1034 #[doc = "Every 14 PWM opportunities"]
1035 pub const LDFQ_13: u16 = 0x0d;
1036 #[doc = "Every 15 PWM opportunities"]
1037 pub const LDFQ_14: u16 = 0x0e;
1038 #[doc = "Every 16 PWM opportunities"]
1039 pub const LDFQ_15: u16 = 0x0f;
1040 }
1041 }
1042 }
1043 #[doc = "Value Register 0"]
1044 pub mod SMVAL0 {
1045 #[doc = "Value Register 0"]
1046 pub mod VAL0 {
1047 pub const offset: u16 = 0;
1048 pub const mask: u16 = 0xffff << offset;
1049 pub mod R {}
1050 pub mod W {}
1051 pub mod RW {}
1052 }
1053 }
1054 #[doc = "Fractional Value Register 1"]
1055 pub mod SMFRACVAL1 {
1056 #[doc = "Fractional Value 1 Register"]
1057 pub mod FRACVAL1 {
1058 pub const offset: u16 = 11;
1059 pub const mask: u16 = 0x1f << offset;
1060 pub mod R {}
1061 pub mod W {}
1062 pub mod RW {}
1063 }
1064 }
1065 #[doc = "Value Register 1"]
1066 pub mod SMVAL1 {
1067 #[doc = "Value Register 1"]
1068 pub mod VAL1 {
1069 pub const offset: u16 = 0;
1070 pub const mask: u16 = 0xffff << offset;
1071 pub mod R {}
1072 pub mod W {}
1073 pub mod RW {}
1074 }
1075 }
1076 #[doc = "Fractional Value Register 2"]
1077 pub mod SMFRACVAL2 {
1078 #[doc = "Fractional Value 2"]
1079 pub mod FRACVAL2 {
1080 pub const offset: u16 = 11;
1081 pub const mask: u16 = 0x1f << offset;
1082 pub mod R {}
1083 pub mod W {}
1084 pub mod RW {}
1085 }
1086 }
1087 #[doc = "Value Register 2"]
1088 pub mod SMVAL2 {
1089 #[doc = "Value Register 2"]
1090 pub mod VAL2 {
1091 pub const offset: u16 = 0;
1092 pub const mask: u16 = 0xffff << offset;
1093 pub mod R {}
1094 pub mod W {}
1095 pub mod RW {}
1096 }
1097 }
1098 #[doc = "Fractional Value Register 3"]
1099 pub mod SMFRACVAL3 {
1100 #[doc = "Fractional Value 3"]
1101 pub mod FRACVAL3 {
1102 pub const offset: u16 = 11;
1103 pub const mask: u16 = 0x1f << offset;
1104 pub mod R {}
1105 pub mod W {}
1106 pub mod RW {}
1107 }
1108 }
1109 #[doc = "Value Register 3"]
1110 pub mod SMVAL3 {
1111 #[doc = "Value Register 3"]
1112 pub mod VAL3 {
1113 pub const offset: u16 = 0;
1114 pub const mask: u16 = 0xffff << offset;
1115 pub mod R {}
1116 pub mod W {}
1117 pub mod RW {}
1118 }
1119 }
1120 #[doc = "Fractional Value Register 4"]
1121 pub mod SMFRACVAL4 {
1122 #[doc = "Fractional Value 4"]
1123 pub mod FRACVAL4 {
1124 pub const offset: u16 = 11;
1125 pub const mask: u16 = 0x1f << offset;
1126 pub mod R {}
1127 pub mod W {}
1128 pub mod RW {}
1129 }
1130 }
1131 #[doc = "Value Register 4"]
1132 pub mod SMVAL4 {
1133 #[doc = "Value Register 4"]
1134 pub mod VAL4 {
1135 pub const offset: u16 = 0;
1136 pub const mask: u16 = 0xffff << offset;
1137 pub mod R {}
1138 pub mod W {}
1139 pub mod RW {}
1140 }
1141 }
1142 #[doc = "Fractional Value Register 5"]
1143 pub mod SMFRACVAL5 {
1144 #[doc = "Fractional Value 5"]
1145 pub mod FRACVAL5 {
1146 pub const offset: u16 = 11;
1147 pub const mask: u16 = 0x1f << offset;
1148 pub mod R {}
1149 pub mod W {}
1150 pub mod RW {}
1151 }
1152 }
1153 #[doc = "Value Register 5"]
1154 pub mod SMVAL5 {
1155 #[doc = "Value Register 5"]
1156 pub mod VAL5 {
1157 pub const offset: u16 = 0;
1158 pub const mask: u16 = 0xffff << offset;
1159 pub mod R {}
1160 pub mod W {}
1161 pub mod RW {}
1162 }
1163 }
1164 #[doc = "Fractional Control Register"]
1165 pub mod SMFRCTRL {
1166 #[doc = "Fractional Cycle PWM Period Enable"]
1167 pub mod FRAC1_EN {
1168 pub const offset: u16 = 1;
1169 pub const mask: u16 = 0x01 << offset;
1170 pub mod R {}
1171 pub mod W {}
1172 pub mod RW {
1173 #[doc = "Disable fractional cycle length for the PWM period."]
1174 pub const FRAC1_EN_0: u16 = 0;
1175 #[doc = "Enable fractional cycle length for the PWM period."]
1176 pub const FRAC1_EN_1: u16 = 0x01;
1177 }
1178 }
1179 #[doc = "Fractional Cycle Placement Enable for PWM_A"]
1180 pub mod FRAC23_EN {
1181 pub const offset: u16 = 2;
1182 pub const mask: u16 = 0x01 << offset;
1183 pub mod R {}
1184 pub mod W {}
1185 pub mod RW {
1186 #[doc = "Disable fractional cycle placement for PWM_A."]
1187 pub const FRAC23_EN_0: u16 = 0;
1188 #[doc = "Enable fractional cycle placement for PWM_A."]
1189 pub const FRAC23_EN_1: u16 = 0x01;
1190 }
1191 }
1192 #[doc = "Fractional Cycle Placement Enable for PWM_B"]
1193 pub mod FRAC45_EN {
1194 pub const offset: u16 = 4;
1195 pub const mask: u16 = 0x01 << offset;
1196 pub mod R {}
1197 pub mod W {}
1198 pub mod RW {
1199 #[doc = "Disable fractional cycle placement for PWM_B."]
1200 pub const FRAC45_EN_0: u16 = 0;
1201 #[doc = "Enable fractional cycle placement for PWM_B."]
1202 pub const FRAC45_EN_1: u16 = 0x01;
1203 }
1204 }
1205 #[doc = "Fractional Delay Circuit Power Up"]
1206 pub mod FRAC_PU {
1207 pub const offset: u16 = 8;
1208 pub const mask: u16 = 0x01 << offset;
1209 pub mod R {}
1210 pub mod W {}
1211 pub mod RW {
1212 #[doc = "Turn off fractional delay logic."]
1213 pub const FRAC_PU_0: u16 = 0;
1214 #[doc = "Power up fractional delay logic."]
1215 pub const FRAC_PU_1: u16 = 0x01;
1216 }
1217 }
1218 #[doc = "Test Status Bit"]
1219 pub mod TEST {
1220 pub const offset: u16 = 15;
1221 pub const mask: u16 = 0x01 << offset;
1222 pub mod R {}
1223 pub mod W {}
1224 pub mod RW {}
1225 }
1226 }
1227 #[doc = "Output Control Register"]
1228 pub mod SMOCTRL {
1229 #[doc = "PWM_X Fault State"]
1230 pub mod PWMXFS {
1231 pub const offset: u16 = 0;
1232 pub const mask: u16 = 0x03 << offset;
1233 pub mod R {}
1234 pub mod W {}
1235 pub mod RW {
1236 #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."]
1237 pub const PWMXFS_0: u16 = 0;
1238 #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."]
1239 pub const PWMXFS_1: u16 = 0x01;
1240 #[doc = "Output is tristated."]
1241 pub const PWMXFS_2: u16 = 0x02;
1242 #[doc = "Output is tristated."]
1243 pub const PWMXFS_3: u16 = 0x03;
1244 }
1245 }
1246 #[doc = "PWM_B Fault State"]
1247 pub mod PWMBFS {
1248 pub const offset: u16 = 2;
1249 pub const mask: u16 = 0x03 << offset;
1250 pub mod R {}
1251 pub mod W {}
1252 pub mod RW {
1253 #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."]
1254 pub const PWMBFS_0: u16 = 0;
1255 #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."]
1256 pub const PWMBFS_1: u16 = 0x01;
1257 #[doc = "Output is tristated."]
1258 pub const PWMBFS_2: u16 = 0x02;
1259 #[doc = "Output is tristated."]
1260 pub const PWMBFS_3: u16 = 0x03;
1261 }
1262 }
1263 #[doc = "PWM_A Fault State"]
1264 pub mod PWMAFS {
1265 pub const offset: u16 = 4;
1266 pub const mask: u16 = 0x03 << offset;
1267 pub mod R {}
1268 pub mod W {}
1269 pub mod RW {
1270 #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."]
1271 pub const PWMAFS_0: u16 = 0;
1272 #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."]
1273 pub const PWMAFS_1: u16 = 0x01;
1274 #[doc = "Output is tristated."]
1275 pub const PWMAFS_2: u16 = 0x02;
1276 #[doc = "Output is tristated."]
1277 pub const PWMAFS_3: u16 = 0x03;
1278 }
1279 }
1280 #[doc = "PWM_X Output Polarity"]
1281 pub mod POLX {
1282 pub const offset: u16 = 8;
1283 pub const mask: u16 = 0x01 << offset;
1284 pub mod R {}
1285 pub mod W {}
1286 pub mod RW {
1287 #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."]
1288 pub const POLX_0: u16 = 0;
1289 #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."]
1290 pub const POLX_1: u16 = 0x01;
1291 }
1292 }
1293 #[doc = "PWM_B Output Polarity"]
1294 pub mod POLB {
1295 pub const offset: u16 = 9;
1296 pub const mask: u16 = 0x01 << offset;
1297 pub mod R {}
1298 pub mod W {}
1299 pub mod RW {
1300 #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."]
1301 pub const POLB_0: u16 = 0;
1302 #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."]
1303 pub const POLB_1: u16 = 0x01;
1304 }
1305 }
1306 #[doc = "PWM_A Output Polarity"]
1307 pub mod POLA {
1308 pub const offset: u16 = 10;
1309 pub const mask: u16 = 0x01 << offset;
1310 pub mod R {}
1311 pub mod W {}
1312 pub mod RW {
1313 #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."]
1314 pub const POLA_0: u16 = 0;
1315 #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."]
1316 pub const POLA_1: u16 = 0x01;
1317 }
1318 }
1319 #[doc = "PWM_X Input"]
1320 pub mod PWMX_IN {
1321 pub const offset: u16 = 13;
1322 pub const mask: u16 = 0x01 << offset;
1323 pub mod R {}
1324 pub mod W {}
1325 pub mod RW {}
1326 }
1327 #[doc = "PWM_B Input"]
1328 pub mod PWMB_IN {
1329 pub const offset: u16 = 14;
1330 pub const mask: u16 = 0x01 << offset;
1331 pub mod R {}
1332 pub mod W {}
1333 pub mod RW {}
1334 }
1335 #[doc = "PWM_A Input"]
1336 pub mod PWMA_IN {
1337 pub const offset: u16 = 15;
1338 pub const mask: u16 = 0x01 << offset;
1339 pub mod R {}
1340 pub mod W {}
1341 pub mod RW {}
1342 }
1343 }
1344 #[doc = "Status Register"]
1345 pub mod SMSTS {
1346 #[doc = "Compare Flags"]
1347 pub mod CMPF {
1348 pub const offset: u16 = 0;
1349 pub const mask: u16 = 0x3f << offset;
1350 pub mod R {}
1351 pub mod W {}
1352 pub mod RW {
1353 #[doc = "No compare event has occurred for a particular VALx value."]
1354 pub const CMPF_0: u16 = 0;
1355 #[doc = "A compare event has occurred for a particular VALx value."]
1356 pub const CMPF_1: u16 = 0x01;
1357 }
1358 }
1359 #[doc = "Capture Flag X0"]
1360 pub mod CFX0 {
1361 pub const offset: u16 = 6;
1362 pub const mask: u16 = 0x01 << offset;
1363 pub mod R {}
1364 pub mod W {}
1365 pub mod RW {}
1366 }
1367 #[doc = "Capture Flag X1"]
1368 pub mod CFX1 {
1369 pub const offset: u16 = 7;
1370 pub const mask: u16 = 0x01 << offset;
1371 pub mod R {}
1372 pub mod W {}
1373 pub mod RW {}
1374 }
1375 #[doc = "Capture Flag B0"]
1376 pub mod CFB0 {
1377 pub const offset: u16 = 8;
1378 pub const mask: u16 = 0x01 << offset;
1379 pub mod R {}
1380 pub mod W {}
1381 pub mod RW {}
1382 }
1383 #[doc = "Capture Flag B1"]
1384 pub mod CFB1 {
1385 pub const offset: u16 = 9;
1386 pub const mask: u16 = 0x01 << offset;
1387 pub mod R {}
1388 pub mod W {}
1389 pub mod RW {}
1390 }
1391 #[doc = "Capture Flag A0"]
1392 pub mod CFA0 {
1393 pub const offset: u16 = 10;
1394 pub const mask: u16 = 0x01 << offset;
1395 pub mod R {}
1396 pub mod W {}
1397 pub mod RW {}
1398 }
1399 #[doc = "Capture Flag A1"]
1400 pub mod CFA1 {
1401 pub const offset: u16 = 11;
1402 pub const mask: u16 = 0x01 << offset;
1403 pub mod R {}
1404 pub mod W {}
1405 pub mod RW {}
1406 }
1407 #[doc = "Reload Flag"]
1408 pub mod RF {
1409 pub const offset: u16 = 12;
1410 pub const mask: u16 = 0x01 << offset;
1411 pub mod R {}
1412 pub mod W {}
1413 pub mod RW {
1414 #[doc = "No new reload cycle since last STS\\[RF\\] clearing"]
1415 pub const RF_0: u16 = 0;
1416 #[doc = "New reload cycle since last STS\\[RF\\] clearing"]
1417 pub const RF_1: u16 = 0x01;
1418 }
1419 }
1420 #[doc = "Reload Error Flag"]
1421 pub mod REF {
1422 pub const offset: u16 = 13;
1423 pub const mask: u16 = 0x01 << offset;
1424 pub mod R {}
1425 pub mod W {}
1426 pub mod RW {
1427 #[doc = "No reload error occurred."]
1428 pub const REF_0: u16 = 0;
1429 #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."]
1430 pub const REF_1: u16 = 0x01;
1431 }
1432 }
1433 #[doc = "Registers Updated Flag"]
1434 pub mod RUF {
1435 pub const offset: u16 = 14;
1436 pub const mask: u16 = 0x01 << offset;
1437 pub mod R {}
1438 pub mod W {}
1439 pub mod RW {
1440 #[doc = "No register update has occurred since last reload."]
1441 pub const RUF_0: u16 = 0;
1442 #[doc = "At least one of the double buffered registers has been updated since the last reload."]
1443 pub const RUF_1: u16 = 0x01;
1444 }
1445 }
1446 }
1447 #[doc = "Interrupt Enable Register"]
1448 pub mod SMINTEN {
1449 #[doc = "Compare Interrupt Enables"]
1450 pub mod CMPIE {
1451 pub const offset: u16 = 0;
1452 pub const mask: u16 = 0x3f << offset;
1453 pub mod R {}
1454 pub mod W {}
1455 pub mod RW {
1456 #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."]
1457 pub const CMPIE_0: u16 = 0;
1458 #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."]
1459 pub const CMPIE_1: u16 = 0x01;
1460 }
1461 }
1462 #[doc = "Capture X 0 Interrupt Enable"]
1463 pub mod CX0IE {
1464 pub const offset: u16 = 6;
1465 pub const mask: u16 = 0x01 << offset;
1466 pub mod R {}
1467 pub mod W {}
1468 pub mod RW {
1469 #[doc = "Interrupt request disabled for STS\\[CFX0\\]."]
1470 pub const CX0IE_0: u16 = 0;
1471 #[doc = "Interrupt request enabled for STS\\[CFX0\\]."]
1472 pub const CX0IE_1: u16 = 0x01;
1473 }
1474 }
1475 #[doc = "Capture X 1 Interrupt Enable"]
1476 pub mod CX1IE {
1477 pub const offset: u16 = 7;
1478 pub const mask: u16 = 0x01 << offset;
1479 pub mod R {}
1480 pub mod W {}
1481 pub mod RW {
1482 #[doc = "Interrupt request disabled for STS\\[CFX1\\]."]
1483 pub const CX1IE_0: u16 = 0;
1484 #[doc = "Interrupt request enabled for STS\\[CFX1\\]."]
1485 pub const CX1IE_1: u16 = 0x01;
1486 }
1487 }
1488 #[doc = "Capture B 0 Interrupt Enable"]
1489 pub mod CB0IE {
1490 pub const offset: u16 = 8;
1491 pub const mask: u16 = 0x01 << offset;
1492 pub mod R {}
1493 pub mod W {}
1494 pub mod RW {
1495 #[doc = "Interrupt request disabled for STS\\[CFB0\\]."]
1496 pub const CB0IE_0: u16 = 0;
1497 #[doc = "Interrupt request enabled for STS\\[CFB0\\]."]
1498 pub const CB0IE_1: u16 = 0x01;
1499 }
1500 }
1501 #[doc = "Capture B 1 Interrupt Enable"]
1502 pub mod CB1IE {
1503 pub const offset: u16 = 9;
1504 pub const mask: u16 = 0x01 << offset;
1505 pub mod R {}
1506 pub mod W {}
1507 pub mod RW {
1508 #[doc = "Interrupt request disabled for STS\\[CFB1\\]."]
1509 pub const CB1IE_0: u16 = 0;
1510 #[doc = "Interrupt request enabled for STS\\[CFB1\\]."]
1511 pub const CB1IE_1: u16 = 0x01;
1512 }
1513 }
1514 #[doc = "Capture A 0 Interrupt Enable"]
1515 pub mod CA0IE {
1516 pub const offset: u16 = 10;
1517 pub const mask: u16 = 0x01 << offset;
1518 pub mod R {}
1519 pub mod W {}
1520 pub mod RW {
1521 #[doc = "Interrupt request disabled for STS\\[CFA0\\]."]
1522 pub const CA0IE_0: u16 = 0;
1523 #[doc = "Interrupt request enabled for STS\\[CFA0\\]."]
1524 pub const CA0IE_1: u16 = 0x01;
1525 }
1526 }
1527 #[doc = "Capture A 1 Interrupt Enable"]
1528 pub mod CA1IE {
1529 pub const offset: u16 = 11;
1530 pub const mask: u16 = 0x01 << offset;
1531 pub mod R {}
1532 pub mod W {}
1533 pub mod RW {
1534 #[doc = "Interrupt request disabled for STS\\[CFA1\\]."]
1535 pub const CA1IE_0: u16 = 0;
1536 #[doc = "Interrupt request enabled for STS\\[CFA1\\]."]
1537 pub const CA1IE_1: u16 = 0x01;
1538 }
1539 }
1540 #[doc = "Reload Interrupt Enable"]
1541 pub mod RIE {
1542 pub const offset: u16 = 12;
1543 pub const mask: u16 = 0x01 << offset;
1544 pub mod R {}
1545 pub mod W {}
1546 pub mod RW {
1547 #[doc = "STS\\[RF\\] CPU interrupt requests disabled"]
1548 pub const RIE_0: u16 = 0;
1549 #[doc = "STS\\[RF\\] CPU interrupt requests enabled"]
1550 pub const RIE_1: u16 = 0x01;
1551 }
1552 }
1553 #[doc = "Reload Error Interrupt Enable"]
1554 pub mod REIE {
1555 pub const offset: u16 = 13;
1556 pub const mask: u16 = 0x01 << offset;
1557 pub mod R {}
1558 pub mod W {}
1559 pub mod RW {
1560 #[doc = "STS\\[REF\\] CPU interrupt requests disabled"]
1561 pub const REIE_0: u16 = 0;
1562 #[doc = "STS\\[REF\\] CPU interrupt requests enabled"]
1563 pub const REIE_1: u16 = 0x01;
1564 }
1565 }
1566 }
1567 #[doc = "DMA Enable Register"]
1568 pub mod SMDMAEN {
1569 #[doc = "Capture X0 FIFO DMA Enable"]
1570 pub mod CX0DE {
1571 pub const offset: u16 = 0;
1572 pub const mask: u16 = 0x01 << offset;
1573 pub mod R {}
1574 pub mod W {}
1575 pub mod RW {}
1576 }
1577 #[doc = "Capture X1 FIFO DMA Enable"]
1578 pub mod CX1DE {
1579 pub const offset: u16 = 1;
1580 pub const mask: u16 = 0x01 << offset;
1581 pub mod R {}
1582 pub mod W {}
1583 pub mod RW {}
1584 }
1585 #[doc = "Capture B0 FIFO DMA Enable"]
1586 pub mod CB0DE {
1587 pub const offset: u16 = 2;
1588 pub const mask: u16 = 0x01 << offset;
1589 pub mod R {}
1590 pub mod W {}
1591 pub mod RW {}
1592 }
1593 #[doc = "Capture B1 FIFO DMA Enable"]
1594 pub mod CB1DE {
1595 pub const offset: u16 = 3;
1596 pub const mask: u16 = 0x01 << offset;
1597 pub mod R {}
1598 pub mod W {}
1599 pub mod RW {}
1600 }
1601 #[doc = "Capture A0 FIFO DMA Enable"]
1602 pub mod CA0DE {
1603 pub const offset: u16 = 4;
1604 pub const mask: u16 = 0x01 << offset;
1605 pub mod R {}
1606 pub mod W {}
1607 pub mod RW {}
1608 }
1609 #[doc = "Capture A1 FIFO DMA Enable"]
1610 pub mod CA1DE {
1611 pub const offset: u16 = 5;
1612 pub const mask: u16 = 0x01 << offset;
1613 pub mod R {}
1614 pub mod W {}
1615 pub mod RW {}
1616 }
1617 #[doc = "Capture DMA Enable Source Select"]
1618 pub mod CAPTDE {
1619 pub const offset: u16 = 6;
1620 pub const mask: u16 = 0x03 << offset;
1621 pub mod R {}
1622 pub mod W {}
1623 pub mod RW {
1624 #[doc = "Read DMA requests disabled."]
1625 pub const CAPTDE_0: u16 = 0;
1626 #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to also be set in order to determine to which watermark(s) the DMA request is sensitive."]
1627 pub const CAPTDE_1: u16 = 0x01;
1628 #[doc = "A local sync (VAL1 matches counter) sets the read DMA request."]
1629 pub const CAPTDE_2: u16 = 0x02;
1630 #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."]
1631 pub const CAPTDE_3: u16 = 0x03;
1632 }
1633 }
1634 #[doc = "FIFO Watermark AND Control"]
1635 pub mod FAND {
1636 pub const offset: u16 = 8;
1637 pub const mask: u16 = 0x01 << offset;
1638 pub mod R {}
1639 pub mod W {}
1640 pub mod RW {
1641 #[doc = "Selected FIFO watermarks are OR'ed together."]
1642 pub const FAND_0: u16 = 0;
1643 #[doc = "Selected FIFO watermarks are AND'ed together."]
1644 pub const FAND_1: u16 = 0x01;
1645 }
1646 }
1647 #[doc = "Value Registers DMA Enable"]
1648 pub mod VALDE {
1649 pub const offset: u16 = 9;
1650 pub const mask: u16 = 0x01 << offset;
1651 pub mod R {}
1652 pub mod W {}
1653 pub mod RW {
1654 #[doc = "DMA write requests disabled"]
1655 pub const VALDE_0: u16 = 0;
1656 #[doc = "DMA write requests for the VALx and FRACVALx registers enabled"]
1657 pub const VALDE_1: u16 = 0x01;
1658 }
1659 }
1660 }
1661 #[doc = "Output Trigger Control Register"]
1662 pub mod SMTCTRL {
1663 #[doc = "Output Trigger Enables"]
1664 pub mod OUT_TRIG_EN {
1665 pub const offset: u16 = 0;
1666 pub const mask: u16 = 0x3f << offset;
1667 pub mod R {}
1668 pub mod W {}
1669 pub mod RW {
1670 #[doc = "PWM_OUT_TRIGx will not set when the counter value matches the VALx value."]
1671 pub const OUT_TRIG_EN_0: u16 = 0;
1672 #[doc = "PWM_OUT_TRIGx will set when the counter value matches the VALx value."]
1673 pub const OUT_TRIG_EN_1: u16 = 0x01;
1674 }
1675 }
1676 #[doc = "Trigger frequency"]
1677 pub mod TRGFRQ {
1678 pub const offset: u16 = 12;
1679 pub const mask: u16 = 0x01 << offset;
1680 pub mod R {}
1681 pub mod W {}
1682 pub mod RW {
1683 #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
1684 pub const TRGFRQ_0: u16 = 0;
1685 #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
1686 pub const TRGFRQ_1: u16 = 0x01;
1687 }
1688 }
1689 #[doc = "Output Trigger 1 Source Select"]
1690 pub mod PWBOT1 {
1691 pub const offset: u16 = 14;
1692 pub const mask: u16 = 0x01 << offset;
1693 pub mod R {}
1694 pub mod W {}
1695 pub mod RW {
1696 #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port."]
1697 pub const PWBOT1_0: u16 = 0;
1698 #[doc = "Route the PWMB output to the PWM_OUT_TRIG1 port."]
1699 pub const PWBOT1_1: u16 = 0x01;
1700 }
1701 }
1702 #[doc = "Output Trigger 0 Source Select"]
1703 pub mod PWAOT0 {
1704 pub const offset: u16 = 15;
1705 pub const mask: u16 = 0x01 << offset;
1706 pub mod R {}
1707 pub mod W {}
1708 pub mod RW {
1709 #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port."]
1710 pub const PWAOT0_0: u16 = 0;
1711 #[doc = "Route the PWMA output to the PWM_OUT_TRIG0 port."]
1712 pub const PWAOT0_1: u16 = 0x01;
1713 }
1714 }
1715 }
1716 #[doc = "Fault Disable Mapping Register 0"]
1717 pub mod SMDISMAP0 {
1718 #[doc = "PWM_A Fault Disable Mask 0"]
1719 pub mod DIS0A {
1720 pub const offset: u16 = 0;
1721 pub const mask: u16 = 0x0f << offset;
1722 pub mod R {}
1723 pub mod W {}
1724 pub mod RW {}
1725 }
1726 #[doc = "PWM_B Fault Disable Mask 0"]
1727 pub mod DIS0B {
1728 pub const offset: u16 = 4;
1729 pub const mask: u16 = 0x0f << offset;
1730 pub mod R {}
1731 pub mod W {}
1732 pub mod RW {}
1733 }
1734 #[doc = "PWM_X Fault Disable Mask 0"]
1735 pub mod DIS0X {
1736 pub const offset: u16 = 8;
1737 pub const mask: u16 = 0x0f << offset;
1738 pub mod R {}
1739 pub mod W {}
1740 pub mod RW {}
1741 }
1742 }
1743 #[doc = "Fault Disable Mapping Register 1"]
1744 pub mod SMDISMAP1 {
1745 #[doc = "PWM_A Fault Disable Mask 1"]
1746 pub mod DIS1A {
1747 pub const offset: u16 = 0;
1748 pub const mask: u16 = 0x0f << offset;
1749 pub mod R {}
1750 pub mod W {}
1751 pub mod RW {}
1752 }
1753 #[doc = "PWM_B Fault Disable Mask 1"]
1754 pub mod DIS1B {
1755 pub const offset: u16 = 4;
1756 pub const mask: u16 = 0x0f << offset;
1757 pub mod R {}
1758 pub mod W {}
1759 pub mod RW {}
1760 }
1761 #[doc = "PWM_X Fault Disable Mask 1"]
1762 pub mod DIS1X {
1763 pub const offset: u16 = 8;
1764 pub const mask: u16 = 0x0f << offset;
1765 pub mod R {}
1766 pub mod W {}
1767 pub mod RW {}
1768 }
1769 }
1770 #[doc = "Deadtime Count Register 0"]
1771 pub mod SMDTCNT0 {
1772 #[doc = "DTCNT0"]
1773 pub mod DTCNT0 {
1774 pub const offset: u16 = 0;
1775 pub const mask: u16 = 0xffff << offset;
1776 pub mod R {}
1777 pub mod W {}
1778 pub mod RW {}
1779 }
1780 }
1781 #[doc = "Deadtime Count Register 1"]
1782 pub mod SMDTCNT1 {
1783 #[doc = "DTCNT1"]
1784 pub mod DTCNT1 {
1785 pub const offset: u16 = 0;
1786 pub const mask: u16 = 0xffff << offset;
1787 pub mod R {}
1788 pub mod W {}
1789 pub mod RW {}
1790 }
1791 }
1792 #[doc = "Capture Control A Register"]
1793 pub mod SMCAPTCTRLA {
1794 #[doc = "Arm A"]
1795 pub mod ARMA {
1796 pub const offset: u16 = 0;
1797 pub const mask: u16 = 0x01 << offset;
1798 pub mod R {}
1799 pub mod W {}
1800 pub mod RW {
1801 #[doc = "Input capture operation is disabled."]
1802 pub const ARMA_0: u16 = 0;
1803 #[doc = "Input capture operation as specified by CAPTCTRLA\\[EDGAx\\] is enabled."]
1804 pub const ARMA_1: u16 = 0x01;
1805 }
1806 }
1807 #[doc = "One Shot Mode A"]
1808 pub mod ONESHOTA {
1809 pub const offset: u16 = 1;
1810 pub const mask: u16 = 0x01 << offset;
1811 pub mod R {}
1812 pub mod W {}
1813 pub mod RW {
1814 #[doc = "Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA\\[ARMA\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit."]
1815 pub const ONESHOTA_0: u16 = 0;
1816 #[doc = "One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA\\[ARMA\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA\\[ARMA\\] is cleared. No further captures will be performed until CAPTCTRLA\\[ARMA\\] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA\\[ARMA\\] is then cleared."]
1817 pub const ONESHOTA_1: u16 = 0x01;
1818 }
1819 }
1820 #[doc = "Edge A 0"]
1821 pub mod EDGA0 {
1822 pub const offset: u16 = 2;
1823 pub const mask: u16 = 0x03 << offset;
1824 pub mod R {}
1825 pub mod W {}
1826 pub mod RW {
1827 #[doc = "Disabled"]
1828 pub const EDGA0_0: u16 = 0;
1829 #[doc = "Capture falling edges"]
1830 pub const EDGA0_1: u16 = 0x01;
1831 #[doc = "Capture rising edges"]
1832 pub const EDGA0_2: u16 = 0x02;
1833 #[doc = "Capture any edge"]
1834 pub const EDGA0_3: u16 = 0x03;
1835 }
1836 }
1837 #[doc = "Edge A 1"]
1838 pub mod EDGA1 {
1839 pub const offset: u16 = 4;
1840 pub const mask: u16 = 0x03 << offset;
1841 pub mod R {}
1842 pub mod W {}
1843 pub mod RW {
1844 #[doc = "Disabled"]
1845 pub const EDGA1_0: u16 = 0;
1846 #[doc = "Capture falling edges"]
1847 pub const EDGA1_1: u16 = 0x01;
1848 #[doc = "Capture rising edges"]
1849 pub const EDGA1_2: u16 = 0x02;
1850 #[doc = "Capture any edge"]
1851 pub const EDGA1_3: u16 = 0x03;
1852 }
1853 }
1854 #[doc = "Input Select A"]
1855 pub mod INP_SELA {
1856 pub const offset: u16 = 6;
1857 pub const mask: u16 = 0x01 << offset;
1858 pub mod R {}
1859 pub mod W {}
1860 pub mod RW {
1861 #[doc = "Raw PWM_A input signal selected as source."]
1862 pub const INP_SELA_0: u16 = 0;
1863 #[doc = "Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA\\[EDGA0\\] and CAPTCTRLA\\[EDGA1\\] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA\\[EDGA0\\] and/or CAPTCTRLA\\[EDGA1\\] fields in order to enable one or both of the capture registers."]
1864 pub const INP_SELA_1: u16 = 0x01;
1865 }
1866 }
1867 #[doc = "Edge Counter A Enable"]
1868 pub mod EDGCNTA_EN {
1869 pub const offset: u16 = 7;
1870 pub const mask: u16 = 0x01 << offset;
1871 pub mod R {}
1872 pub mod W {}
1873 pub mod RW {
1874 #[doc = "Edge counter disabled and held in reset"]
1875 pub const EDGCNTA_EN_0: u16 = 0;
1876 #[doc = "Edge counter enabled"]
1877 pub const EDGCNTA_EN_1: u16 = 0x01;
1878 }
1879 }
1880 #[doc = "Capture A FIFOs Water Mark"]
1881 pub mod CFAWM {
1882 pub const offset: u16 = 8;
1883 pub const mask: u16 = 0x03 << offset;
1884 pub mod R {}
1885 pub mod W {}
1886 pub mod RW {}
1887 }
1888 #[doc = "Capture A0 FIFO Word Count"]
1889 pub mod CA0CNT {
1890 pub const offset: u16 = 10;
1891 pub const mask: u16 = 0x07 << offset;
1892 pub mod R {}
1893 pub mod W {}
1894 pub mod RW {}
1895 }
1896 #[doc = "Capture A1 FIFO Word Count"]
1897 pub mod CA1CNT {
1898 pub const offset: u16 = 13;
1899 pub const mask: u16 = 0x07 << offset;
1900 pub mod R {}
1901 pub mod W {}
1902 pub mod RW {}
1903 }
1904 }
1905 #[doc = "Capture Compare A Register"]
1906 pub mod SMCAPTCOMPA {
1907 #[doc = "Edge Compare A"]
1908 pub mod EDGCMPA {
1909 pub const offset: u16 = 0;
1910 pub const mask: u16 = 0xff << offset;
1911 pub mod R {}
1912 pub mod W {}
1913 pub mod RW {}
1914 }
1915 #[doc = "Edge Counter A"]
1916 pub mod EDGCNTA {
1917 pub const offset: u16 = 8;
1918 pub const mask: u16 = 0xff << offset;
1919 pub mod R {}
1920 pub mod W {}
1921 pub mod RW {}
1922 }
1923 }
1924 #[doc = "Capture Control B Register"]
1925 pub mod SMCAPTCTRLB {
1926 #[doc = "Arm B"]
1927 pub mod ARMB {
1928 pub const offset: u16 = 0;
1929 pub const mask: u16 = 0x01 << offset;
1930 pub mod R {}
1931 pub mod W {}
1932 pub mod RW {
1933 #[doc = "Input capture operation is disabled."]
1934 pub const ARMB_0: u16 = 0;
1935 #[doc = "Input capture operation as specified by CAPTCTRLB\\[EDGBx\\] is enabled."]
1936 pub const ARMB_1: u16 = 0x01;
1937 }
1938 }
1939 #[doc = "One Shot Mode B"]
1940 pub mod ONESHOTB {
1941 pub const offset: u16 = 1;
1942 pub const mask: u16 = 0x01 << offset;
1943 pub mod R {}
1944 pub mod W {}
1945 pub mod RW {
1946 #[doc = "Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB\\[ARMB\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit."]
1947 pub const ONESHOTB_0: u16 = 0;
1948 #[doc = "One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB\\[ARMB\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB\\[ARMB\\] is cleared. No further captures will be performed until CAPTCTRLB\\[ARMB\\] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB\\[ARMB\\] is then cleared."]
1949 pub const ONESHOTB_1: u16 = 0x01;
1950 }
1951 }
1952 #[doc = "Edge B 0"]
1953 pub mod EDGB0 {
1954 pub const offset: u16 = 2;
1955 pub const mask: u16 = 0x03 << offset;
1956 pub mod R {}
1957 pub mod W {}
1958 pub mod RW {
1959 #[doc = "Disabled"]
1960 pub const EDGB0_0: u16 = 0;
1961 #[doc = "Capture falling edges"]
1962 pub const EDGB0_1: u16 = 0x01;
1963 #[doc = "Capture rising edges"]
1964 pub const EDGB0_2: u16 = 0x02;
1965 #[doc = "Capture any edge"]
1966 pub const EDGB0_3: u16 = 0x03;
1967 }
1968 }
1969 #[doc = "Edge B 1"]
1970 pub mod EDGB1 {
1971 pub const offset: u16 = 4;
1972 pub const mask: u16 = 0x03 << offset;
1973 pub mod R {}
1974 pub mod W {}
1975 pub mod RW {
1976 #[doc = "Disabled"]
1977 pub const EDGB1_0: u16 = 0;
1978 #[doc = "Capture falling edges"]
1979 pub const EDGB1_1: u16 = 0x01;
1980 #[doc = "Capture rising edges"]
1981 pub const EDGB1_2: u16 = 0x02;
1982 #[doc = "Capture any edge"]
1983 pub const EDGB1_3: u16 = 0x03;
1984 }
1985 }
1986 #[doc = "Input Select B"]
1987 pub mod INP_SELB {
1988 pub const offset: u16 = 6;
1989 pub const mask: u16 = 0x01 << offset;
1990 pub mod R {}
1991 pub mod W {}
1992 pub mod RW {
1993 #[doc = "Raw PWM_B input signal selected as source."]
1994 pub const INP_SELB_0: u16 = 0;
1995 #[doc = "Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB\\[EDGB0\\] and CAPTCTRLB\\[EDGB1\\] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB\\[EDGB0\\] and/or CAPTCTRLB\\[EDGB1\\] fields in order to enable one or both of the capture registers."]
1996 pub const INP_SELB_1: u16 = 0x01;
1997 }
1998 }
1999 #[doc = "Edge Counter B Enable"]
2000 pub mod EDGCNTB_EN {
2001 pub const offset: u16 = 7;
2002 pub const mask: u16 = 0x01 << offset;
2003 pub mod R {}
2004 pub mod W {}
2005 pub mod RW {
2006 #[doc = "Edge counter disabled and held in reset"]
2007 pub const EDGCNTB_EN_0: u16 = 0;
2008 #[doc = "Edge counter enabled"]
2009 pub const EDGCNTB_EN_1: u16 = 0x01;
2010 }
2011 }
2012 #[doc = "Capture B FIFOs Water Mark"]
2013 pub mod CFBWM {
2014 pub const offset: u16 = 8;
2015 pub const mask: u16 = 0x03 << offset;
2016 pub mod R {}
2017 pub mod W {}
2018 pub mod RW {}
2019 }
2020 #[doc = "Capture B0 FIFO Word Count"]
2021 pub mod CB0CNT {
2022 pub const offset: u16 = 10;
2023 pub const mask: u16 = 0x07 << offset;
2024 pub mod R {}
2025 pub mod W {}
2026 pub mod RW {}
2027 }
2028 #[doc = "Capture B1 FIFO Word Count"]
2029 pub mod CB1CNT {
2030 pub const offset: u16 = 13;
2031 pub const mask: u16 = 0x07 << offset;
2032 pub mod R {}
2033 pub mod W {}
2034 pub mod RW {}
2035 }
2036 }
2037 #[doc = "Capture Compare B Register"]
2038 pub mod SMCAPTCOMPB {
2039 #[doc = "Edge Compare B"]
2040 pub mod EDGCMPB {
2041 pub const offset: u16 = 0;
2042 pub const mask: u16 = 0xff << offset;
2043 pub mod R {}
2044 pub mod W {}
2045 pub mod RW {}
2046 }
2047 #[doc = "Edge Counter B"]
2048 pub mod EDGCNTB {
2049 pub const offset: u16 = 8;
2050 pub const mask: u16 = 0xff << offset;
2051 pub mod R {}
2052 pub mod W {}
2053 pub mod RW {}
2054 }
2055 }
2056 #[doc = "Capture Control X Register"]
2057 pub mod SMCAPTCTRLX {
2058 #[doc = "Arm X"]
2059 pub mod ARMX {
2060 pub const offset: u16 = 0;
2061 pub const mask: u16 = 0x01 << offset;
2062 pub mod R {}
2063 pub mod W {}
2064 pub mod RW {
2065 #[doc = "Input capture operation is disabled."]
2066 pub const ARMX_0: u16 = 0;
2067 #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."]
2068 pub const ARMX_1: u16 = 0x01;
2069 }
2070 }
2071 #[doc = "One Shot Mode Aux"]
2072 pub mod ONESHOTX {
2073 pub const offset: u16 = 1;
2074 pub const mask: u16 = 0x01 << offset;
2075 pub mod R {}
2076 pub mod W {}
2077 pub mod RW {
2078 #[doc = "Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit."]
2079 pub const ONESHOTX_0: u16 = 0;
2080 #[doc = "One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared."]
2081 pub const ONESHOTX_1: u16 = 0x01;
2082 }
2083 }
2084 #[doc = "Edge X 0"]
2085 pub mod EDGX0 {
2086 pub const offset: u16 = 2;
2087 pub const mask: u16 = 0x03 << offset;
2088 pub mod R {}
2089 pub mod W {}
2090 pub mod RW {
2091 #[doc = "Disabled"]
2092 pub const EDGX0_0: u16 = 0;
2093 #[doc = "Capture falling edges"]
2094 pub const EDGX0_1: u16 = 0x01;
2095 #[doc = "Capture rising edges"]
2096 pub const EDGX0_2: u16 = 0x02;
2097 #[doc = "Capture any edge"]
2098 pub const EDGX0_3: u16 = 0x03;
2099 }
2100 }
2101 #[doc = "Edge X 1"]
2102 pub mod EDGX1 {
2103 pub const offset: u16 = 4;
2104 pub const mask: u16 = 0x03 << offset;
2105 pub mod R {}
2106 pub mod W {}
2107 pub mod RW {
2108 #[doc = "Disabled"]
2109 pub const EDGX1_0: u16 = 0;
2110 #[doc = "Capture falling edges"]
2111 pub const EDGX1_1: u16 = 0x01;
2112 #[doc = "Capture rising edges"]
2113 pub const EDGX1_2: u16 = 0x02;
2114 #[doc = "Capture any edge"]
2115 pub const EDGX1_3: u16 = 0x03;
2116 }
2117 }
2118 #[doc = "Input Select X"]
2119 pub mod INP_SELX {
2120 pub const offset: u16 = 6;
2121 pub const mask: u16 = 0x01 << offset;
2122 pub mod R {}
2123 pub mod W {}
2124 pub mod RW {
2125 #[doc = "Raw PWM_X input signal selected as source."]
2126 pub const INP_SELX_0: u16 = 0;
2127 #[doc = "Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX\\[EDGX0\\] and CAPTCTRLX\\[EDGX1\\] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX\\[EDGX0\\] and/or CAPTCTRLX\\[EDGX1\\] fields in order to enable one or both of the capture registers."]
2128 pub const INP_SELX_1: u16 = 0x01;
2129 }
2130 }
2131 #[doc = "Edge Counter X Enable"]
2132 pub mod EDGCNTX_EN {
2133 pub const offset: u16 = 7;
2134 pub const mask: u16 = 0x01 << offset;
2135 pub mod R {}
2136 pub mod W {}
2137 pub mod RW {
2138 #[doc = "Edge counter disabled and held in reset"]
2139 pub const EDGCNTX_EN_0: u16 = 0;
2140 #[doc = "Edge counter enabled"]
2141 pub const EDGCNTX_EN_1: u16 = 0x01;
2142 }
2143 }
2144 #[doc = "Capture X FIFOs Water Mark"]
2145 pub mod CFXWM {
2146 pub const offset: u16 = 8;
2147 pub const mask: u16 = 0x03 << offset;
2148 pub mod R {}
2149 pub mod W {}
2150 pub mod RW {}
2151 }
2152 #[doc = "Capture X0 FIFO Word Count"]
2153 pub mod CX0CNT {
2154 pub const offset: u16 = 10;
2155 pub const mask: u16 = 0x07 << offset;
2156 pub mod R {}
2157 pub mod W {}
2158 pub mod RW {}
2159 }
2160 #[doc = "Capture X1 FIFO Word Count"]
2161 pub mod CX1CNT {
2162 pub const offset: u16 = 13;
2163 pub const mask: u16 = 0x07 << offset;
2164 pub mod R {}
2165 pub mod W {}
2166 pub mod RW {}
2167 }
2168 }
2169 #[doc = "Capture Compare X Register"]
2170 pub mod SMCAPTCOMPX {
2171 #[doc = "Edge Compare X"]
2172 pub mod EDGCMPX {
2173 pub const offset: u16 = 0;
2174 pub const mask: u16 = 0xff << offset;
2175 pub mod R {}
2176 pub mod W {}
2177 pub mod RW {}
2178 }
2179 #[doc = "Edge Counter X"]
2180 pub mod EDGCNTX {
2181 pub const offset: u16 = 8;
2182 pub const mask: u16 = 0xff << offset;
2183 pub mod R {}
2184 pub mod W {}
2185 pub mod RW {}
2186 }
2187 }
2188 #[doc = "Capture Value 0 Register"]
2189 pub mod SMCVAL0 {
2190 #[doc = "CAPTVAL0"]
2191 pub mod CAPTVAL0 {
2192 pub const offset: u16 = 0;
2193 pub const mask: u16 = 0xffff << offset;
2194 pub mod R {}
2195 pub mod W {}
2196 pub mod RW {}
2197 }
2198 }
2199 #[doc = "Capture Value 0 Cycle Register"]
2200 pub mod SMCVAL0CYC {
2201 #[doc = "CVAL0CYC"]
2202 pub mod CVAL0CYC {
2203 pub const offset: u16 = 0;
2204 pub const mask: u16 = 0x0f << offset;
2205 pub mod R {}
2206 pub mod W {}
2207 pub mod RW {}
2208 }
2209 }
2210 #[doc = "Capture Value 1 Register"]
2211 pub mod SMCVAL1 {
2212 #[doc = "CAPTVAL1"]
2213 pub mod CAPTVAL1 {
2214 pub const offset: u16 = 0;
2215 pub const mask: u16 = 0xffff << offset;
2216 pub mod R {}
2217 pub mod W {}
2218 pub mod RW {}
2219 }
2220 }
2221 #[doc = "Capture Value 1 Cycle Register"]
2222 pub mod SMCVAL1CYC {
2223 #[doc = "CVAL1CYC"]
2224 pub mod CVAL1CYC {
2225 pub const offset: u16 = 0;
2226 pub const mask: u16 = 0x0f << offset;
2227 pub mod R {}
2228 pub mod W {}
2229 pub mod RW {}
2230 }
2231 }
2232 #[doc = "Capture Value 2 Register"]
2233 pub mod SMCVAL2 {
2234 #[doc = "CAPTVAL2"]
2235 pub mod CAPTVAL2 {
2236 pub const offset: u16 = 0;
2237 pub const mask: u16 = 0xffff << offset;
2238 pub mod R {}
2239 pub mod W {}
2240 pub mod RW {}
2241 }
2242 }
2243 #[doc = "Capture Value 2 Cycle Register"]
2244 pub mod SMCVAL2CYC {
2245 #[doc = "CVAL2CYC"]
2246 pub mod CVAL2CYC {
2247 pub const offset: u16 = 0;
2248 pub const mask: u16 = 0x0f << offset;
2249 pub mod R {}
2250 pub mod W {}
2251 pub mod RW {}
2252 }
2253 }
2254 #[doc = "Capture Value 3 Register"]
2255 pub mod SMCVAL3 {
2256 #[doc = "CAPTVAL3"]
2257 pub mod CAPTVAL3 {
2258 pub const offset: u16 = 0;
2259 pub const mask: u16 = 0xffff << offset;
2260 pub mod R {}
2261 pub mod W {}
2262 pub mod RW {}
2263 }
2264 }
2265 #[doc = "Capture Value 3 Cycle Register"]
2266 pub mod SMCVAL3CYC {
2267 #[doc = "CVAL3CYC"]
2268 pub mod CVAL3CYC {
2269 pub const offset: u16 = 0;
2270 pub const mask: u16 = 0x0f << offset;
2271 pub mod R {}
2272 pub mod W {}
2273 pub mod RW {}
2274 }
2275 }
2276 #[doc = "Capture Value 4 Register"]
2277 pub mod SMCVAL4 {
2278 #[doc = "CAPTVAL4"]
2279 pub mod CAPTVAL4 {
2280 pub const offset: u16 = 0;
2281 pub const mask: u16 = 0xffff << offset;
2282 pub mod R {}
2283 pub mod W {}
2284 pub mod RW {}
2285 }
2286 }
2287 #[doc = "Capture Value 4 Cycle Register"]
2288 pub mod SMCVAL4CYC {
2289 #[doc = "CVAL4CYC"]
2290 pub mod CVAL4CYC {
2291 pub const offset: u16 = 0;
2292 pub const mask: u16 = 0x0f << offset;
2293 pub mod R {}
2294 pub mod W {}
2295 pub mod RW {}
2296 }
2297 }
2298 #[doc = "Capture Value 5 Register"]
2299 pub mod SMCVAL5 {
2300 #[doc = "CAPTVAL5"]
2301 pub mod CAPTVAL5 {
2302 pub const offset: u16 = 0;
2303 pub const mask: u16 = 0xffff << offset;
2304 pub mod R {}
2305 pub mod W {}
2306 pub mod RW {}
2307 }
2308 }
2309 #[doc = "Capture Value 5 Cycle Register"]
2310 pub mod SMCVAL5CYC {
2311 #[doc = "CVAL5CYC"]
2312 pub mod CVAL5CYC {
2313 pub const offset: u16 = 0;
2314 pub const mask: u16 = 0x0f << offset;
2315 pub mod R {}
2316 pub mod W {}
2317 pub mod RW {}
2318 }
2319 }
2320 #[doc = "Phase Delay Register"]
2321 pub mod SMPHASEDLY {
2322 #[doc = "Initial Count Register Bits"]
2323 pub mod PHASEDLY {
2324 pub const offset: u16 = 0;
2325 pub const mask: u16 = 0xffff << offset;
2326 pub mod R {}
2327 pub mod W {}
2328 pub mod RW {}
2329 }
2330 }
2331}