rp2040_pac/i2c0/
ic_enable_status.rs

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1#[doc = "Register `IC_ENABLE_STATUS` reader"]
2pub type R = crate::R<IC_ENABLE_STATUS_SPEC>;
3#[doc = "Field `IC_EN` reader - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).  
4
5 Reset value: 0x0"]
6pub type IC_EN_R = crate::BitReader<IC_EN_A>;
7#[doc = "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).  
8
9 Reset value: 0x0  
10
11Value on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum IC_EN_A {
14    #[doc = "0: I2C disabled"]
15    DISABLED = 0,
16    #[doc = "1: I2C enabled"]
17    ENABLED = 1,
18}
19impl From<IC_EN_A> for bool {
20    #[inline(always)]
21    fn from(variant: IC_EN_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl IC_EN_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> IC_EN_A {
29        match self.bits {
30            false => IC_EN_A::DISABLED,
31            true => IC_EN_A::ENABLED,
32        }
33    }
34    #[doc = "I2C disabled"]
35    #[inline(always)]
36    pub fn is_disabled(&self) -> bool {
37        *self == IC_EN_A::DISABLED
38    }
39    #[doc = "I2C enabled"]
40    #[inline(always)]
41    pub fn is_enabled(&self) -> bool {
42        *self == IC_EN_A::ENABLED
43    }
44}
45#[doc = "Field `SLV_DISABLED_WHILE_BUSY` reader - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:  
46
47 (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;  
48
49 OR,  
50
51 (b) address and data bytes of the Slave-Receiver operation from a remote master.  
52
53 When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.  
54
55 Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\]
56has been set to 0, then this bit will also be set to 1.  
57
58 When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.  
59
60 Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.  
61
62 Reset value: 0x0"]
63pub type SLV_DISABLED_WHILE_BUSY_R = crate::BitReader<SLV_DISABLED_WHILE_BUSY_A>;
64#[doc = "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:  
65
66 (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;  
67
68 OR,  
69
70 (b) address and data bytes of the Slave-Receiver operation from a remote master.  
71
72 When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.  
73
74 Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\]
75has been set to 0, then this bit will also be set to 1.  
76
77 When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.  
78
79 Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.  
80
81 Reset value: 0x0  
82
83Value on reset: 0"]
84#[derive(Clone, Copy, Debug, PartialEq, Eq)]
85pub enum SLV_DISABLED_WHILE_BUSY_A {
86    #[doc = "0: Slave is disabled when it is idle"]
87    INACTIVE = 0,
88    #[doc = "1: Slave is disabled when it is active"]
89    ACTIVE = 1,
90}
91impl From<SLV_DISABLED_WHILE_BUSY_A> for bool {
92    #[inline(always)]
93    fn from(variant: SLV_DISABLED_WHILE_BUSY_A) -> Self {
94        variant as u8 != 0
95    }
96}
97impl SLV_DISABLED_WHILE_BUSY_R {
98    #[doc = "Get enumerated values variant"]
99    #[inline(always)]
100    pub const fn variant(&self) -> SLV_DISABLED_WHILE_BUSY_A {
101        match self.bits {
102            false => SLV_DISABLED_WHILE_BUSY_A::INACTIVE,
103            true => SLV_DISABLED_WHILE_BUSY_A::ACTIVE,
104        }
105    }
106    #[doc = "Slave is disabled when it is idle"]
107    #[inline(always)]
108    pub fn is_inactive(&self) -> bool {
109        *self == SLV_DISABLED_WHILE_BUSY_A::INACTIVE
110    }
111    #[doc = "Slave is disabled when it is active"]
112    #[inline(always)]
113    pub fn is_active(&self) -> bool {
114        *self == SLV_DISABLED_WHILE_BUSY_A::ACTIVE
115    }
116}
117#[doc = "Field `SLV_RX_DATA_LOST` reader - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.  
118
119 Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\]
120has been set to 0, then this bit is also set to 1.  
121
122 When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.  
123
124 Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.  
125
126 Reset value: 0x0"]
127pub type SLV_RX_DATA_LOST_R = crate::BitReader<SLV_RX_DATA_LOST_A>;
128#[doc = "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.  
129
130 Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\]
131has been set to 0, then this bit is also set to 1.  
132
133 When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.  
134
135 Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.  
136
137 Reset value: 0x0  
138
139Value on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum SLV_RX_DATA_LOST_A {
142    #[doc = "0: Slave RX Data is not lost"]
143    INACTIVE = 0,
144    #[doc = "1: Slave RX Data is lost"]
145    ACTIVE = 1,
146}
147impl From<SLV_RX_DATA_LOST_A> for bool {
148    #[inline(always)]
149    fn from(variant: SLV_RX_DATA_LOST_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl SLV_RX_DATA_LOST_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub const fn variant(&self) -> SLV_RX_DATA_LOST_A {
157        match self.bits {
158            false => SLV_RX_DATA_LOST_A::INACTIVE,
159            true => SLV_RX_DATA_LOST_A::ACTIVE,
160        }
161    }
162    #[doc = "Slave RX Data is not lost"]
163    #[inline(always)]
164    pub fn is_inactive(&self) -> bool {
165        *self == SLV_RX_DATA_LOST_A::INACTIVE
166    }
167    #[doc = "Slave RX Data is lost"]
168    #[inline(always)]
169    pub fn is_active(&self) -> bool {
170        *self == SLV_RX_DATA_LOST_A::ACTIVE
171    }
172}
173impl R {
174    #[doc = "Bit 0 - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).  
175
176 Reset value: 0x0"]
177    #[inline(always)]
178    pub fn ic_en(&self) -> IC_EN_R {
179        IC_EN_R::new((self.bits & 1) != 0)
180    }
181    #[doc = "Bit 1 - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:  
182
183 (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;  
184
185 OR,  
186
187 (b) address and data bytes of the Slave-Receiver operation from a remote master.  
188
189 When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.  
190
191 Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\]
192has been set to 0, then this bit will also be set to 1.  
193
194 When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.  
195
196 Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.  
197
198 Reset value: 0x0"]
199    #[inline(always)]
200    pub fn slv_disabled_while_busy(&self) -> SLV_DISABLED_WHILE_BUSY_R {
201        SLV_DISABLED_WHILE_BUSY_R::new(((self.bits >> 1) & 1) != 0)
202    }
203    #[doc = "Bit 2 - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.  
204
205 Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\]
206has been set to 0, then this bit is also set to 1.  
207
208 When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.  
209
210 Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.  
211
212 Reset value: 0x0"]
213    #[inline(always)]
214    pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R {
215        SLV_RX_DATA_LOST_R::new(((self.bits >> 2) & 1) != 0)
216    }
217}
218#[doc = "I2C Enable Status Register  
219
220 The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\]
221register is set from 1 to 0; that is, when DW_apb_i2c is disabled.  
222
223 If IC_ENABLE\\[0\\]
224has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.  
225
226 If IC_ENABLE\\[0\\]
227has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.  
228
229 Note: When IC_ENABLE\\[0\\]
230has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.  
231
232You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
233pub struct IC_ENABLE_STATUS_SPEC;
234impl crate::RegisterSpec for IC_ENABLE_STATUS_SPEC {
235    type Ux = u32;
236}
237#[doc = "`read()` method returns [`ic_enable_status::R`](R) reader structure"]
238impl crate::Readable for IC_ENABLE_STATUS_SPEC {}
239#[doc = "`reset()` method sets IC_ENABLE_STATUS to value 0"]
240impl crate::Resettable for IC_ENABLE_STATUS_SPEC {
241    const RESET_VALUE: u32 = 0;
242}
rp2040_pac/i2c0/ic_enable_status.rs

rp2040_pac/i2c0/
ic_enable_status.rs
