imxrt_ral/blocks/imxrt1011/
ccm_analog.rs

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1#[doc = "CCM_ANALOG"]
2#[repr(C)]
3pub struct RegisterBlock {
4    _reserved0: [u8; 0x10],
5    #[doc = "Analog USB1 480MHz PLL Control Register"]
6    pub PLL_USB1: crate::RWRegister<u32>,
7    #[doc = "Analog USB1 480MHz PLL Control Register"]
8    pub PLL_USB1_SET: crate::RWRegister<u32>,
9    #[doc = "Analog USB1 480MHz PLL Control Register"]
10    pub PLL_USB1_CLR: crate::RWRegister<u32>,
11    #[doc = "Analog USB1 480MHz PLL Control Register"]
12    pub PLL_USB1_TOG: crate::RWRegister<u32>,
13    _reserved1: [u8; 0x10],
14    #[doc = "Analog System PLL Control Register"]
15    pub PLL_SYS: crate::RWRegister<u32>,
16    #[doc = "Analog System PLL Control Register"]
17    pub PLL_SYS_SET: crate::RWRegister<u32>,
18    #[doc = "Analog System PLL Control Register"]
19    pub PLL_SYS_CLR: crate::RWRegister<u32>,
20    #[doc = "Analog System PLL Control Register"]
21    pub PLL_SYS_TOG: crate::RWRegister<u32>,
22    #[doc = "528MHz System PLL Spread Spectrum Register"]
23    pub PLL_SYS_SS: crate::RWRegister<u32>,
24    _reserved2: [u8; 0x0c],
25    #[doc = "Numerator of 528MHz System PLL Fractional Loop Divider Register"]
26    pub PLL_SYS_NUM: crate::RWRegister<u32>,
27    _reserved3: [u8; 0x0c],
28    #[doc = "Denominator of 528MHz System PLL Fractional Loop Divider Register"]
29    pub PLL_SYS_DENOM: crate::RWRegister<u32>,
30    _reserved4: [u8; 0x0c],
31    #[doc = "Analog Audio PLL control Register"]
32    pub PLL_AUDIO: crate::RWRegister<u32>,
33    #[doc = "Analog Audio PLL control Register"]
34    pub PLL_AUDIO_SET: crate::RWRegister<u32>,
35    #[doc = "Analog Audio PLL control Register"]
36    pub PLL_AUDIO_CLR: crate::RWRegister<u32>,
37    #[doc = "Analog Audio PLL control Register"]
38    pub PLL_AUDIO_TOG: crate::RWRegister<u32>,
39    #[doc = "Numerator of Audio PLL Fractional Loop Divider Register"]
40    pub PLL_AUDIO_NUM: crate::RWRegister<u32>,
41    _reserved5: [u8; 0x0c],
42    #[doc = "Denominator of Audio PLL Fractional Loop Divider Register"]
43    pub PLL_AUDIO_DENOM: crate::RWRegister<u32>,
44    _reserved6: [u8; 0x4c],
45    #[doc = "Analog ENET PLL Control Register"]
46    pub PLL_ENET: crate::RWRegister<u32>,
47    #[doc = "Analog ENET PLL Control Register"]
48    pub PLL_ENET_SET: crate::RWRegister<u32>,
49    #[doc = "Analog ENET PLL Control Register"]
50    pub PLL_ENET_CLR: crate::RWRegister<u32>,
51    #[doc = "Analog ENET PLL Control Register"]
52    pub PLL_ENET_TOG: crate::RWRegister<u32>,
53    #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
54    pub PFD_480: crate::RWRegister<u32>,
55    #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
56    pub PFD_480_SET: crate::RWRegister<u32>,
57    #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
58    pub PFD_480_CLR: crate::RWRegister<u32>,
59    #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
60    pub PFD_480_TOG: crate::RWRegister<u32>,
61    #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
62    pub PFD_528: crate::RWRegister<u32>,
63    #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
64    pub PFD_528_SET: crate::RWRegister<u32>,
65    #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
66    pub PFD_528_CLR: crate::RWRegister<u32>,
67    #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
68    pub PFD_528_TOG: crate::RWRegister<u32>,
69    _reserved7: [u8; 0x40],
70    #[doc = "Miscellaneous Register 0"]
71    pub MISC0: crate::RWRegister<u32>,
72    #[doc = "Miscellaneous Register 0"]
73    pub MISC0_SET: crate::RWRegister<u32>,
74    #[doc = "Miscellaneous Register 0"]
75    pub MISC0_CLR: crate::RWRegister<u32>,
76    #[doc = "Miscellaneous Register 0"]
77    pub MISC0_TOG: crate::RWRegister<u32>,
78    #[doc = "Miscellaneous Register 1"]
79    pub MISC1: crate::RWRegister<u32>,
80    #[doc = "Miscellaneous Register 1"]
81    pub MISC1_SET: crate::RWRegister<u32>,
82    #[doc = "Miscellaneous Register 1"]
83    pub MISC1_CLR: crate::RWRegister<u32>,
84    #[doc = "Miscellaneous Register 1"]
85    pub MISC1_TOG: crate::RWRegister<u32>,
86    #[doc = "Miscellaneous Register 2"]
87    pub MISC2: crate::RWRegister<u32>,
88    #[doc = "Miscellaneous Register 2"]
89    pub MISC2_SET: crate::RWRegister<u32>,
90    #[doc = "Miscellaneous Register 2"]
91    pub MISC2_CLR: crate::RWRegister<u32>,
92    #[doc = "Miscellaneous Register 2"]
93    pub MISC2_TOG: crate::RWRegister<u32>,
94}
95#[doc = "Analog USB1 480MHz PLL Control Register"]
96pub mod PLL_USB1 {
97    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
98    pub mod DIV_SELECT {
99        pub const offset: u32 = 1;
100        pub const mask: u32 = 0x01 << offset;
101        pub mod R {}
102        pub mod W {}
103        pub mod RW {}
104    }
105    #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
106    pub mod EN_USB_CLKS {
107        pub const offset: u32 = 6;
108        pub const mask: u32 = 0x01 << offset;
109        pub mod R {}
110        pub mod W {}
111        pub mod RW {
112            #[doc = "PLL outputs for USBPHYn off."]
113            pub const EN_USB_CLKS_0: u32 = 0;
114            #[doc = "PLL outputs for USBPHYn on."]
115            pub const EN_USB_CLKS_1: u32 = 0x01;
116        }
117    }
118    #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
119    pub mod POWER {
120        pub const offset: u32 = 12;
121        pub const mask: u32 = 0x01 << offset;
122        pub mod R {}
123        pub mod W {}
124        pub mod RW {}
125    }
126    #[doc = "Enable the PLL clock output."]
127    pub mod ENABLE {
128        pub const offset: u32 = 13;
129        pub const mask: u32 = 0x01 << offset;
130        pub mod R {}
131        pub mod W {}
132        pub mod RW {}
133    }
134    #[doc = "Determines the bypass source."]
135    pub mod BYPASS_CLK_SRC {
136        pub const offset: u32 = 14;
137        pub const mask: u32 = 0x03 << offset;
138        pub mod R {}
139        pub mod W {}
140        pub mod RW {
141            #[doc = "Select the 24MHz oscillator as source."]
142            pub const REF_CLK_24M: u32 = 0;
143        }
144    }
145    #[doc = "Bypass the PLL."]
146    pub mod BYPASS {
147        pub const offset: u32 = 16;
148        pub const mask: u32 = 0x01 << offset;
149        pub mod R {}
150        pub mod W {}
151        pub mod RW {}
152    }
153    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
154    pub mod LOCK {
155        pub const offset: u32 = 31;
156        pub const mask: u32 = 0x01 << offset;
157        pub mod R {}
158        pub mod W {}
159        pub mod RW {}
160    }
161}
162#[doc = "Analog USB1 480MHz PLL Control Register"]
163pub mod PLL_USB1_SET {
164    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
165    pub mod DIV_SELECT {
166        pub const offset: u32 = 1;
167        pub const mask: u32 = 0x01 << offset;
168        pub mod R {}
169        pub mod W {}
170        pub mod RW {}
171    }
172    #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
173    pub mod EN_USB_CLKS {
174        pub const offset: u32 = 6;
175        pub const mask: u32 = 0x01 << offset;
176        pub mod R {}
177        pub mod W {}
178        pub mod RW {
179            #[doc = "PLL outputs for USBPHYn off."]
180            pub const EN_USB_CLKS_0: u32 = 0;
181            #[doc = "PLL outputs for USBPHYn on."]
182            pub const EN_USB_CLKS_1: u32 = 0x01;
183        }
184    }
185    #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
186    pub mod POWER {
187        pub const offset: u32 = 12;
188        pub const mask: u32 = 0x01 << offset;
189        pub mod R {}
190        pub mod W {}
191        pub mod RW {}
192    }
193    #[doc = "Enable the PLL clock output."]
194    pub mod ENABLE {
195        pub const offset: u32 = 13;
196        pub const mask: u32 = 0x01 << offset;
197        pub mod R {}
198        pub mod W {}
199        pub mod RW {}
200    }
201    #[doc = "Determines the bypass source."]
202    pub mod BYPASS_CLK_SRC {
203        pub const offset: u32 = 14;
204        pub const mask: u32 = 0x03 << offset;
205        pub mod R {}
206        pub mod W {}
207        pub mod RW {
208            #[doc = "Select the 24MHz oscillator as source."]
209            pub const REF_CLK_24M: u32 = 0;
210        }
211    }
212    #[doc = "Bypass the PLL."]
213    pub mod BYPASS {
214        pub const offset: u32 = 16;
215        pub const mask: u32 = 0x01 << offset;
216        pub mod R {}
217        pub mod W {}
218        pub mod RW {}
219    }
220    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
221    pub mod LOCK {
222        pub const offset: u32 = 31;
223        pub const mask: u32 = 0x01 << offset;
224        pub mod R {}
225        pub mod W {}
226        pub mod RW {}
227    }
228}
229#[doc = "Analog USB1 480MHz PLL Control Register"]
230pub mod PLL_USB1_CLR {
231    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
232    pub mod DIV_SELECT {
233        pub const offset: u32 = 1;
234        pub const mask: u32 = 0x01 << offset;
235        pub mod R {}
236        pub mod W {}
237        pub mod RW {}
238    }
239    #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
240    pub mod EN_USB_CLKS {
241        pub const offset: u32 = 6;
242        pub const mask: u32 = 0x01 << offset;
243        pub mod R {}
244        pub mod W {}
245        pub mod RW {
246            #[doc = "PLL outputs for USBPHYn off."]
247            pub const EN_USB_CLKS_0: u32 = 0;
248            #[doc = "PLL outputs for USBPHYn on."]
249            pub const EN_USB_CLKS_1: u32 = 0x01;
250        }
251    }
252    #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
253    pub mod POWER {
254        pub const offset: u32 = 12;
255        pub const mask: u32 = 0x01 << offset;
256        pub mod R {}
257        pub mod W {}
258        pub mod RW {}
259    }
260    #[doc = "Enable the PLL clock output."]
261    pub mod ENABLE {
262        pub const offset: u32 = 13;
263        pub const mask: u32 = 0x01 << offset;
264        pub mod R {}
265        pub mod W {}
266        pub mod RW {}
267    }
268    #[doc = "Determines the bypass source."]
269    pub mod BYPASS_CLK_SRC {
270        pub const offset: u32 = 14;
271        pub const mask: u32 = 0x03 << offset;
272        pub mod R {}
273        pub mod W {}
274        pub mod RW {
275            #[doc = "Select the 24MHz oscillator as source."]
276            pub const REF_CLK_24M: u32 = 0;
277        }
278    }
279    #[doc = "Bypass the PLL."]
280    pub mod BYPASS {
281        pub const offset: u32 = 16;
282        pub const mask: u32 = 0x01 << offset;
283        pub mod R {}
284        pub mod W {}
285        pub mod RW {}
286    }
287    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
288    pub mod LOCK {
289        pub const offset: u32 = 31;
290        pub const mask: u32 = 0x01 << offset;
291        pub mod R {}
292        pub mod W {}
293        pub mod RW {}
294    }
295}
296#[doc = "Analog USB1 480MHz PLL Control Register"]
297pub mod PLL_USB1_TOG {
298    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
299    pub mod DIV_SELECT {
300        pub const offset: u32 = 1;
301        pub const mask: u32 = 0x01 << offset;
302        pub mod R {}
303        pub mod W {}
304        pub mod RW {}
305    }
306    #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
307    pub mod EN_USB_CLKS {
308        pub const offset: u32 = 6;
309        pub const mask: u32 = 0x01 << offset;
310        pub mod R {}
311        pub mod W {}
312        pub mod RW {
313            #[doc = "PLL outputs for USBPHYn off."]
314            pub const EN_USB_CLKS_0: u32 = 0;
315            #[doc = "PLL outputs for USBPHYn on."]
316            pub const EN_USB_CLKS_1: u32 = 0x01;
317        }
318    }
319    #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
320    pub mod POWER {
321        pub const offset: u32 = 12;
322        pub const mask: u32 = 0x01 << offset;
323        pub mod R {}
324        pub mod W {}
325        pub mod RW {}
326    }
327    #[doc = "Enable the PLL clock output."]
328    pub mod ENABLE {
329        pub const offset: u32 = 13;
330        pub const mask: u32 = 0x01 << offset;
331        pub mod R {}
332        pub mod W {}
333        pub mod RW {}
334    }
335    #[doc = "Determines the bypass source."]
336    pub mod BYPASS_CLK_SRC {
337        pub const offset: u32 = 14;
338        pub const mask: u32 = 0x03 << offset;
339        pub mod R {}
340        pub mod W {}
341        pub mod RW {
342            #[doc = "Select the 24MHz oscillator as source."]
343            pub const REF_CLK_24M: u32 = 0;
344        }
345    }
346    #[doc = "Bypass the PLL."]
347    pub mod BYPASS {
348        pub const offset: u32 = 16;
349        pub const mask: u32 = 0x01 << offset;
350        pub mod R {}
351        pub mod W {}
352        pub mod RW {}
353    }
354    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
355    pub mod LOCK {
356        pub const offset: u32 = 31;
357        pub const mask: u32 = 0x01 << offset;
358        pub mod R {}
359        pub mod W {}
360        pub mod RW {}
361    }
362}
363#[doc = "Analog System PLL Control Register"]
364pub mod PLL_SYS {
365    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
366    pub mod DIV_SELECT {
367        pub const offset: u32 = 0;
368        pub const mask: u32 = 0x01 << offset;
369        pub mod R {}
370        pub mod W {}
371        pub mod RW {}
372    }
373    #[doc = "Powers down the PLL."]
374    pub mod POWERDOWN {
375        pub const offset: u32 = 12;
376        pub const mask: u32 = 0x01 << offset;
377        pub mod R {}
378        pub mod W {}
379        pub mod RW {}
380    }
381    #[doc = "Enable PLL output"]
382    pub mod ENABLE {
383        pub const offset: u32 = 13;
384        pub const mask: u32 = 0x01 << offset;
385        pub mod R {}
386        pub mod W {}
387        pub mod RW {}
388    }
389    #[doc = "Determines the bypass source."]
390    pub mod BYPASS_CLK_SRC {
391        pub const offset: u32 = 14;
392        pub const mask: u32 = 0x03 << offset;
393        pub mod R {}
394        pub mod W {}
395        pub mod RW {
396            #[doc = "Select the 24MHz oscillator as source."]
397            pub const REF_CLK_24M: u32 = 0;
398        }
399    }
400    #[doc = "Bypass the PLL."]
401    pub mod BYPASS {
402        pub const offset: u32 = 16;
403        pub const mask: u32 = 0x01 << offset;
404        pub mod R {}
405        pub mod W {}
406        pub mod RW {}
407    }
408    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
409    pub mod LOCK {
410        pub const offset: u32 = 31;
411        pub const mask: u32 = 0x01 << offset;
412        pub mod R {}
413        pub mod W {}
414        pub mod RW {}
415    }
416}
417#[doc = "Analog System PLL Control Register"]
418pub mod PLL_SYS_SET {
419    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
420    pub mod DIV_SELECT {
421        pub const offset: u32 = 0;
422        pub const mask: u32 = 0x01 << offset;
423        pub mod R {}
424        pub mod W {}
425        pub mod RW {}
426    }
427    #[doc = "Powers down the PLL."]
428    pub mod POWERDOWN {
429        pub const offset: u32 = 12;
430        pub const mask: u32 = 0x01 << offset;
431        pub mod R {}
432        pub mod W {}
433        pub mod RW {}
434    }
435    #[doc = "Enable PLL output"]
436    pub mod ENABLE {
437        pub const offset: u32 = 13;
438        pub const mask: u32 = 0x01 << offset;
439        pub mod R {}
440        pub mod W {}
441        pub mod RW {}
442    }
443    #[doc = "Determines the bypass source."]
444    pub mod BYPASS_CLK_SRC {
445        pub const offset: u32 = 14;
446        pub const mask: u32 = 0x03 << offset;
447        pub mod R {}
448        pub mod W {}
449        pub mod RW {
450            #[doc = "Select the 24MHz oscillator as source."]
451            pub const REF_CLK_24M: u32 = 0;
452        }
453    }
454    #[doc = "Bypass the PLL."]
455    pub mod BYPASS {
456        pub const offset: u32 = 16;
457        pub const mask: u32 = 0x01 << offset;
458        pub mod R {}
459        pub mod W {}
460        pub mod RW {}
461    }
462    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
463    pub mod LOCK {
464        pub const offset: u32 = 31;
465        pub const mask: u32 = 0x01 << offset;
466        pub mod R {}
467        pub mod W {}
468        pub mod RW {}
469    }
470}
471#[doc = "Analog System PLL Control Register"]
472pub mod PLL_SYS_CLR {
473    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
474    pub mod DIV_SELECT {
475        pub const offset: u32 = 0;
476        pub const mask: u32 = 0x01 << offset;
477        pub mod R {}
478        pub mod W {}
479        pub mod RW {}
480    }
481    #[doc = "Powers down the PLL."]
482    pub mod POWERDOWN {
483        pub const offset: u32 = 12;
484        pub const mask: u32 = 0x01 << offset;
485        pub mod R {}
486        pub mod W {}
487        pub mod RW {}
488    }
489    #[doc = "Enable PLL output"]
490    pub mod ENABLE {
491        pub const offset: u32 = 13;
492        pub const mask: u32 = 0x01 << offset;
493        pub mod R {}
494        pub mod W {}
495        pub mod RW {}
496    }
497    #[doc = "Determines the bypass source."]
498    pub mod BYPASS_CLK_SRC {
499        pub const offset: u32 = 14;
500        pub const mask: u32 = 0x03 << offset;
501        pub mod R {}
502        pub mod W {}
503        pub mod RW {
504            #[doc = "Select the 24MHz oscillator as source."]
505            pub const REF_CLK_24M: u32 = 0;
506        }
507    }
508    #[doc = "Bypass the PLL."]
509    pub mod BYPASS {
510        pub const offset: u32 = 16;
511        pub const mask: u32 = 0x01 << offset;
512        pub mod R {}
513        pub mod W {}
514        pub mod RW {}
515    }
516    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
517    pub mod LOCK {
518        pub const offset: u32 = 31;
519        pub const mask: u32 = 0x01 << offset;
520        pub mod R {}
521        pub mod W {}
522        pub mod RW {}
523    }
524}
525#[doc = "Analog System PLL Control Register"]
526pub mod PLL_SYS_TOG {
527    #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
528    pub mod DIV_SELECT {
529        pub const offset: u32 = 0;
530        pub const mask: u32 = 0x01 << offset;
531        pub mod R {}
532        pub mod W {}
533        pub mod RW {}
534    }
535    #[doc = "Powers down the PLL."]
536    pub mod POWERDOWN {
537        pub const offset: u32 = 12;
538        pub const mask: u32 = 0x01 << offset;
539        pub mod R {}
540        pub mod W {}
541        pub mod RW {}
542    }
543    #[doc = "Enable PLL output"]
544    pub mod ENABLE {
545        pub const offset: u32 = 13;
546        pub const mask: u32 = 0x01 << offset;
547        pub mod R {}
548        pub mod W {}
549        pub mod RW {}
550    }
551    #[doc = "Determines the bypass source."]
552    pub mod BYPASS_CLK_SRC {
553        pub const offset: u32 = 14;
554        pub const mask: u32 = 0x03 << offset;
555        pub mod R {}
556        pub mod W {}
557        pub mod RW {
558            #[doc = "Select the 24MHz oscillator as source."]
559            pub const REF_CLK_24M: u32 = 0;
560        }
561    }
562    #[doc = "Bypass the PLL."]
563    pub mod BYPASS {
564        pub const offset: u32 = 16;
565        pub const mask: u32 = 0x01 << offset;
566        pub mod R {}
567        pub mod W {}
568        pub mod RW {}
569    }
570    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
571    pub mod LOCK {
572        pub const offset: u32 = 31;
573        pub const mask: u32 = 0x01 << offset;
574        pub mod R {}
575        pub mod W {}
576        pub mod RW {}
577    }
578}
579#[doc = "528MHz System PLL Spread Spectrum Register"]
580pub mod PLL_SYS_SS {
581    #[doc = "Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM\\[B\\]*24MHz."]
582    pub mod STEP {
583        pub const offset: u32 = 0;
584        pub const mask: u32 = 0x7fff << offset;
585        pub mod R {}
586        pub mod W {}
587        pub mod RW {}
588    }
589    #[doc = "Enable bit"]
590    pub mod ENABLE {
591        pub const offset: u32 = 15;
592        pub const mask: u32 = 0x01 << offset;
593        pub mod R {}
594        pub mod W {}
595        pub mod RW {
596            #[doc = "Spread spectrum modulation disabled"]
597            pub const ENABLE_0: u32 = 0;
598            #[doc = "Soread spectrum modulation enabled"]
599            pub const ENABLE_1: u32 = 0x01;
600        }
601    }
602    #[doc = "Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM\\[B\\]*24MHz."]
603    pub mod STOP {
604        pub const offset: u32 = 16;
605        pub const mask: u32 = 0xffff << offset;
606        pub mod R {}
607        pub mod W {}
608        pub mod RW {}
609    }
610}
611#[doc = "Numerator of 528MHz System PLL Fractional Loop Divider Register"]
612pub mod PLL_SYS_NUM {
613    #[doc = "30 bit numerator (A) of fractional loop divider (signed integer)."]
614    pub mod A {
615        pub const offset: u32 = 0;
616        pub const mask: u32 = 0x3fff_ffff << offset;
617        pub mod R {}
618        pub mod W {}
619        pub mod RW {}
620    }
621}
622#[doc = "Denominator of 528MHz System PLL Fractional Loop Divider Register"]
623pub mod PLL_SYS_DENOM {
624    #[doc = "30 bit denominator (B) of fractional loop divider (unsigned integer)."]
625    pub mod B {
626        pub const offset: u32 = 0;
627        pub const mask: u32 = 0x3fff_ffff << offset;
628        pub mod R {}
629        pub mod W {}
630        pub mod RW {}
631    }
632}
633#[doc = "Analog Audio PLL control Register"]
634pub mod PLL_AUDIO {
635    #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
636    pub mod DIV_SELECT {
637        pub const offset: u32 = 0;
638        pub const mask: u32 = 0x7f << offset;
639        pub mod R {}
640        pub mod W {}
641        pub mod RW {}
642    }
643    #[doc = "Powers down the PLL."]
644    pub mod POWERDOWN {
645        pub const offset: u32 = 12;
646        pub const mask: u32 = 0x01 << offset;
647        pub mod R {}
648        pub mod W {}
649        pub mod RW {}
650    }
651    #[doc = "Enable PLL output"]
652    pub mod ENABLE {
653        pub const offset: u32 = 13;
654        pub const mask: u32 = 0x01 << offset;
655        pub mod R {}
656        pub mod W {}
657        pub mod RW {}
658    }
659    #[doc = "Determines the bypass source."]
660    pub mod BYPASS_CLK_SRC {
661        pub const offset: u32 = 14;
662        pub const mask: u32 = 0x03 << offset;
663        pub mod R {}
664        pub mod W {}
665        pub mod RW {
666            #[doc = "Select the 24MHz oscillator as source."]
667            pub const REF_CLK_24M: u32 = 0;
668        }
669    }
670    #[doc = "Bypass the PLL."]
671    pub mod BYPASS {
672        pub const offset: u32 = 16;
673        pub const mask: u32 = 0x01 << offset;
674        pub mod R {}
675        pub mod W {}
676        pub mod RW {}
677    }
678    #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
679    pub mod POST_DIV_SELECT {
680        pub const offset: u32 = 19;
681        pub const mask: u32 = 0x03 << offset;
682        pub mod R {}
683        pub mod W {}
684        pub mod RW {
685            #[doc = "Divide by 4."]
686            pub const POST_DIV_SELECT_0: u32 = 0;
687            #[doc = "Divide by 2."]
688            pub const POST_DIV_SELECT_1: u32 = 0x01;
689            #[doc = "Divide by 1."]
690            pub const POST_DIV_SELECT_2: u32 = 0x02;
691        }
692    }
693    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
694    pub mod LOCK {
695        pub const offset: u32 = 31;
696        pub const mask: u32 = 0x01 << offset;
697        pub mod R {}
698        pub mod W {}
699        pub mod RW {}
700    }
701}
702#[doc = "Analog Audio PLL control Register"]
703pub mod PLL_AUDIO_SET {
704    #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
705    pub mod DIV_SELECT {
706        pub const offset: u32 = 0;
707        pub const mask: u32 = 0x7f << offset;
708        pub mod R {}
709        pub mod W {}
710        pub mod RW {}
711    }
712    #[doc = "Powers down the PLL."]
713    pub mod POWERDOWN {
714        pub const offset: u32 = 12;
715        pub const mask: u32 = 0x01 << offset;
716        pub mod R {}
717        pub mod W {}
718        pub mod RW {}
719    }
720    #[doc = "Enable PLL output"]
721    pub mod ENABLE {
722        pub const offset: u32 = 13;
723        pub const mask: u32 = 0x01 << offset;
724        pub mod R {}
725        pub mod W {}
726        pub mod RW {}
727    }
728    #[doc = "Determines the bypass source."]
729    pub mod BYPASS_CLK_SRC {
730        pub const offset: u32 = 14;
731        pub const mask: u32 = 0x03 << offset;
732        pub mod R {}
733        pub mod W {}
734        pub mod RW {
735            #[doc = "Select the 24MHz oscillator as source."]
736            pub const REF_CLK_24M: u32 = 0;
737        }
738    }
739    #[doc = "Bypass the PLL."]
740    pub mod BYPASS {
741        pub const offset: u32 = 16;
742        pub const mask: u32 = 0x01 << offset;
743        pub mod R {}
744        pub mod W {}
745        pub mod RW {}
746    }
747    #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
748    pub mod POST_DIV_SELECT {
749        pub const offset: u32 = 19;
750        pub const mask: u32 = 0x03 << offset;
751        pub mod R {}
752        pub mod W {}
753        pub mod RW {
754            #[doc = "Divide by 4."]
755            pub const POST_DIV_SELECT_0: u32 = 0;
756            #[doc = "Divide by 2."]
757            pub const POST_DIV_SELECT_1: u32 = 0x01;
758            #[doc = "Divide by 1."]
759            pub const POST_DIV_SELECT_2: u32 = 0x02;
760        }
761    }
762    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
763    pub mod LOCK {
764        pub const offset: u32 = 31;
765        pub const mask: u32 = 0x01 << offset;
766        pub mod R {}
767        pub mod W {}
768        pub mod RW {}
769    }
770}
771#[doc = "Analog Audio PLL control Register"]
772pub mod PLL_AUDIO_CLR {
773    #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
774    pub mod DIV_SELECT {
775        pub const offset: u32 = 0;
776        pub const mask: u32 = 0x7f << offset;
777        pub mod R {}
778        pub mod W {}
779        pub mod RW {}
780    }
781    #[doc = "Powers down the PLL."]
782    pub mod POWERDOWN {
783        pub const offset: u32 = 12;
784        pub const mask: u32 = 0x01 << offset;
785        pub mod R {}
786        pub mod W {}
787        pub mod RW {}
788    }
789    #[doc = "Enable PLL output"]
790    pub mod ENABLE {
791        pub const offset: u32 = 13;
792        pub const mask: u32 = 0x01 << offset;
793        pub mod R {}
794        pub mod W {}
795        pub mod RW {}
796    }
797    #[doc = "Determines the bypass source."]
798    pub mod BYPASS_CLK_SRC {
799        pub const offset: u32 = 14;
800        pub const mask: u32 = 0x03 << offset;
801        pub mod R {}
802        pub mod W {}
803        pub mod RW {
804            #[doc = "Select the 24MHz oscillator as source."]
805            pub const REF_CLK_24M: u32 = 0;
806        }
807    }
808    #[doc = "Bypass the PLL."]
809    pub mod BYPASS {
810        pub const offset: u32 = 16;
811        pub const mask: u32 = 0x01 << offset;
812        pub mod R {}
813        pub mod W {}
814        pub mod RW {}
815    }
816    #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
817    pub mod POST_DIV_SELECT {
818        pub const offset: u32 = 19;
819        pub const mask: u32 = 0x03 << offset;
820        pub mod R {}
821        pub mod W {}
822        pub mod RW {
823            #[doc = "Divide by 4."]
824            pub const POST_DIV_SELECT_0: u32 = 0;
825            #[doc = "Divide by 2."]
826            pub const POST_DIV_SELECT_1: u32 = 0x01;
827            #[doc = "Divide by 1."]
828            pub const POST_DIV_SELECT_2: u32 = 0x02;
829        }
830    }
831    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
832    pub mod LOCK {
833        pub const offset: u32 = 31;
834        pub const mask: u32 = 0x01 << offset;
835        pub mod R {}
836        pub mod W {}
837        pub mod RW {}
838    }
839}
840#[doc = "Analog Audio PLL control Register"]
841pub mod PLL_AUDIO_TOG {
842    #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
843    pub mod DIV_SELECT {
844        pub const offset: u32 = 0;
845        pub const mask: u32 = 0x7f << offset;
846        pub mod R {}
847        pub mod W {}
848        pub mod RW {}
849    }
850    #[doc = "Powers down the PLL."]
851    pub mod POWERDOWN {
852        pub const offset: u32 = 12;
853        pub const mask: u32 = 0x01 << offset;
854        pub mod R {}
855        pub mod W {}
856        pub mod RW {}
857    }
858    #[doc = "Enable PLL output"]
859    pub mod ENABLE {
860        pub const offset: u32 = 13;
861        pub const mask: u32 = 0x01 << offset;
862        pub mod R {}
863        pub mod W {}
864        pub mod RW {}
865    }
866    #[doc = "Determines the bypass source."]
867    pub mod BYPASS_CLK_SRC {
868        pub const offset: u32 = 14;
869        pub const mask: u32 = 0x03 << offset;
870        pub mod R {}
871        pub mod W {}
872        pub mod RW {
873            #[doc = "Select the 24MHz oscillator as source."]
874            pub const REF_CLK_24M: u32 = 0;
875        }
876    }
877    #[doc = "Bypass the PLL."]
878    pub mod BYPASS {
879        pub const offset: u32 = 16;
880        pub const mask: u32 = 0x01 << offset;
881        pub mod R {}
882        pub mod W {}
883        pub mod RW {}
884    }
885    #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
886    pub mod POST_DIV_SELECT {
887        pub const offset: u32 = 19;
888        pub const mask: u32 = 0x03 << offset;
889        pub mod R {}
890        pub mod W {}
891        pub mod RW {
892            #[doc = "Divide by 4."]
893            pub const POST_DIV_SELECT_0: u32 = 0;
894            #[doc = "Divide by 2."]
895            pub const POST_DIV_SELECT_1: u32 = 0x01;
896            #[doc = "Divide by 1."]
897            pub const POST_DIV_SELECT_2: u32 = 0x02;
898        }
899    }
900    #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
901    pub mod LOCK {
902        pub const offset: u32 = 31;
903        pub const mask: u32 = 0x01 << offset;
904        pub mod R {}
905        pub mod W {}
906        pub mod RW {}
907    }
908}
909#[doc = "Numerator of Audio PLL Fractional Loop Divider Register"]
910pub mod PLL_AUDIO_NUM {
911    #[doc = "30 bit numerator of fractional loop divider."]
912    pub mod A {
913        pub const offset: u32 = 0;
914        pub const mask: u32 = 0x3fff_ffff << offset;
915        pub mod R {}
916        pub mod W {}
917        pub mod RW {}
918    }
919}
920#[doc = "Denominator of Audio PLL Fractional Loop Divider Register"]
921pub mod PLL_AUDIO_DENOM {
922    #[doc = "30 bit denominator of fractional loop divider."]
923    pub mod B {
924        pub const offset: u32 = 0;
925        pub const mask: u32 = 0x3fff_ffff << offset;
926        pub mod R {}
927        pub mod W {}
928        pub mod RW {}
929    }
930}
931#[doc = "Analog ENET PLL Control Register"]
932pub mod PLL_ENET {
933    #[doc = "Powers down the PLL."]
934    pub mod POWERDOWN {
935        pub const offset: u32 = 12;
936        pub const mask: u32 = 0x01 << offset;
937        pub mod R {}
938        pub mod W {}
939        pub mod RW {}
940    }
941    #[doc = "Determines the bypass source."]
942    pub mod BYPASS_CLK_SRC {
943        pub const offset: u32 = 14;
944        pub const mask: u32 = 0x03 << offset;
945        pub mod R {}
946        pub mod W {}
947        pub mod RW {
948            #[doc = "Select the 24MHz oscillator as source."]
949            pub const REF_CLK_24M: u32 = 0;
950        }
951    }
952    #[doc = "Bypass the PLL."]
953    pub mod BYPASS {
954        pub const offset: u32 = 16;
955        pub const mask: u32 = 0x01 << offset;
956        pub mod R {}
957        pub mod W {}
958        pub mod RW {}
959    }
960    #[doc = "Enable the PLL providing ENET 500 MHz reference clock"]
961    pub mod ENET_500M_REF_EN {
962        pub const offset: u32 = 22;
963        pub const mask: u32 = 0x01 << offset;
964        pub mod R {}
965        pub mod W {}
966        pub mod RW {}
967    }
968    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
969    pub mod LOCK {
970        pub const offset: u32 = 31;
971        pub const mask: u32 = 0x01 << offset;
972        pub mod R {}
973        pub mod W {}
974        pub mod RW {}
975    }
976}
977#[doc = "Analog ENET PLL Control Register"]
978pub mod PLL_ENET_SET {
979    #[doc = "Powers down the PLL."]
980    pub mod POWERDOWN {
981        pub const offset: u32 = 12;
982        pub const mask: u32 = 0x01 << offset;
983        pub mod R {}
984        pub mod W {}
985        pub mod RW {}
986    }
987    #[doc = "Determines the bypass source."]
988    pub mod BYPASS_CLK_SRC {
989        pub const offset: u32 = 14;
990        pub const mask: u32 = 0x03 << offset;
991        pub mod R {}
992        pub mod W {}
993        pub mod RW {
994            #[doc = "Select the 24MHz oscillator as source."]
995            pub const REF_CLK_24M: u32 = 0;
996        }
997    }
998    #[doc = "Bypass the PLL."]
999    pub mod BYPASS {
1000        pub const offset: u32 = 16;
1001        pub const mask: u32 = 0x01 << offset;
1002        pub mod R {}
1003        pub mod W {}
1004        pub mod RW {}
1005    }
1006    #[doc = "Enable the PLL providing ENET 500 MHz reference clock"]
1007    pub mod ENET_500M_REF_EN {
1008        pub const offset: u32 = 22;
1009        pub const mask: u32 = 0x01 << offset;
1010        pub mod R {}
1011        pub mod W {}
1012        pub mod RW {}
1013    }
1014    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1015    pub mod LOCK {
1016        pub const offset: u32 = 31;
1017        pub const mask: u32 = 0x01 << offset;
1018        pub mod R {}
1019        pub mod W {}
1020        pub mod RW {}
1021    }
1022}
1023#[doc = "Analog ENET PLL Control Register"]
1024pub mod PLL_ENET_CLR {
1025    #[doc = "Powers down the PLL."]
1026    pub mod POWERDOWN {
1027        pub const offset: u32 = 12;
1028        pub const mask: u32 = 0x01 << offset;
1029        pub mod R {}
1030        pub mod W {}
1031        pub mod RW {}
1032    }
1033    #[doc = "Determines the bypass source."]
1034    pub mod BYPASS_CLK_SRC {
1035        pub const offset: u32 = 14;
1036        pub const mask: u32 = 0x03 << offset;
1037        pub mod R {}
1038        pub mod W {}
1039        pub mod RW {
1040            #[doc = "Select the 24MHz oscillator as source."]
1041            pub const REF_CLK_24M: u32 = 0;
1042        }
1043    }
1044    #[doc = "Bypass the PLL."]
1045    pub mod BYPASS {
1046        pub const offset: u32 = 16;
1047        pub const mask: u32 = 0x01 << offset;
1048        pub mod R {}
1049        pub mod W {}
1050        pub mod RW {}
1051    }
1052    #[doc = "Enable the PLL providing ENET 500 MHz reference clock"]
1053    pub mod ENET_500M_REF_EN {
1054        pub const offset: u32 = 22;
1055        pub const mask: u32 = 0x01 << offset;
1056        pub mod R {}
1057        pub mod W {}
1058        pub mod RW {}
1059    }
1060    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1061    pub mod LOCK {
1062        pub const offset: u32 = 31;
1063        pub const mask: u32 = 0x01 << offset;
1064        pub mod R {}
1065        pub mod W {}
1066        pub mod RW {}
1067    }
1068}
1069#[doc = "Analog ENET PLL Control Register"]
1070pub mod PLL_ENET_TOG {
1071    #[doc = "Powers down the PLL."]
1072    pub mod POWERDOWN {
1073        pub const offset: u32 = 12;
1074        pub const mask: u32 = 0x01 << offset;
1075        pub mod R {}
1076        pub mod W {}
1077        pub mod RW {}
1078    }
1079    #[doc = "Determines the bypass source."]
1080    pub mod BYPASS_CLK_SRC {
1081        pub const offset: u32 = 14;
1082        pub const mask: u32 = 0x03 << offset;
1083        pub mod R {}
1084        pub mod W {}
1085        pub mod RW {
1086            #[doc = "Select the 24MHz oscillator as source."]
1087            pub const REF_CLK_24M: u32 = 0;
1088        }
1089    }
1090    #[doc = "Bypass the PLL."]
1091    pub mod BYPASS {
1092        pub const offset: u32 = 16;
1093        pub const mask: u32 = 0x01 << offset;
1094        pub mod R {}
1095        pub mod W {}
1096        pub mod RW {}
1097    }
1098    #[doc = "Enable the PLL providing ENET 500 MHz reference clock"]
1099    pub mod ENET_500M_REF_EN {
1100        pub const offset: u32 = 22;
1101        pub const mask: u32 = 0x01 << offset;
1102        pub mod R {}
1103        pub mod W {}
1104        pub mod RW {}
1105    }
1106    #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1107    pub mod LOCK {
1108        pub const offset: u32 = 31;
1109        pub const mask: u32 = 0x01 << offset;
1110        pub mod R {}
1111        pub mod W {}
1112        pub mod RW {}
1113    }
1114}
1115#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
1116pub mod PFD_480 {
1117    #[doc = "This field controls the fractional divide value"]
1118    pub mod PFD0_FRAC {
1119        pub const offset: u32 = 0;
1120        pub const mask: u32 = 0x3f << offset;
1121        pub mod R {}
1122        pub mod W {}
1123        pub mod RW {}
1124    }
1125    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1126    pub mod PFD0_STABLE {
1127        pub const offset: u32 = 6;
1128        pub const mask: u32 = 0x01 << offset;
1129        pub mod R {}
1130        pub mod W {}
1131        pub mod RW {}
1132    }
1133    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1134    pub mod PFD0_CLKGATE {
1135        pub const offset: u32 = 7;
1136        pub const mask: u32 = 0x01 << offset;
1137        pub mod R {}
1138        pub mod W {}
1139        pub mod RW {}
1140    }
1141    #[doc = "This field controls the fractional divide value"]
1142    pub mod PFD1_FRAC {
1143        pub const offset: u32 = 8;
1144        pub const mask: u32 = 0x3f << offset;
1145        pub mod R {}
1146        pub mod W {}
1147        pub mod RW {}
1148    }
1149    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1150    pub mod PFD1_STABLE {
1151        pub const offset: u32 = 14;
1152        pub const mask: u32 = 0x01 << offset;
1153        pub mod R {}
1154        pub mod W {}
1155        pub mod RW {}
1156    }
1157    #[doc = "IO Clock Gate"]
1158    pub mod PFD1_CLKGATE {
1159        pub const offset: u32 = 15;
1160        pub const mask: u32 = 0x01 << offset;
1161        pub mod R {}
1162        pub mod W {}
1163        pub mod RW {}
1164    }
1165    #[doc = "This field controls the fractional divide value"]
1166    pub mod PFD2_FRAC {
1167        pub const offset: u32 = 16;
1168        pub const mask: u32 = 0x3f << offset;
1169        pub mod R {}
1170        pub mod W {}
1171        pub mod RW {}
1172    }
1173    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1174    pub mod PFD2_STABLE {
1175        pub const offset: u32 = 22;
1176        pub const mask: u32 = 0x01 << offset;
1177        pub mod R {}
1178        pub mod W {}
1179        pub mod RW {}
1180    }
1181    #[doc = "IO Clock Gate"]
1182    pub mod PFD2_CLKGATE {
1183        pub const offset: u32 = 23;
1184        pub const mask: u32 = 0x01 << offset;
1185        pub mod R {}
1186        pub mod W {}
1187        pub mod RW {}
1188    }
1189    #[doc = "This field controls the fractional divide value"]
1190    pub mod PFD3_FRAC {
1191        pub const offset: u32 = 24;
1192        pub const mask: u32 = 0x3f << offset;
1193        pub mod R {}
1194        pub mod W {}
1195        pub mod RW {}
1196    }
1197    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1198    pub mod PFD3_STABLE {
1199        pub const offset: u32 = 30;
1200        pub const mask: u32 = 0x01 << offset;
1201        pub mod R {}
1202        pub mod W {}
1203        pub mod RW {}
1204    }
1205    #[doc = "IO Clock Gate"]
1206    pub mod PFD3_CLKGATE {
1207        pub const offset: u32 = 31;
1208        pub const mask: u32 = 0x01 << offset;
1209        pub mod R {}
1210        pub mod W {}
1211        pub mod RW {}
1212    }
1213}
1214#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
1215pub mod PFD_480_SET {
1216    #[doc = "This field controls the fractional divide value"]
1217    pub mod PFD0_FRAC {
1218        pub const offset: u32 = 0;
1219        pub const mask: u32 = 0x3f << offset;
1220        pub mod R {}
1221        pub mod W {}
1222        pub mod RW {}
1223    }
1224    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1225    pub mod PFD0_STABLE {
1226        pub const offset: u32 = 6;
1227        pub const mask: u32 = 0x01 << offset;
1228        pub mod R {}
1229        pub mod W {}
1230        pub mod RW {}
1231    }
1232    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1233    pub mod PFD0_CLKGATE {
1234        pub const offset: u32 = 7;
1235        pub const mask: u32 = 0x01 << offset;
1236        pub mod R {}
1237        pub mod W {}
1238        pub mod RW {}
1239    }
1240    #[doc = "This field controls the fractional divide value"]
1241    pub mod PFD1_FRAC {
1242        pub const offset: u32 = 8;
1243        pub const mask: u32 = 0x3f << offset;
1244        pub mod R {}
1245        pub mod W {}
1246        pub mod RW {}
1247    }
1248    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1249    pub mod PFD1_STABLE {
1250        pub const offset: u32 = 14;
1251        pub const mask: u32 = 0x01 << offset;
1252        pub mod R {}
1253        pub mod W {}
1254        pub mod RW {}
1255    }
1256    #[doc = "IO Clock Gate"]
1257    pub mod PFD1_CLKGATE {
1258        pub const offset: u32 = 15;
1259        pub const mask: u32 = 0x01 << offset;
1260        pub mod R {}
1261        pub mod W {}
1262        pub mod RW {}
1263    }
1264    #[doc = "This field controls the fractional divide value"]
1265    pub mod PFD2_FRAC {
1266        pub const offset: u32 = 16;
1267        pub const mask: u32 = 0x3f << offset;
1268        pub mod R {}
1269        pub mod W {}
1270        pub mod RW {}
1271    }
1272    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1273    pub mod PFD2_STABLE {
1274        pub const offset: u32 = 22;
1275        pub const mask: u32 = 0x01 << offset;
1276        pub mod R {}
1277        pub mod W {}
1278        pub mod RW {}
1279    }
1280    #[doc = "IO Clock Gate"]
1281    pub mod PFD2_CLKGATE {
1282        pub const offset: u32 = 23;
1283        pub const mask: u32 = 0x01 << offset;
1284        pub mod R {}
1285        pub mod W {}
1286        pub mod RW {}
1287    }
1288    #[doc = "This field controls the fractional divide value"]
1289    pub mod PFD3_FRAC {
1290        pub const offset: u32 = 24;
1291        pub const mask: u32 = 0x3f << offset;
1292        pub mod R {}
1293        pub mod W {}
1294        pub mod RW {}
1295    }
1296    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1297    pub mod PFD3_STABLE {
1298        pub const offset: u32 = 30;
1299        pub const mask: u32 = 0x01 << offset;
1300        pub mod R {}
1301        pub mod W {}
1302        pub mod RW {}
1303    }
1304    #[doc = "IO Clock Gate"]
1305    pub mod PFD3_CLKGATE {
1306        pub const offset: u32 = 31;
1307        pub const mask: u32 = 0x01 << offset;
1308        pub mod R {}
1309        pub mod W {}
1310        pub mod RW {}
1311    }
1312}
1313#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
1314pub mod PFD_480_CLR {
1315    #[doc = "This field controls the fractional divide value"]
1316    pub mod PFD0_FRAC {
1317        pub const offset: u32 = 0;
1318        pub const mask: u32 = 0x3f << offset;
1319        pub mod R {}
1320        pub mod W {}
1321        pub mod RW {}
1322    }
1323    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1324    pub mod PFD0_STABLE {
1325        pub const offset: u32 = 6;
1326        pub const mask: u32 = 0x01 << offset;
1327        pub mod R {}
1328        pub mod W {}
1329        pub mod RW {}
1330    }
1331    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1332    pub mod PFD0_CLKGATE {
1333        pub const offset: u32 = 7;
1334        pub const mask: u32 = 0x01 << offset;
1335        pub mod R {}
1336        pub mod W {}
1337        pub mod RW {}
1338    }
1339    #[doc = "This field controls the fractional divide value"]
1340    pub mod PFD1_FRAC {
1341        pub const offset: u32 = 8;
1342        pub const mask: u32 = 0x3f << offset;
1343        pub mod R {}
1344        pub mod W {}
1345        pub mod RW {}
1346    }
1347    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1348    pub mod PFD1_STABLE {
1349        pub const offset: u32 = 14;
1350        pub const mask: u32 = 0x01 << offset;
1351        pub mod R {}
1352        pub mod W {}
1353        pub mod RW {}
1354    }
1355    #[doc = "IO Clock Gate"]
1356    pub mod PFD1_CLKGATE {
1357        pub const offset: u32 = 15;
1358        pub const mask: u32 = 0x01 << offset;
1359        pub mod R {}
1360        pub mod W {}
1361        pub mod RW {}
1362    }
1363    #[doc = "This field controls the fractional divide value"]
1364    pub mod PFD2_FRAC {
1365        pub const offset: u32 = 16;
1366        pub const mask: u32 = 0x3f << offset;
1367        pub mod R {}
1368        pub mod W {}
1369        pub mod RW {}
1370    }
1371    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1372    pub mod PFD2_STABLE {
1373        pub const offset: u32 = 22;
1374        pub const mask: u32 = 0x01 << offset;
1375        pub mod R {}
1376        pub mod W {}
1377        pub mod RW {}
1378    }
1379    #[doc = "IO Clock Gate"]
1380    pub mod PFD2_CLKGATE {
1381        pub const offset: u32 = 23;
1382        pub const mask: u32 = 0x01 << offset;
1383        pub mod R {}
1384        pub mod W {}
1385        pub mod RW {}
1386    }
1387    #[doc = "This field controls the fractional divide value"]
1388    pub mod PFD3_FRAC {
1389        pub const offset: u32 = 24;
1390        pub const mask: u32 = 0x3f << offset;
1391        pub mod R {}
1392        pub mod W {}
1393        pub mod RW {}
1394    }
1395    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1396    pub mod PFD3_STABLE {
1397        pub const offset: u32 = 30;
1398        pub const mask: u32 = 0x01 << offset;
1399        pub mod R {}
1400        pub mod W {}
1401        pub mod RW {}
1402    }
1403    #[doc = "IO Clock Gate"]
1404    pub mod PFD3_CLKGATE {
1405        pub const offset: u32 = 31;
1406        pub const mask: u32 = 0x01 << offset;
1407        pub mod R {}
1408        pub mod W {}
1409        pub mod RW {}
1410    }
1411}
1412#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
1413pub mod PFD_480_TOG {
1414    #[doc = "This field controls the fractional divide value"]
1415    pub mod PFD0_FRAC {
1416        pub const offset: u32 = 0;
1417        pub const mask: u32 = 0x3f << offset;
1418        pub mod R {}
1419        pub mod W {}
1420        pub mod RW {}
1421    }
1422    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1423    pub mod PFD0_STABLE {
1424        pub const offset: u32 = 6;
1425        pub const mask: u32 = 0x01 << offset;
1426        pub mod R {}
1427        pub mod W {}
1428        pub mod RW {}
1429    }
1430    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1431    pub mod PFD0_CLKGATE {
1432        pub const offset: u32 = 7;
1433        pub const mask: u32 = 0x01 << offset;
1434        pub mod R {}
1435        pub mod W {}
1436        pub mod RW {}
1437    }
1438    #[doc = "This field controls the fractional divide value"]
1439    pub mod PFD1_FRAC {
1440        pub const offset: u32 = 8;
1441        pub const mask: u32 = 0x3f << offset;
1442        pub mod R {}
1443        pub mod W {}
1444        pub mod RW {}
1445    }
1446    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1447    pub mod PFD1_STABLE {
1448        pub const offset: u32 = 14;
1449        pub const mask: u32 = 0x01 << offset;
1450        pub mod R {}
1451        pub mod W {}
1452        pub mod RW {}
1453    }
1454    #[doc = "IO Clock Gate"]
1455    pub mod PFD1_CLKGATE {
1456        pub const offset: u32 = 15;
1457        pub const mask: u32 = 0x01 << offset;
1458        pub mod R {}
1459        pub mod W {}
1460        pub mod RW {}
1461    }
1462    #[doc = "This field controls the fractional divide value"]
1463    pub mod PFD2_FRAC {
1464        pub const offset: u32 = 16;
1465        pub const mask: u32 = 0x3f << offset;
1466        pub mod R {}
1467        pub mod W {}
1468        pub mod RW {}
1469    }
1470    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1471    pub mod PFD2_STABLE {
1472        pub const offset: u32 = 22;
1473        pub const mask: u32 = 0x01 << offset;
1474        pub mod R {}
1475        pub mod W {}
1476        pub mod RW {}
1477    }
1478    #[doc = "IO Clock Gate"]
1479    pub mod PFD2_CLKGATE {
1480        pub const offset: u32 = 23;
1481        pub const mask: u32 = 0x01 << offset;
1482        pub mod R {}
1483        pub mod W {}
1484        pub mod RW {}
1485    }
1486    #[doc = "This field controls the fractional divide value"]
1487    pub mod PFD3_FRAC {
1488        pub const offset: u32 = 24;
1489        pub const mask: u32 = 0x3f << offset;
1490        pub mod R {}
1491        pub mod W {}
1492        pub mod RW {}
1493    }
1494    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1495    pub mod PFD3_STABLE {
1496        pub const offset: u32 = 30;
1497        pub const mask: u32 = 0x01 << offset;
1498        pub mod R {}
1499        pub mod W {}
1500        pub mod RW {}
1501    }
1502    #[doc = "IO Clock Gate"]
1503    pub mod PFD3_CLKGATE {
1504        pub const offset: u32 = 31;
1505        pub const mask: u32 = 0x01 << offset;
1506        pub mod R {}
1507        pub mod W {}
1508        pub mod RW {}
1509    }
1510}
1511#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
1512pub mod PFD_528 {
1513    #[doc = "This field controls the fractional divide value"]
1514    pub mod PFD0_FRAC {
1515        pub const offset: u32 = 0;
1516        pub const mask: u32 = 0x3f << offset;
1517        pub mod R {}
1518        pub mod W {}
1519        pub mod RW {}
1520    }
1521    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1522    pub mod PFD0_STABLE {
1523        pub const offset: u32 = 6;
1524        pub const mask: u32 = 0x01 << offset;
1525        pub mod R {}
1526        pub mod W {}
1527        pub mod RW {}
1528    }
1529    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1530    pub mod PFD0_CLKGATE {
1531        pub const offset: u32 = 7;
1532        pub const mask: u32 = 0x01 << offset;
1533        pub mod R {}
1534        pub mod W {}
1535        pub mod RW {}
1536    }
1537    #[doc = "This field controls the fractional divide value"]
1538    pub mod PFD1_FRAC {
1539        pub const offset: u32 = 8;
1540        pub const mask: u32 = 0x3f << offset;
1541        pub mod R {}
1542        pub mod W {}
1543        pub mod RW {}
1544    }
1545    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1546    pub mod PFD1_STABLE {
1547        pub const offset: u32 = 14;
1548        pub const mask: u32 = 0x01 << offset;
1549        pub mod R {}
1550        pub mod W {}
1551        pub mod RW {}
1552    }
1553    #[doc = "IO Clock Gate"]
1554    pub mod PFD1_CLKGATE {
1555        pub const offset: u32 = 15;
1556        pub const mask: u32 = 0x01 << offset;
1557        pub mod R {}
1558        pub mod W {}
1559        pub mod RW {}
1560    }
1561    #[doc = "This field controls the fractional divide value"]
1562    pub mod PFD2_FRAC {
1563        pub const offset: u32 = 16;
1564        pub const mask: u32 = 0x3f << offset;
1565        pub mod R {}
1566        pub mod W {}
1567        pub mod RW {}
1568    }
1569    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1570    pub mod PFD2_STABLE {
1571        pub const offset: u32 = 22;
1572        pub const mask: u32 = 0x01 << offset;
1573        pub mod R {}
1574        pub mod W {}
1575        pub mod RW {}
1576    }
1577    #[doc = "IO Clock Gate"]
1578    pub mod PFD2_CLKGATE {
1579        pub const offset: u32 = 23;
1580        pub const mask: u32 = 0x01 << offset;
1581        pub mod R {}
1582        pub mod W {}
1583        pub mod RW {}
1584    }
1585    #[doc = "This field controls the fractional divide value"]
1586    pub mod PFD3_FRAC {
1587        pub const offset: u32 = 24;
1588        pub const mask: u32 = 0x3f << offset;
1589        pub mod R {}
1590        pub mod W {}
1591        pub mod RW {}
1592    }
1593    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1594    pub mod PFD3_STABLE {
1595        pub const offset: u32 = 30;
1596        pub const mask: u32 = 0x01 << offset;
1597        pub mod R {}
1598        pub mod W {}
1599        pub mod RW {}
1600    }
1601    #[doc = "IO Clock Gate"]
1602    pub mod PFD3_CLKGATE {
1603        pub const offset: u32 = 31;
1604        pub const mask: u32 = 0x01 << offset;
1605        pub mod R {}
1606        pub mod W {}
1607        pub mod RW {}
1608    }
1609}
1610#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
1611pub mod PFD_528_SET {
1612    #[doc = "This field controls the fractional divide value"]
1613    pub mod PFD0_FRAC {
1614        pub const offset: u32 = 0;
1615        pub const mask: u32 = 0x3f << offset;
1616        pub mod R {}
1617        pub mod W {}
1618        pub mod RW {}
1619    }
1620    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1621    pub mod PFD0_STABLE {
1622        pub const offset: u32 = 6;
1623        pub const mask: u32 = 0x01 << offset;
1624        pub mod R {}
1625        pub mod W {}
1626        pub mod RW {}
1627    }
1628    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1629    pub mod PFD0_CLKGATE {
1630        pub const offset: u32 = 7;
1631        pub const mask: u32 = 0x01 << offset;
1632        pub mod R {}
1633        pub mod W {}
1634        pub mod RW {}
1635    }
1636    #[doc = "This field controls the fractional divide value"]
1637    pub mod PFD1_FRAC {
1638        pub const offset: u32 = 8;
1639        pub const mask: u32 = 0x3f << offset;
1640        pub mod R {}
1641        pub mod W {}
1642        pub mod RW {}
1643    }
1644    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1645    pub mod PFD1_STABLE {
1646        pub const offset: u32 = 14;
1647        pub const mask: u32 = 0x01 << offset;
1648        pub mod R {}
1649        pub mod W {}
1650        pub mod RW {}
1651    }
1652    #[doc = "IO Clock Gate"]
1653    pub mod PFD1_CLKGATE {
1654        pub const offset: u32 = 15;
1655        pub const mask: u32 = 0x01 << offset;
1656        pub mod R {}
1657        pub mod W {}
1658        pub mod RW {}
1659    }
1660    #[doc = "This field controls the fractional divide value"]
1661    pub mod PFD2_FRAC {
1662        pub const offset: u32 = 16;
1663        pub const mask: u32 = 0x3f << offset;
1664        pub mod R {}
1665        pub mod W {}
1666        pub mod RW {}
1667    }
1668    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1669    pub mod PFD2_STABLE {
1670        pub const offset: u32 = 22;
1671        pub const mask: u32 = 0x01 << offset;
1672        pub mod R {}
1673        pub mod W {}
1674        pub mod RW {}
1675    }
1676    #[doc = "IO Clock Gate"]
1677    pub mod PFD2_CLKGATE {
1678        pub const offset: u32 = 23;
1679        pub const mask: u32 = 0x01 << offset;
1680        pub mod R {}
1681        pub mod W {}
1682        pub mod RW {}
1683    }
1684    #[doc = "This field controls the fractional divide value"]
1685    pub mod PFD3_FRAC {
1686        pub const offset: u32 = 24;
1687        pub const mask: u32 = 0x3f << offset;
1688        pub mod R {}
1689        pub mod W {}
1690        pub mod RW {}
1691    }
1692    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1693    pub mod PFD3_STABLE {
1694        pub const offset: u32 = 30;
1695        pub const mask: u32 = 0x01 << offset;
1696        pub mod R {}
1697        pub mod W {}
1698        pub mod RW {}
1699    }
1700    #[doc = "IO Clock Gate"]
1701    pub mod PFD3_CLKGATE {
1702        pub const offset: u32 = 31;
1703        pub const mask: u32 = 0x01 << offset;
1704        pub mod R {}
1705        pub mod W {}
1706        pub mod RW {}
1707    }
1708}
1709#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
1710pub mod PFD_528_CLR {
1711    #[doc = "This field controls the fractional divide value"]
1712    pub mod PFD0_FRAC {
1713        pub const offset: u32 = 0;
1714        pub const mask: u32 = 0x3f << offset;
1715        pub mod R {}
1716        pub mod W {}
1717        pub mod RW {}
1718    }
1719    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1720    pub mod PFD0_STABLE {
1721        pub const offset: u32 = 6;
1722        pub const mask: u32 = 0x01 << offset;
1723        pub mod R {}
1724        pub mod W {}
1725        pub mod RW {}
1726    }
1727    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1728    pub mod PFD0_CLKGATE {
1729        pub const offset: u32 = 7;
1730        pub const mask: u32 = 0x01 << offset;
1731        pub mod R {}
1732        pub mod W {}
1733        pub mod RW {}
1734    }
1735    #[doc = "This field controls the fractional divide value"]
1736    pub mod PFD1_FRAC {
1737        pub const offset: u32 = 8;
1738        pub const mask: u32 = 0x3f << offset;
1739        pub mod R {}
1740        pub mod W {}
1741        pub mod RW {}
1742    }
1743    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1744    pub mod PFD1_STABLE {
1745        pub const offset: u32 = 14;
1746        pub const mask: u32 = 0x01 << offset;
1747        pub mod R {}
1748        pub mod W {}
1749        pub mod RW {}
1750    }
1751    #[doc = "IO Clock Gate"]
1752    pub mod PFD1_CLKGATE {
1753        pub const offset: u32 = 15;
1754        pub const mask: u32 = 0x01 << offset;
1755        pub mod R {}
1756        pub mod W {}
1757        pub mod RW {}
1758    }
1759    #[doc = "This field controls the fractional divide value"]
1760    pub mod PFD2_FRAC {
1761        pub const offset: u32 = 16;
1762        pub const mask: u32 = 0x3f << offset;
1763        pub mod R {}
1764        pub mod W {}
1765        pub mod RW {}
1766    }
1767    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1768    pub mod PFD2_STABLE {
1769        pub const offset: u32 = 22;
1770        pub const mask: u32 = 0x01 << offset;
1771        pub mod R {}
1772        pub mod W {}
1773        pub mod RW {}
1774    }
1775    #[doc = "IO Clock Gate"]
1776    pub mod PFD2_CLKGATE {
1777        pub const offset: u32 = 23;
1778        pub const mask: u32 = 0x01 << offset;
1779        pub mod R {}
1780        pub mod W {}
1781        pub mod RW {}
1782    }
1783    #[doc = "This field controls the fractional divide value"]
1784    pub mod PFD3_FRAC {
1785        pub const offset: u32 = 24;
1786        pub const mask: u32 = 0x3f << offset;
1787        pub mod R {}
1788        pub mod W {}
1789        pub mod RW {}
1790    }
1791    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1792    pub mod PFD3_STABLE {
1793        pub const offset: u32 = 30;
1794        pub const mask: u32 = 0x01 << offset;
1795        pub mod R {}
1796        pub mod W {}
1797        pub mod RW {}
1798    }
1799    #[doc = "IO Clock Gate"]
1800    pub mod PFD3_CLKGATE {
1801        pub const offset: u32 = 31;
1802        pub const mask: u32 = 0x01 << offset;
1803        pub mod R {}
1804        pub mod W {}
1805        pub mod RW {}
1806    }
1807}
1808#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
1809pub mod PFD_528_TOG {
1810    #[doc = "This field controls the fractional divide value"]
1811    pub mod PFD0_FRAC {
1812        pub const offset: u32 = 0;
1813        pub const mask: u32 = 0x3f << offset;
1814        pub mod R {}
1815        pub mod W {}
1816        pub mod RW {}
1817    }
1818    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1819    pub mod PFD0_STABLE {
1820        pub const offset: u32 = 6;
1821        pub const mask: u32 = 0x01 << offset;
1822        pub mod R {}
1823        pub mod W {}
1824        pub mod RW {}
1825    }
1826    #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
1827    pub mod PFD0_CLKGATE {
1828        pub const offset: u32 = 7;
1829        pub const mask: u32 = 0x01 << offset;
1830        pub mod R {}
1831        pub mod W {}
1832        pub mod RW {}
1833    }
1834    #[doc = "This field controls the fractional divide value"]
1835    pub mod PFD1_FRAC {
1836        pub const offset: u32 = 8;
1837        pub const mask: u32 = 0x3f << offset;
1838        pub mod R {}
1839        pub mod W {}
1840        pub mod RW {}
1841    }
1842    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1843    pub mod PFD1_STABLE {
1844        pub const offset: u32 = 14;
1845        pub const mask: u32 = 0x01 << offset;
1846        pub mod R {}
1847        pub mod W {}
1848        pub mod RW {}
1849    }
1850    #[doc = "IO Clock Gate"]
1851    pub mod PFD1_CLKGATE {
1852        pub const offset: u32 = 15;
1853        pub const mask: u32 = 0x01 << offset;
1854        pub mod R {}
1855        pub mod W {}
1856        pub mod RW {}
1857    }
1858    #[doc = "This field controls the fractional divide value"]
1859    pub mod PFD2_FRAC {
1860        pub const offset: u32 = 16;
1861        pub const mask: u32 = 0x3f << offset;
1862        pub mod R {}
1863        pub mod W {}
1864        pub mod RW {}
1865    }
1866    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1867    pub mod PFD2_STABLE {
1868        pub const offset: u32 = 22;
1869        pub const mask: u32 = 0x01 << offset;
1870        pub mod R {}
1871        pub mod W {}
1872        pub mod RW {}
1873    }
1874    #[doc = "IO Clock Gate"]
1875    pub mod PFD2_CLKGATE {
1876        pub const offset: u32 = 23;
1877        pub const mask: u32 = 0x01 << offset;
1878        pub mod R {}
1879        pub mod W {}
1880        pub mod RW {}
1881    }
1882    #[doc = "This field controls the fractional divide value"]
1883    pub mod PFD3_FRAC {
1884        pub const offset: u32 = 24;
1885        pub const mask: u32 = 0x3f << offset;
1886        pub mod R {}
1887        pub mod W {}
1888        pub mod RW {}
1889    }
1890    #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
1891    pub mod PFD3_STABLE {
1892        pub const offset: u32 = 30;
1893        pub const mask: u32 = 0x01 << offset;
1894        pub mod R {}
1895        pub mod W {}
1896        pub mod RW {}
1897    }
1898    #[doc = "IO Clock Gate"]
1899    pub mod PFD3_CLKGATE {
1900        pub const offset: u32 = 31;
1901        pub const mask: u32 = 0x01 << offset;
1902        pub mod R {}
1903        pub mod W {}
1904        pub mod RW {}
1905    }
1906}
1907#[doc = "Miscellaneous Register 0"]
1908pub mod MISC0 {
1909    #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
1910    pub mod REFTOP_PWD {
1911        pub const offset: u32 = 0;
1912        pub const mask: u32 = 0x01 << offset;
1913        pub mod R {}
1914        pub mod W {}
1915        pub mod RW {}
1916    }
1917    #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
1918    pub mod REFTOP_SELFBIASOFF {
1919        pub const offset: u32 = 3;
1920        pub const mask: u32 = 0x01 << offset;
1921        pub mod R {}
1922        pub mod W {}
1923        pub mod RW {
1924            #[doc = "Uses coarse bias currents for startup"]
1925            pub const REFTOP_SELFBIASOFF_0: u32 = 0;
1926            #[doc = "Uses bandgap-based bias currents for best performance."]
1927            pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
1928        }
1929    }
1930    #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
1931    pub mod REFTOP_VBGADJ {
1932        pub const offset: u32 = 4;
1933        pub const mask: u32 = 0x07 << offset;
1934        pub mod R {}
1935        pub mod W {}
1936        pub mod RW {
1937            #[doc = "Nominal VBG"]
1938            pub const REFTOP_VBGADJ_0: u32 = 0;
1939            #[doc = "VBG+0.78%"]
1940            pub const REFTOP_VBGADJ_1: u32 = 0x01;
1941            #[doc = "VBG+1.56%"]
1942            pub const REFTOP_VBGADJ_2: u32 = 0x02;
1943            #[doc = "VBG+2.34%"]
1944            pub const REFTOP_VBGADJ_3: u32 = 0x03;
1945            #[doc = "VBG-0.78%"]
1946            pub const REFTOP_VBGADJ_4: u32 = 0x04;
1947            #[doc = "VBG-1.56%"]
1948            pub const REFTOP_VBGADJ_5: u32 = 0x05;
1949            #[doc = "VBG-2.34%"]
1950            pub const REFTOP_VBGADJ_6: u32 = 0x06;
1951            #[doc = "VBG-3.12%"]
1952            pub const REFTOP_VBGADJ_7: u32 = 0x07;
1953        }
1954    }
1955    #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
1956    pub mod REFTOP_VBGUP {
1957        pub const offset: u32 = 7;
1958        pub const mask: u32 = 0x01 << offset;
1959        pub mod R {}
1960        pub mod W {}
1961        pub mod RW {}
1962    }
1963    #[doc = "Configure the analog behavior in stop mode."]
1964    pub mod STOP_MODE_CONFIG {
1965        pub const offset: u32 = 10;
1966        pub const mask: u32 = 0x03 << offset;
1967        pub mod R {}
1968        pub mod W {}
1969        pub mod RW {
1970            #[doc = "All analog except RTC powered down on stop mode assertion."]
1971            pub const STOP_MODE_CONFIG_0: u32 = 0;
1972            #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
1973            pub const STOP_MODE_CONFIG_1: u32 = 0x01;
1974            #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
1975            pub const STOP_MODE_CONFIG_2: u32 = 0x02;
1976            #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
1977            pub const STOP_MODE_CONFIG_3: u32 = 0x03;
1978        }
1979    }
1980    #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
1981    pub mod DISCON_HIGH_SNVS {
1982        pub const offset: u32 = 12;
1983        pub const mask: u32 = 0x01 << offset;
1984        pub mod R {}
1985        pub mod W {}
1986        pub mod RW {
1987            #[doc = "Turn on the switch"]
1988            pub const DISCON_HIGH_SNVS_0: u32 = 0;
1989            #[doc = "Turn off the switch"]
1990            pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
1991        }
1992    }
1993    #[doc = "This field determines the bias current in the 24MHz oscillator"]
1994    pub mod OSC_I {
1995        pub const offset: u32 = 13;
1996        pub const mask: u32 = 0x03 << offset;
1997        pub mod R {}
1998        pub mod W {}
1999        pub mod RW {
2000            #[doc = "Nominal"]
2001            pub const NOMINAL: u32 = 0;
2002            #[doc = "Decrease current by 12.5%"]
2003            pub const MINUS_12_5_PERCENT: u32 = 0x01;
2004            #[doc = "Decrease current by 25.0%"]
2005            pub const MINUS_25_PERCENT: u32 = 0x02;
2006            #[doc = "Decrease current by 37.5%"]
2007            pub const MINUS_37_5_PERCENT: u32 = 0x03;
2008        }
2009    }
2010    #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2011    pub mod OSC_XTALOK {
2012        pub const offset: u32 = 15;
2013        pub const mask: u32 = 0x01 << offset;
2014        pub mod R {}
2015        pub mod W {}
2016        pub mod RW {}
2017    }
2018    #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2019    pub mod OSC_XTALOK_EN {
2020        pub const offset: u32 = 16;
2021        pub const mask: u32 = 0x01 << offset;
2022        pub mod R {}
2023        pub mod W {}
2024        pub mod RW {}
2025    }
2026    #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2027    pub mod CLKGATE_CTRL {
2028        pub const offset: u32 = 25;
2029        pub const mask: u32 = 0x01 << offset;
2030        pub mod R {}
2031        pub mod W {}
2032        pub mod RW {
2033            #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2034            pub const ALLOW_AUTO_GATE: u32 = 0;
2035            #[doc = "Prevent the logic from ever gating off the clock."]
2036            pub const NO_AUTO_GATE: u32 = 0x01;
2037        }
2038    }
2039    #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2040    pub mod CLKGATE_DELAY {
2041        pub const offset: u32 = 26;
2042        pub const mask: u32 = 0x07 << offset;
2043        pub mod R {}
2044        pub mod W {}
2045        pub mod RW {
2046            #[doc = "0.5ms"]
2047            pub const CLKGATE_DELAY_0: u32 = 0;
2048            #[doc = "1.0ms"]
2049            pub const CLKGATE_DELAY_1: u32 = 0x01;
2050            #[doc = "2.0ms"]
2051            pub const CLKGATE_DELAY_2: u32 = 0x02;
2052            #[doc = "3.0ms"]
2053            pub const CLKGATE_DELAY_3: u32 = 0x03;
2054            #[doc = "4.0ms"]
2055            pub const CLKGATE_DELAY_4: u32 = 0x04;
2056            #[doc = "5.0ms"]
2057            pub const CLKGATE_DELAY_5: u32 = 0x05;
2058            #[doc = "6.0ms"]
2059            pub const CLKGATE_DELAY_6: u32 = 0x06;
2060            #[doc = "7.0ms"]
2061            pub const CLKGATE_DELAY_7: u32 = 0x07;
2062        }
2063    }
2064    #[doc = "This field indicates which chip source is being used for the rtc clock"]
2065    pub mod RTC_XTAL_SOURCE {
2066        pub const offset: u32 = 29;
2067        pub const mask: u32 = 0x01 << offset;
2068        pub mod R {}
2069        pub mod W {}
2070        pub mod RW {
2071            #[doc = "Internal ring oscillator"]
2072            pub const RTC_XTAL_SOURCE_0: u32 = 0;
2073            #[doc = "RTC_XTAL"]
2074            pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2075        }
2076    }
2077    #[doc = "This field powers down the 24M crystal oscillator if set true"]
2078    pub mod XTAL_24M_PWD {
2079        pub const offset: u32 = 30;
2080        pub const mask: u32 = 0x01 << offset;
2081        pub mod R {}
2082        pub mod W {}
2083        pub mod RW {}
2084    }
2085}
2086#[doc = "Miscellaneous Register 0"]
2087pub mod MISC0_SET {
2088    #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2089    pub mod REFTOP_PWD {
2090        pub const offset: u32 = 0;
2091        pub const mask: u32 = 0x01 << offset;
2092        pub mod R {}
2093        pub mod W {}
2094        pub mod RW {}
2095    }
2096    #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2097    pub mod REFTOP_SELFBIASOFF {
2098        pub const offset: u32 = 3;
2099        pub const mask: u32 = 0x01 << offset;
2100        pub mod R {}
2101        pub mod W {}
2102        pub mod RW {
2103            #[doc = "Uses coarse bias currents for startup"]
2104            pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2105            #[doc = "Uses bandgap-based bias currents for best performance."]
2106            pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2107        }
2108    }
2109    #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
2110    pub mod REFTOP_VBGADJ {
2111        pub const offset: u32 = 4;
2112        pub const mask: u32 = 0x07 << offset;
2113        pub mod R {}
2114        pub mod W {}
2115        pub mod RW {
2116            #[doc = "Nominal VBG"]
2117            pub const REFTOP_VBGADJ_0: u32 = 0;
2118            #[doc = "VBG+0.78%"]
2119            pub const REFTOP_VBGADJ_1: u32 = 0x01;
2120            #[doc = "VBG+1.56%"]
2121            pub const REFTOP_VBGADJ_2: u32 = 0x02;
2122            #[doc = "VBG+2.34%"]
2123            pub const REFTOP_VBGADJ_3: u32 = 0x03;
2124            #[doc = "VBG-0.78%"]
2125            pub const REFTOP_VBGADJ_4: u32 = 0x04;
2126            #[doc = "VBG-1.56%"]
2127            pub const REFTOP_VBGADJ_5: u32 = 0x05;
2128            #[doc = "VBG-2.34%"]
2129            pub const REFTOP_VBGADJ_6: u32 = 0x06;
2130            #[doc = "VBG-3.12%"]
2131            pub const REFTOP_VBGADJ_7: u32 = 0x07;
2132        }
2133    }
2134    #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
2135    pub mod REFTOP_VBGUP {
2136        pub const offset: u32 = 7;
2137        pub const mask: u32 = 0x01 << offset;
2138        pub mod R {}
2139        pub mod W {}
2140        pub mod RW {}
2141    }
2142    #[doc = "Configure the analog behavior in stop mode."]
2143    pub mod STOP_MODE_CONFIG {
2144        pub const offset: u32 = 10;
2145        pub const mask: u32 = 0x03 << offset;
2146        pub mod R {}
2147        pub mod W {}
2148        pub mod RW {
2149            #[doc = "All analog except RTC powered down on stop mode assertion."]
2150            pub const STOP_MODE_CONFIG_0: u32 = 0;
2151            #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
2152            pub const STOP_MODE_CONFIG_1: u32 = 0x01;
2153            #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
2154            pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2155            #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
2156            pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2157        }
2158    }
2159    #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2160    pub mod DISCON_HIGH_SNVS {
2161        pub const offset: u32 = 12;
2162        pub const mask: u32 = 0x01 << offset;
2163        pub mod R {}
2164        pub mod W {}
2165        pub mod RW {
2166            #[doc = "Turn on the switch"]
2167            pub const DISCON_HIGH_SNVS_0: u32 = 0;
2168            #[doc = "Turn off the switch"]
2169            pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2170        }
2171    }
2172    #[doc = "This field determines the bias current in the 24MHz oscillator"]
2173    pub mod OSC_I {
2174        pub const offset: u32 = 13;
2175        pub const mask: u32 = 0x03 << offset;
2176        pub mod R {}
2177        pub mod W {}
2178        pub mod RW {
2179            #[doc = "Nominal"]
2180            pub const NOMINAL: u32 = 0;
2181            #[doc = "Decrease current by 12.5%"]
2182            pub const MINUS_12_5_PERCENT: u32 = 0x01;
2183            #[doc = "Decrease current by 25.0%"]
2184            pub const MINUS_25_PERCENT: u32 = 0x02;
2185            #[doc = "Decrease current by 37.5%"]
2186            pub const MINUS_37_5_PERCENT: u32 = 0x03;
2187        }
2188    }
2189    #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2190    pub mod OSC_XTALOK {
2191        pub const offset: u32 = 15;
2192        pub const mask: u32 = 0x01 << offset;
2193        pub mod R {}
2194        pub mod W {}
2195        pub mod RW {}
2196    }
2197    #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2198    pub mod OSC_XTALOK_EN {
2199        pub const offset: u32 = 16;
2200        pub const mask: u32 = 0x01 << offset;
2201        pub mod R {}
2202        pub mod W {}
2203        pub mod RW {}
2204    }
2205    #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2206    pub mod CLKGATE_CTRL {
2207        pub const offset: u32 = 25;
2208        pub const mask: u32 = 0x01 << offset;
2209        pub mod R {}
2210        pub mod W {}
2211        pub mod RW {
2212            #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2213            pub const ALLOW_AUTO_GATE: u32 = 0;
2214            #[doc = "Prevent the logic from ever gating off the clock."]
2215            pub const NO_AUTO_GATE: u32 = 0x01;
2216        }
2217    }
2218    #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2219    pub mod CLKGATE_DELAY {
2220        pub const offset: u32 = 26;
2221        pub const mask: u32 = 0x07 << offset;
2222        pub mod R {}
2223        pub mod W {}
2224        pub mod RW {
2225            #[doc = "0.5ms"]
2226            pub const CLKGATE_DELAY_0: u32 = 0;
2227            #[doc = "1.0ms"]
2228            pub const CLKGATE_DELAY_1: u32 = 0x01;
2229            #[doc = "2.0ms"]
2230            pub const CLKGATE_DELAY_2: u32 = 0x02;
2231            #[doc = "3.0ms"]
2232            pub const CLKGATE_DELAY_3: u32 = 0x03;
2233            #[doc = "4.0ms"]
2234            pub const CLKGATE_DELAY_4: u32 = 0x04;
2235            #[doc = "5.0ms"]
2236            pub const CLKGATE_DELAY_5: u32 = 0x05;
2237            #[doc = "6.0ms"]
2238            pub const CLKGATE_DELAY_6: u32 = 0x06;
2239            #[doc = "7.0ms"]
2240            pub const CLKGATE_DELAY_7: u32 = 0x07;
2241        }
2242    }
2243    #[doc = "This field indicates which chip source is being used for the rtc clock"]
2244    pub mod RTC_XTAL_SOURCE {
2245        pub const offset: u32 = 29;
2246        pub const mask: u32 = 0x01 << offset;
2247        pub mod R {}
2248        pub mod W {}
2249        pub mod RW {
2250            #[doc = "Internal ring oscillator"]
2251            pub const RTC_XTAL_SOURCE_0: u32 = 0;
2252            #[doc = "RTC_XTAL"]
2253            pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2254        }
2255    }
2256    #[doc = "This field powers down the 24M crystal oscillator if set true"]
2257    pub mod XTAL_24M_PWD {
2258        pub const offset: u32 = 30;
2259        pub const mask: u32 = 0x01 << offset;
2260        pub mod R {}
2261        pub mod W {}
2262        pub mod RW {}
2263    }
2264}
2265#[doc = "Miscellaneous Register 0"]
2266pub mod MISC0_CLR {
2267    #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2268    pub mod REFTOP_PWD {
2269        pub const offset: u32 = 0;
2270        pub const mask: u32 = 0x01 << offset;
2271        pub mod R {}
2272        pub mod W {}
2273        pub mod RW {}
2274    }
2275    #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2276    pub mod REFTOP_SELFBIASOFF {
2277        pub const offset: u32 = 3;
2278        pub const mask: u32 = 0x01 << offset;
2279        pub mod R {}
2280        pub mod W {}
2281        pub mod RW {
2282            #[doc = "Uses coarse bias currents for startup"]
2283            pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2284            #[doc = "Uses bandgap-based bias currents for best performance."]
2285            pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2286        }
2287    }
2288    #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
2289    pub mod REFTOP_VBGADJ {
2290        pub const offset: u32 = 4;
2291        pub const mask: u32 = 0x07 << offset;
2292        pub mod R {}
2293        pub mod W {}
2294        pub mod RW {
2295            #[doc = "Nominal VBG"]
2296            pub const REFTOP_VBGADJ_0: u32 = 0;
2297            #[doc = "VBG+0.78%"]
2298            pub const REFTOP_VBGADJ_1: u32 = 0x01;
2299            #[doc = "VBG+1.56%"]
2300            pub const REFTOP_VBGADJ_2: u32 = 0x02;
2301            #[doc = "VBG+2.34%"]
2302            pub const REFTOP_VBGADJ_3: u32 = 0x03;
2303            #[doc = "VBG-0.78%"]
2304            pub const REFTOP_VBGADJ_4: u32 = 0x04;
2305            #[doc = "VBG-1.56%"]
2306            pub const REFTOP_VBGADJ_5: u32 = 0x05;
2307            #[doc = "VBG-2.34%"]
2308            pub const REFTOP_VBGADJ_6: u32 = 0x06;
2309            #[doc = "VBG-3.12%"]
2310            pub const REFTOP_VBGADJ_7: u32 = 0x07;
2311        }
2312    }
2313    #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
2314    pub mod REFTOP_VBGUP {
2315        pub const offset: u32 = 7;
2316        pub const mask: u32 = 0x01 << offset;
2317        pub mod R {}
2318        pub mod W {}
2319        pub mod RW {}
2320    }
2321    #[doc = "Configure the analog behavior in stop mode."]
2322    pub mod STOP_MODE_CONFIG {
2323        pub const offset: u32 = 10;
2324        pub const mask: u32 = 0x03 << offset;
2325        pub mod R {}
2326        pub mod W {}
2327        pub mod RW {
2328            #[doc = "All analog except RTC powered down on stop mode assertion."]
2329            pub const STOP_MODE_CONFIG_0: u32 = 0;
2330            #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
2331            pub const STOP_MODE_CONFIG_1: u32 = 0x01;
2332            #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
2333            pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2334            #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
2335            pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2336        }
2337    }
2338    #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2339    pub mod DISCON_HIGH_SNVS {
2340        pub const offset: u32 = 12;
2341        pub const mask: u32 = 0x01 << offset;
2342        pub mod R {}
2343        pub mod W {}
2344        pub mod RW {
2345            #[doc = "Turn on the switch"]
2346            pub const DISCON_HIGH_SNVS_0: u32 = 0;
2347            #[doc = "Turn off the switch"]
2348            pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2349        }
2350    }
2351    #[doc = "This field determines the bias current in the 24MHz oscillator"]
2352    pub mod OSC_I {
2353        pub const offset: u32 = 13;
2354        pub const mask: u32 = 0x03 << offset;
2355        pub mod R {}
2356        pub mod W {}
2357        pub mod RW {
2358            #[doc = "Nominal"]
2359            pub const NOMINAL: u32 = 0;
2360            #[doc = "Decrease current by 12.5%"]
2361            pub const MINUS_12_5_PERCENT: u32 = 0x01;
2362            #[doc = "Decrease current by 25.0%"]
2363            pub const MINUS_25_PERCENT: u32 = 0x02;
2364            #[doc = "Decrease current by 37.5%"]
2365            pub const MINUS_37_5_PERCENT: u32 = 0x03;
2366        }
2367    }
2368    #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2369    pub mod OSC_XTALOK {
2370        pub const offset: u32 = 15;
2371        pub const mask: u32 = 0x01 << offset;
2372        pub mod R {}
2373        pub mod W {}
2374        pub mod RW {}
2375    }
2376    #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2377    pub mod OSC_XTALOK_EN {
2378        pub const offset: u32 = 16;
2379        pub const mask: u32 = 0x01 << offset;
2380        pub mod R {}
2381        pub mod W {}
2382        pub mod RW {}
2383    }
2384    #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2385    pub mod CLKGATE_CTRL {
2386        pub const offset: u32 = 25;
2387        pub const mask: u32 = 0x01 << offset;
2388        pub mod R {}
2389        pub mod W {}
2390        pub mod RW {
2391            #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2392            pub const ALLOW_AUTO_GATE: u32 = 0;
2393            #[doc = "Prevent the logic from ever gating off the clock."]
2394            pub const NO_AUTO_GATE: u32 = 0x01;
2395        }
2396    }
2397    #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2398    pub mod CLKGATE_DELAY {
2399        pub const offset: u32 = 26;
2400        pub const mask: u32 = 0x07 << offset;
2401        pub mod R {}
2402        pub mod W {}
2403        pub mod RW {
2404            #[doc = "0.5ms"]
2405            pub const CLKGATE_DELAY_0: u32 = 0;
2406            #[doc = "1.0ms"]
2407            pub const CLKGATE_DELAY_1: u32 = 0x01;
2408            #[doc = "2.0ms"]
2409            pub const CLKGATE_DELAY_2: u32 = 0x02;
2410            #[doc = "3.0ms"]
2411            pub const CLKGATE_DELAY_3: u32 = 0x03;
2412            #[doc = "4.0ms"]
2413            pub const CLKGATE_DELAY_4: u32 = 0x04;
2414            #[doc = "5.0ms"]
2415            pub const CLKGATE_DELAY_5: u32 = 0x05;
2416            #[doc = "6.0ms"]
2417            pub const CLKGATE_DELAY_6: u32 = 0x06;
2418            #[doc = "7.0ms"]
2419            pub const CLKGATE_DELAY_7: u32 = 0x07;
2420        }
2421    }
2422    #[doc = "This field indicates which chip source is being used for the rtc clock"]
2423    pub mod RTC_XTAL_SOURCE {
2424        pub const offset: u32 = 29;
2425        pub const mask: u32 = 0x01 << offset;
2426        pub mod R {}
2427        pub mod W {}
2428        pub mod RW {
2429            #[doc = "Internal ring oscillator"]
2430            pub const RTC_XTAL_SOURCE_0: u32 = 0;
2431            #[doc = "RTC_XTAL"]
2432            pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2433        }
2434    }
2435    #[doc = "This field powers down the 24M crystal oscillator if set true"]
2436    pub mod XTAL_24M_PWD {
2437        pub const offset: u32 = 30;
2438        pub const mask: u32 = 0x01 << offset;
2439        pub mod R {}
2440        pub mod W {}
2441        pub mod RW {}
2442    }
2443}
2444#[doc = "Miscellaneous Register 0"]
2445pub mod MISC0_TOG {
2446    #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2447    pub mod REFTOP_PWD {
2448        pub const offset: u32 = 0;
2449        pub const mask: u32 = 0x01 << offset;
2450        pub mod R {}
2451        pub mod W {}
2452        pub mod RW {}
2453    }
2454    #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2455    pub mod REFTOP_SELFBIASOFF {
2456        pub const offset: u32 = 3;
2457        pub const mask: u32 = 0x01 << offset;
2458        pub mod R {}
2459        pub mod W {}
2460        pub mod RW {
2461            #[doc = "Uses coarse bias currents for startup"]
2462            pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2463            #[doc = "Uses bandgap-based bias currents for best performance."]
2464            pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2465        }
2466    }
2467    #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
2468    pub mod REFTOP_VBGADJ {
2469        pub const offset: u32 = 4;
2470        pub const mask: u32 = 0x07 << offset;
2471        pub mod R {}
2472        pub mod W {}
2473        pub mod RW {
2474            #[doc = "Nominal VBG"]
2475            pub const REFTOP_VBGADJ_0: u32 = 0;
2476            #[doc = "VBG+0.78%"]
2477            pub const REFTOP_VBGADJ_1: u32 = 0x01;
2478            #[doc = "VBG+1.56%"]
2479            pub const REFTOP_VBGADJ_2: u32 = 0x02;
2480            #[doc = "VBG+2.34%"]
2481            pub const REFTOP_VBGADJ_3: u32 = 0x03;
2482            #[doc = "VBG-0.78%"]
2483            pub const REFTOP_VBGADJ_4: u32 = 0x04;
2484            #[doc = "VBG-1.56%"]
2485            pub const REFTOP_VBGADJ_5: u32 = 0x05;
2486            #[doc = "VBG-2.34%"]
2487            pub const REFTOP_VBGADJ_6: u32 = 0x06;
2488            #[doc = "VBG-3.12%"]
2489            pub const REFTOP_VBGADJ_7: u32 = 0x07;
2490        }
2491    }
2492    #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
2493    pub mod REFTOP_VBGUP {
2494        pub const offset: u32 = 7;
2495        pub const mask: u32 = 0x01 << offset;
2496        pub mod R {}
2497        pub mod W {}
2498        pub mod RW {}
2499    }
2500    #[doc = "Configure the analog behavior in stop mode."]
2501    pub mod STOP_MODE_CONFIG {
2502        pub const offset: u32 = 10;
2503        pub const mask: u32 = 0x03 << offset;
2504        pub mod R {}
2505        pub mod W {}
2506        pub mod RW {
2507            #[doc = "All analog except RTC powered down on stop mode assertion."]
2508            pub const STOP_MODE_CONFIG_0: u32 = 0;
2509            #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
2510            pub const STOP_MODE_CONFIG_1: u32 = 0x01;
2511            #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
2512            pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2513            #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
2514            pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2515        }
2516    }
2517    #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2518    pub mod DISCON_HIGH_SNVS {
2519        pub const offset: u32 = 12;
2520        pub const mask: u32 = 0x01 << offset;
2521        pub mod R {}
2522        pub mod W {}
2523        pub mod RW {
2524            #[doc = "Turn on the switch"]
2525            pub const DISCON_HIGH_SNVS_0: u32 = 0;
2526            #[doc = "Turn off the switch"]
2527            pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2528        }
2529    }
2530    #[doc = "This field determines the bias current in the 24MHz oscillator"]
2531    pub mod OSC_I {
2532        pub const offset: u32 = 13;
2533        pub const mask: u32 = 0x03 << offset;
2534        pub mod R {}
2535        pub mod W {}
2536        pub mod RW {
2537            #[doc = "Nominal"]
2538            pub const NOMINAL: u32 = 0;
2539            #[doc = "Decrease current by 12.5%"]
2540            pub const MINUS_12_5_PERCENT: u32 = 0x01;
2541            #[doc = "Decrease current by 25.0%"]
2542            pub const MINUS_25_PERCENT: u32 = 0x02;
2543            #[doc = "Decrease current by 37.5%"]
2544            pub const MINUS_37_5_PERCENT: u32 = 0x03;
2545        }
2546    }
2547    #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2548    pub mod OSC_XTALOK {
2549        pub const offset: u32 = 15;
2550        pub const mask: u32 = 0x01 << offset;
2551        pub mod R {}
2552        pub mod W {}
2553        pub mod RW {}
2554    }
2555    #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2556    pub mod OSC_XTALOK_EN {
2557        pub const offset: u32 = 16;
2558        pub const mask: u32 = 0x01 << offset;
2559        pub mod R {}
2560        pub mod W {}
2561        pub mod RW {}
2562    }
2563    #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2564    pub mod CLKGATE_CTRL {
2565        pub const offset: u32 = 25;
2566        pub const mask: u32 = 0x01 << offset;
2567        pub mod R {}
2568        pub mod W {}
2569        pub mod RW {
2570            #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2571            pub const ALLOW_AUTO_GATE: u32 = 0;
2572            #[doc = "Prevent the logic from ever gating off the clock."]
2573            pub const NO_AUTO_GATE: u32 = 0x01;
2574        }
2575    }
2576    #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2577    pub mod CLKGATE_DELAY {
2578        pub const offset: u32 = 26;
2579        pub const mask: u32 = 0x07 << offset;
2580        pub mod R {}
2581        pub mod W {}
2582        pub mod RW {
2583            #[doc = "0.5ms"]
2584            pub const CLKGATE_DELAY_0: u32 = 0;
2585            #[doc = "1.0ms"]
2586            pub const CLKGATE_DELAY_1: u32 = 0x01;
2587            #[doc = "2.0ms"]
2588            pub const CLKGATE_DELAY_2: u32 = 0x02;
2589            #[doc = "3.0ms"]
2590            pub const CLKGATE_DELAY_3: u32 = 0x03;
2591            #[doc = "4.0ms"]
2592            pub const CLKGATE_DELAY_4: u32 = 0x04;
2593            #[doc = "5.0ms"]
2594            pub const CLKGATE_DELAY_5: u32 = 0x05;
2595            #[doc = "6.0ms"]
2596            pub const CLKGATE_DELAY_6: u32 = 0x06;
2597            #[doc = "7.0ms"]
2598            pub const CLKGATE_DELAY_7: u32 = 0x07;
2599        }
2600    }
2601    #[doc = "This field indicates which chip source is being used for the rtc clock"]
2602    pub mod RTC_XTAL_SOURCE {
2603        pub const offset: u32 = 29;
2604        pub const mask: u32 = 0x01 << offset;
2605        pub mod R {}
2606        pub mod W {}
2607        pub mod RW {
2608            #[doc = "Internal ring oscillator"]
2609            pub const RTC_XTAL_SOURCE_0: u32 = 0;
2610            #[doc = "RTC_XTAL"]
2611            pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2612        }
2613    }
2614    #[doc = "This field powers down the 24M crystal oscillator if set true"]
2615    pub mod XTAL_24M_PWD {
2616        pub const offset: u32 = 30;
2617        pub const mask: u32 = 0x01 << offset;
2618        pub mod R {}
2619        pub mod W {}
2620        pub mod RW {}
2621    }
2622}
2623#[doc = "Miscellaneous Register 1"]
2624pub mod MISC1 {
2625    #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2626    pub mod PFD_480_AUTOGATE_EN {
2627        pub const offset: u32 = 16;
2628        pub const mask: u32 = 0x01 << offset;
2629        pub mod R {}
2630        pub mod W {}
2631        pub mod RW {}
2632    }
2633    #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2634    pub mod PFD_528_AUTOGATE_EN {
2635        pub const offset: u32 = 17;
2636        pub const mask: u32 = 0x01 << offset;
2637        pub mod R {}
2638        pub mod W {}
2639        pub mod RW {}
2640    }
2641    #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2642    pub mod IRQ_TEMPPANIC {
2643        pub const offset: u32 = 27;
2644        pub const mask: u32 = 0x01 << offset;
2645        pub mod R {}
2646        pub mod W {}
2647        pub mod RW {}
2648    }
2649    #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2650    pub mod IRQ_TEMPLOW {
2651        pub const offset: u32 = 28;
2652        pub const mask: u32 = 0x01 << offset;
2653        pub mod R {}
2654        pub mod W {}
2655        pub mod RW {}
2656    }
2657    #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2658    pub mod IRQ_TEMPHIGH {
2659        pub const offset: u32 = 29;
2660        pub const mask: u32 = 0x01 << offset;
2661        pub mod R {}
2662        pub mod W {}
2663        pub mod RW {}
2664    }
2665    #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2666    pub mod IRQ_ANA_BO {
2667        pub const offset: u32 = 30;
2668        pub const mask: u32 = 0x01 << offset;
2669        pub mod R {}
2670        pub mod W {}
2671        pub mod RW {}
2672    }
2673    #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2674    pub mod IRQ_DIG_BO {
2675        pub const offset: u32 = 31;
2676        pub const mask: u32 = 0x01 << offset;
2677        pub mod R {}
2678        pub mod W {}
2679        pub mod RW {}
2680    }
2681}
2682#[doc = "Miscellaneous Register 1"]
2683pub mod MISC1_SET {
2684    #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2685    pub mod PFD_480_AUTOGATE_EN {
2686        pub const offset: u32 = 16;
2687        pub const mask: u32 = 0x01 << offset;
2688        pub mod R {}
2689        pub mod W {}
2690        pub mod RW {}
2691    }
2692    #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2693    pub mod PFD_528_AUTOGATE_EN {
2694        pub const offset: u32 = 17;
2695        pub const mask: u32 = 0x01 << offset;
2696        pub mod R {}
2697        pub mod W {}
2698        pub mod RW {}
2699    }
2700    #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2701    pub mod IRQ_TEMPPANIC {
2702        pub const offset: u32 = 27;
2703        pub const mask: u32 = 0x01 << offset;
2704        pub mod R {}
2705        pub mod W {}
2706        pub mod RW {}
2707    }
2708    #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2709    pub mod IRQ_TEMPLOW {
2710        pub const offset: u32 = 28;
2711        pub const mask: u32 = 0x01 << offset;
2712        pub mod R {}
2713        pub mod W {}
2714        pub mod RW {}
2715    }
2716    #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2717    pub mod IRQ_TEMPHIGH {
2718        pub const offset: u32 = 29;
2719        pub const mask: u32 = 0x01 << offset;
2720        pub mod R {}
2721        pub mod W {}
2722        pub mod RW {}
2723    }
2724    #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2725    pub mod IRQ_ANA_BO {
2726        pub const offset: u32 = 30;
2727        pub const mask: u32 = 0x01 << offset;
2728        pub mod R {}
2729        pub mod W {}
2730        pub mod RW {}
2731    }
2732    #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2733    pub mod IRQ_DIG_BO {
2734        pub const offset: u32 = 31;
2735        pub const mask: u32 = 0x01 << offset;
2736        pub mod R {}
2737        pub mod W {}
2738        pub mod RW {}
2739    }
2740}
2741#[doc = "Miscellaneous Register 1"]
2742pub mod MISC1_CLR {
2743    #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2744    pub mod PFD_480_AUTOGATE_EN {
2745        pub const offset: u32 = 16;
2746        pub const mask: u32 = 0x01 << offset;
2747        pub mod R {}
2748        pub mod W {}
2749        pub mod RW {}
2750    }
2751    #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2752    pub mod PFD_528_AUTOGATE_EN {
2753        pub const offset: u32 = 17;
2754        pub const mask: u32 = 0x01 << offset;
2755        pub mod R {}
2756        pub mod W {}
2757        pub mod RW {}
2758    }
2759    #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2760    pub mod IRQ_TEMPPANIC {
2761        pub const offset: u32 = 27;
2762        pub const mask: u32 = 0x01 << offset;
2763        pub mod R {}
2764        pub mod W {}
2765        pub mod RW {}
2766    }
2767    #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2768    pub mod IRQ_TEMPLOW {
2769        pub const offset: u32 = 28;
2770        pub const mask: u32 = 0x01 << offset;
2771        pub mod R {}
2772        pub mod W {}
2773        pub mod RW {}
2774    }
2775    #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2776    pub mod IRQ_TEMPHIGH {
2777        pub const offset: u32 = 29;
2778        pub const mask: u32 = 0x01 << offset;
2779        pub mod R {}
2780        pub mod W {}
2781        pub mod RW {}
2782    }
2783    #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2784    pub mod IRQ_ANA_BO {
2785        pub const offset: u32 = 30;
2786        pub const mask: u32 = 0x01 << offset;
2787        pub mod R {}
2788        pub mod W {}
2789        pub mod RW {}
2790    }
2791    #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2792    pub mod IRQ_DIG_BO {
2793        pub const offset: u32 = 31;
2794        pub const mask: u32 = 0x01 << offset;
2795        pub mod R {}
2796        pub mod W {}
2797        pub mod RW {}
2798    }
2799}
2800#[doc = "Miscellaneous Register 1"]
2801pub mod MISC1_TOG {
2802    #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2803    pub mod PFD_480_AUTOGATE_EN {
2804        pub const offset: u32 = 16;
2805        pub const mask: u32 = 0x01 << offset;
2806        pub mod R {}
2807        pub mod W {}
2808        pub mod RW {}
2809    }
2810    #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2811    pub mod PFD_528_AUTOGATE_EN {
2812        pub const offset: u32 = 17;
2813        pub const mask: u32 = 0x01 << offset;
2814        pub mod R {}
2815        pub mod W {}
2816        pub mod RW {}
2817    }
2818    #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2819    pub mod IRQ_TEMPPANIC {
2820        pub const offset: u32 = 27;
2821        pub const mask: u32 = 0x01 << offset;
2822        pub mod R {}
2823        pub mod W {}
2824        pub mod RW {}
2825    }
2826    #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2827    pub mod IRQ_TEMPLOW {
2828        pub const offset: u32 = 28;
2829        pub const mask: u32 = 0x01 << offset;
2830        pub mod R {}
2831        pub mod W {}
2832        pub mod RW {}
2833    }
2834    #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2835    pub mod IRQ_TEMPHIGH {
2836        pub const offset: u32 = 29;
2837        pub const mask: u32 = 0x01 << offset;
2838        pub mod R {}
2839        pub mod W {}
2840        pub mod RW {}
2841    }
2842    #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2843    pub mod IRQ_ANA_BO {
2844        pub const offset: u32 = 30;
2845        pub const mask: u32 = 0x01 << offset;
2846        pub mod R {}
2847        pub mod W {}
2848        pub mod RW {}
2849    }
2850    #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2851    pub mod IRQ_DIG_BO {
2852        pub const offset: u32 = 31;
2853        pub const mask: u32 = 0x01 << offset;
2854        pub mod R {}
2855        pub mod W {}
2856        pub mod RW {}
2857    }
2858}
2859#[doc = "Miscellaneous Register 2"]
2860pub mod MISC2 {
2861    #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
2862    pub mod REG0_BO_OFFSET {
2863        pub const offset: u32 = 0;
2864        pub const mask: u32 = 0x07 << offset;
2865        pub mod R {}
2866        pub mod W {}
2867        pub mod RW {
2868            #[doc = "Brownout offset = 0.100V"]
2869            pub const REG0_BO_OFFSET_4: u32 = 0x04;
2870            #[doc = "Brownout offset = 0.175V"]
2871            pub const REG0_BO_OFFSET_7: u32 = 0x07;
2872        }
2873    }
2874    #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
2875    pub mod REG0_BO_STATUS {
2876        pub const offset: u32 = 3;
2877        pub const mask: u32 = 0x01 << offset;
2878        pub mod R {}
2879        pub mod W {}
2880        pub mod RW {
2881            #[doc = "Brownout, supply is below target minus brownout offset."]
2882            pub const REG0_BO_STATUS_1: u32 = 0x01;
2883        }
2884    }
2885    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
2886    pub mod REG0_ENABLE_BO {
2887        pub const offset: u32 = 5;
2888        pub const mask: u32 = 0x01 << offset;
2889        pub mod R {}
2890        pub mod W {}
2891        pub mod RW {}
2892    }
2893    #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
2894    pub mod REG0_OK {
2895        pub const offset: u32 = 6;
2896        pub const mask: u32 = 0x01 << offset;
2897        pub mod R {}
2898        pub mod W {}
2899        pub mod RW {}
2900    }
2901    #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
2902    pub mod PLL3_DISABLE {
2903        pub const offset: u32 = 7;
2904        pub const mask: u32 = 0x01 << offset;
2905        pub mod R {}
2906        pub mod W {}
2907        pub mod RW {
2908            #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
2909            pub const PLL3_DISABLE_0: u32 = 0;
2910            #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
2911            pub const PLL3_DISABLE_1: u32 = 0x01;
2912        }
2913    }
2914    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
2915    pub mod REG1_BO_OFFSET {
2916        pub const offset: u32 = 8;
2917        pub const mask: u32 = 0x07 << offset;
2918        pub mod R {}
2919        pub mod W {}
2920        pub mod RW {
2921            #[doc = "Brownout offset = 0.100V"]
2922            pub const REG1_BO_OFFSET_4: u32 = 0x04;
2923            #[doc = "Brownout offset = 0.175V"]
2924            pub const REG1_BO_OFFSET_7: u32 = 0x07;
2925        }
2926    }
2927    #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
2928    pub mod REG1_BO_STATUS {
2929        pub const offset: u32 = 11;
2930        pub const mask: u32 = 0x01 << offset;
2931        pub mod R {}
2932        pub mod W {}
2933        pub mod RW {
2934            #[doc = "Brownout, supply is below target minus brownout offset."]
2935            pub const REG1_BO_STATUS_1: u32 = 0x01;
2936        }
2937    }
2938    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
2939    pub mod REG1_ENABLE_BO {
2940        pub const offset: u32 = 13;
2941        pub const mask: u32 = 0x01 << offset;
2942        pub mod R {}
2943        pub mod W {}
2944        pub mod RW {}
2945    }
2946    #[doc = "GPU supply Not related to CCM. See Power Management Unit (PMU)"]
2947    pub mod REG1_OK {
2948        pub const offset: u32 = 14;
2949        pub const mask: u32 = 0x01 << offset;
2950        pub mod R {}
2951        pub mod W {}
2952        pub mod RW {}
2953    }
2954    #[doc = "LSB of Post-divider for Audio PLL"]
2955    pub mod AUDIO_DIV_LSB {
2956        pub const offset: u32 = 15;
2957        pub const mask: u32 = 0x01 << offset;
2958        pub mod R {}
2959        pub mod W {}
2960        pub mod RW {
2961            #[doc = "divide by 1 (Default)"]
2962            pub const AUDIO_DIV_LSB_0: u32 = 0;
2963            #[doc = "divide by 2"]
2964            pub const AUDIO_DIV_LSB_1: u32 = 0x01;
2965        }
2966    }
2967    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
2968    pub mod REG2_BO_OFFSET {
2969        pub const offset: u32 = 16;
2970        pub const mask: u32 = 0x07 << offset;
2971        pub mod R {}
2972        pub mod W {}
2973        pub mod RW {
2974            #[doc = "Brownout offset = 0.100V"]
2975            pub const REG2_BO_OFFSET_4: u32 = 0x04;
2976            #[doc = "Brownout offset = 0.175V"]
2977            pub const REG2_BO_OFFSET_7: u32 = 0x07;
2978        }
2979    }
2980    #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
2981    pub mod REG2_BO_STATUS {
2982        pub const offset: u32 = 19;
2983        pub const mask: u32 = 0x01 << offset;
2984        pub mod R {}
2985        pub mod W {}
2986        pub mod RW {}
2987    }
2988    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
2989    pub mod REG2_ENABLE_BO {
2990        pub const offset: u32 = 21;
2991        pub const mask: u32 = 0x01 << offset;
2992        pub mod R {}
2993        pub mod W {}
2994        pub mod RW {}
2995    }
2996    #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
2997    pub mod REG2_OK {
2998        pub const offset: u32 = 22;
2999        pub const mask: u32 = 0x01 << offset;
3000        pub mod R {}
3001        pub mod W {}
3002        pub mod RW {}
3003    }
3004    #[doc = "MSB of Post-divider for Audio PLL"]
3005    pub mod AUDIO_DIV_MSB {
3006        pub const offset: u32 = 23;
3007        pub const mask: u32 = 0x01 << offset;
3008        pub mod R {}
3009        pub mod W {}
3010        pub mod RW {
3011            #[doc = "divide by 1 (Default)"]
3012            pub const AUDIO_DIV_MSB_0: u32 = 0;
3013            #[doc = "divide by 2"]
3014            pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3015        }
3016    }
3017    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3018    pub mod REG0_STEP_TIME {
3019        pub const offset: u32 = 24;
3020        pub const mask: u32 = 0x03 << offset;
3021        pub mod R {}
3022        pub mod W {}
3023        pub mod RW {
3024            #[doc = "64"]
3025            pub const _64_CLOCKS: u32 = 0;
3026            #[doc = "128"]
3027            pub const _128_CLOCKS: u32 = 0x01;
3028            #[doc = "256"]
3029            pub const _256_CLOCKS: u32 = 0x02;
3030            #[doc = "512"]
3031            pub const _512_CLOCKS: u32 = 0x03;
3032        }
3033    }
3034    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3035    pub mod REG1_STEP_TIME {
3036        pub const offset: u32 = 26;
3037        pub const mask: u32 = 0x03 << offset;
3038        pub mod R {}
3039        pub mod W {}
3040        pub mod RW {
3041            #[doc = "64"]
3042            pub const _64_CLOCKS: u32 = 0;
3043            #[doc = "128"]
3044            pub const _128_CLOCKS: u32 = 0x01;
3045            #[doc = "256"]
3046            pub const _256_CLOCKS: u32 = 0x02;
3047            #[doc = "512"]
3048            pub const _512_CLOCKS: u32 = 0x03;
3049        }
3050    }
3051    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3052    pub mod REG2_STEP_TIME {
3053        pub const offset: u32 = 28;
3054        pub const mask: u32 = 0x03 << offset;
3055        pub mod R {}
3056        pub mod W {}
3057        pub mod RW {
3058            #[doc = "64"]
3059            pub const _64_CLOCKS: u32 = 0;
3060            #[doc = "128"]
3061            pub const _128_CLOCKS: u32 = 0x01;
3062            #[doc = "256"]
3063            pub const _256_CLOCKS: u32 = 0x02;
3064            #[doc = "512"]
3065            pub const _512_CLOCKS: u32 = 0x03;
3066        }
3067    }
3068}
3069#[doc = "Miscellaneous Register 2"]
3070pub mod MISC2_SET {
3071    #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3072    pub mod REG0_BO_OFFSET {
3073        pub const offset: u32 = 0;
3074        pub const mask: u32 = 0x07 << offset;
3075        pub mod R {}
3076        pub mod W {}
3077        pub mod RW {
3078            #[doc = "Brownout offset = 0.100V"]
3079            pub const REG0_BO_OFFSET_4: u32 = 0x04;
3080            #[doc = "Brownout offset = 0.175V"]
3081            pub const REG0_BO_OFFSET_7: u32 = 0x07;
3082        }
3083    }
3084    #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
3085    pub mod REG0_BO_STATUS {
3086        pub const offset: u32 = 3;
3087        pub const mask: u32 = 0x01 << offset;
3088        pub mod R {}
3089        pub mod W {}
3090        pub mod RW {
3091            #[doc = "Brownout, supply is below target minus brownout offset."]
3092            pub const REG0_BO_STATUS_1: u32 = 0x01;
3093        }
3094    }
3095    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3096    pub mod REG0_ENABLE_BO {
3097        pub const offset: u32 = 5;
3098        pub const mask: u32 = 0x01 << offset;
3099        pub mod R {}
3100        pub mod W {}
3101        pub mod RW {}
3102    }
3103    #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
3104    pub mod REG0_OK {
3105        pub const offset: u32 = 6;
3106        pub const mask: u32 = 0x01 << offset;
3107        pub mod R {}
3108        pub mod W {}
3109        pub mod RW {}
3110    }
3111    #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
3112    pub mod PLL3_DISABLE {
3113        pub const offset: u32 = 7;
3114        pub const mask: u32 = 0x01 << offset;
3115        pub mod R {}
3116        pub mod W {}
3117        pub mod RW {
3118            #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
3119            pub const PLL3_DISABLE_0: u32 = 0;
3120            #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
3121            pub const PLL3_DISABLE_1: u32 = 0x01;
3122        }
3123    }
3124    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3125    pub mod REG1_BO_OFFSET {
3126        pub const offset: u32 = 8;
3127        pub const mask: u32 = 0x07 << offset;
3128        pub mod R {}
3129        pub mod W {}
3130        pub mod RW {
3131            #[doc = "Brownout offset = 0.100V"]
3132            pub const REG1_BO_OFFSET_4: u32 = 0x04;
3133            #[doc = "Brownout offset = 0.175V"]
3134            pub const REG1_BO_OFFSET_7: u32 = 0x07;
3135        }
3136    }
3137    #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
3138    pub mod REG1_BO_STATUS {
3139        pub const offset: u32 = 11;
3140        pub const mask: u32 = 0x01 << offset;
3141        pub mod R {}
3142        pub mod W {}
3143        pub mod RW {
3144            #[doc = "Brownout, supply is below target minus brownout offset."]
3145            pub const REG1_BO_STATUS_1: u32 = 0x01;
3146        }
3147    }
3148    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3149    pub mod REG1_ENABLE_BO {
3150        pub const offset: u32 = 13;
3151        pub const mask: u32 = 0x01 << offset;
3152        pub mod R {}
3153        pub mod W {}
3154        pub mod RW {}
3155    }
3156    #[doc = "GPU supply Not related to CCM. See Power Management Unit (PMU)"]
3157    pub mod REG1_OK {
3158        pub const offset: u32 = 14;
3159        pub const mask: u32 = 0x01 << offset;
3160        pub mod R {}
3161        pub mod W {}
3162        pub mod RW {}
3163    }
3164    #[doc = "LSB of Post-divider for Audio PLL"]
3165    pub mod AUDIO_DIV_LSB {
3166        pub const offset: u32 = 15;
3167        pub const mask: u32 = 0x01 << offset;
3168        pub mod R {}
3169        pub mod W {}
3170        pub mod RW {
3171            #[doc = "divide by 1 (Default)"]
3172            pub const AUDIO_DIV_LSB_0: u32 = 0;
3173            #[doc = "divide by 2"]
3174            pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3175        }
3176    }
3177    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3178    pub mod REG2_BO_OFFSET {
3179        pub const offset: u32 = 16;
3180        pub const mask: u32 = 0x07 << offset;
3181        pub mod R {}
3182        pub mod W {}
3183        pub mod RW {
3184            #[doc = "Brownout offset = 0.100V"]
3185            pub const REG2_BO_OFFSET_4: u32 = 0x04;
3186            #[doc = "Brownout offset = 0.175V"]
3187            pub const REG2_BO_OFFSET_7: u32 = 0x07;
3188        }
3189    }
3190    #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
3191    pub mod REG2_BO_STATUS {
3192        pub const offset: u32 = 19;
3193        pub const mask: u32 = 0x01 << offset;
3194        pub mod R {}
3195        pub mod W {}
3196        pub mod RW {}
3197    }
3198    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3199    pub mod REG2_ENABLE_BO {
3200        pub const offset: u32 = 21;
3201        pub const mask: u32 = 0x01 << offset;
3202        pub mod R {}
3203        pub mod W {}
3204        pub mod RW {}
3205    }
3206    #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3207    pub mod REG2_OK {
3208        pub const offset: u32 = 22;
3209        pub const mask: u32 = 0x01 << offset;
3210        pub mod R {}
3211        pub mod W {}
3212        pub mod RW {}
3213    }
3214    #[doc = "MSB of Post-divider for Audio PLL"]
3215    pub mod AUDIO_DIV_MSB {
3216        pub const offset: u32 = 23;
3217        pub const mask: u32 = 0x01 << offset;
3218        pub mod R {}
3219        pub mod W {}
3220        pub mod RW {
3221            #[doc = "divide by 1 (Default)"]
3222            pub const AUDIO_DIV_MSB_0: u32 = 0;
3223            #[doc = "divide by 2"]
3224            pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3225        }
3226    }
3227    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3228    pub mod REG0_STEP_TIME {
3229        pub const offset: u32 = 24;
3230        pub const mask: u32 = 0x03 << offset;
3231        pub mod R {}
3232        pub mod W {}
3233        pub mod RW {
3234            #[doc = "64"]
3235            pub const _64_CLOCKS: u32 = 0;
3236            #[doc = "128"]
3237            pub const _128_CLOCKS: u32 = 0x01;
3238            #[doc = "256"]
3239            pub const _256_CLOCKS: u32 = 0x02;
3240            #[doc = "512"]
3241            pub const _512_CLOCKS: u32 = 0x03;
3242        }
3243    }
3244    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3245    pub mod REG1_STEP_TIME {
3246        pub const offset: u32 = 26;
3247        pub const mask: u32 = 0x03 << offset;
3248        pub mod R {}
3249        pub mod W {}
3250        pub mod RW {
3251            #[doc = "64"]
3252            pub const _64_CLOCKS: u32 = 0;
3253            #[doc = "128"]
3254            pub const _128_CLOCKS: u32 = 0x01;
3255            #[doc = "256"]
3256            pub const _256_CLOCKS: u32 = 0x02;
3257            #[doc = "512"]
3258            pub const _512_CLOCKS: u32 = 0x03;
3259        }
3260    }
3261    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3262    pub mod REG2_STEP_TIME {
3263        pub const offset: u32 = 28;
3264        pub const mask: u32 = 0x03 << offset;
3265        pub mod R {}
3266        pub mod W {}
3267        pub mod RW {
3268            #[doc = "64"]
3269            pub const _64_CLOCKS: u32 = 0;
3270            #[doc = "128"]
3271            pub const _128_CLOCKS: u32 = 0x01;
3272            #[doc = "256"]
3273            pub const _256_CLOCKS: u32 = 0x02;
3274            #[doc = "512"]
3275            pub const _512_CLOCKS: u32 = 0x03;
3276        }
3277    }
3278}
3279#[doc = "Miscellaneous Register 2"]
3280pub mod MISC2_CLR {
3281    #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3282    pub mod REG0_BO_OFFSET {
3283        pub const offset: u32 = 0;
3284        pub const mask: u32 = 0x07 << offset;
3285        pub mod R {}
3286        pub mod W {}
3287        pub mod RW {
3288            #[doc = "Brownout offset = 0.100V"]
3289            pub const REG0_BO_OFFSET_4: u32 = 0x04;
3290            #[doc = "Brownout offset = 0.175V"]
3291            pub const REG0_BO_OFFSET_7: u32 = 0x07;
3292        }
3293    }
3294    #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
3295    pub mod REG0_BO_STATUS {
3296        pub const offset: u32 = 3;
3297        pub const mask: u32 = 0x01 << offset;
3298        pub mod R {}
3299        pub mod W {}
3300        pub mod RW {
3301            #[doc = "Brownout, supply is below target minus brownout offset."]
3302            pub const REG0_BO_STATUS_1: u32 = 0x01;
3303        }
3304    }
3305    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3306    pub mod REG0_ENABLE_BO {
3307        pub const offset: u32 = 5;
3308        pub const mask: u32 = 0x01 << offset;
3309        pub mod R {}
3310        pub mod W {}
3311        pub mod RW {}
3312    }
3313    #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
3314    pub mod REG0_OK {
3315        pub const offset: u32 = 6;
3316        pub const mask: u32 = 0x01 << offset;
3317        pub mod R {}
3318        pub mod W {}
3319        pub mod RW {}
3320    }
3321    #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
3322    pub mod PLL3_DISABLE {
3323        pub const offset: u32 = 7;
3324        pub const mask: u32 = 0x01 << offset;
3325        pub mod R {}
3326        pub mod W {}
3327        pub mod RW {
3328            #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
3329            pub const PLL3_DISABLE_0: u32 = 0;
3330            #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
3331            pub const PLL3_DISABLE_1: u32 = 0x01;
3332        }
3333    }
3334    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3335    pub mod REG1_BO_OFFSET {
3336        pub const offset: u32 = 8;
3337        pub const mask: u32 = 0x07 << offset;
3338        pub mod R {}
3339        pub mod W {}
3340        pub mod RW {
3341            #[doc = "Brownout offset = 0.100V"]
3342            pub const REG1_BO_OFFSET_4: u32 = 0x04;
3343            #[doc = "Brownout offset = 0.175V"]
3344            pub const REG1_BO_OFFSET_7: u32 = 0x07;
3345        }
3346    }
3347    #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
3348    pub mod REG1_BO_STATUS {
3349        pub const offset: u32 = 11;
3350        pub const mask: u32 = 0x01 << offset;
3351        pub mod R {}
3352        pub mod W {}
3353        pub mod RW {
3354            #[doc = "Brownout, supply is below target minus brownout offset."]
3355            pub const REG1_BO_STATUS_1: u32 = 0x01;
3356        }
3357    }
3358    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3359    pub mod REG1_ENABLE_BO {
3360        pub const offset: u32 = 13;
3361        pub const mask: u32 = 0x01 << offset;
3362        pub mod R {}
3363        pub mod W {}
3364        pub mod RW {}
3365    }
3366    #[doc = "GPU supply Not related to CCM. See Power Management Unit (PMU)"]
3367    pub mod REG1_OK {
3368        pub const offset: u32 = 14;
3369        pub const mask: u32 = 0x01 << offset;
3370        pub mod R {}
3371        pub mod W {}
3372        pub mod RW {}
3373    }
3374    #[doc = "LSB of Post-divider for Audio PLL"]
3375    pub mod AUDIO_DIV_LSB {
3376        pub const offset: u32 = 15;
3377        pub const mask: u32 = 0x01 << offset;
3378        pub mod R {}
3379        pub mod W {}
3380        pub mod RW {
3381            #[doc = "divide by 1 (Default)"]
3382            pub const AUDIO_DIV_LSB_0: u32 = 0;
3383            #[doc = "divide by 2"]
3384            pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3385        }
3386    }
3387    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3388    pub mod REG2_BO_OFFSET {
3389        pub const offset: u32 = 16;
3390        pub const mask: u32 = 0x07 << offset;
3391        pub mod R {}
3392        pub mod W {}
3393        pub mod RW {
3394            #[doc = "Brownout offset = 0.100V"]
3395            pub const REG2_BO_OFFSET_4: u32 = 0x04;
3396            #[doc = "Brownout offset = 0.175V"]
3397            pub const REG2_BO_OFFSET_7: u32 = 0x07;
3398        }
3399    }
3400    #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
3401    pub mod REG2_BO_STATUS {
3402        pub const offset: u32 = 19;
3403        pub const mask: u32 = 0x01 << offset;
3404        pub mod R {}
3405        pub mod W {}
3406        pub mod RW {}
3407    }
3408    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3409    pub mod REG2_ENABLE_BO {
3410        pub const offset: u32 = 21;
3411        pub const mask: u32 = 0x01 << offset;
3412        pub mod R {}
3413        pub mod W {}
3414        pub mod RW {}
3415    }
3416    #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3417    pub mod REG2_OK {
3418        pub const offset: u32 = 22;
3419        pub const mask: u32 = 0x01 << offset;
3420        pub mod R {}
3421        pub mod W {}
3422        pub mod RW {}
3423    }
3424    #[doc = "MSB of Post-divider for Audio PLL"]
3425    pub mod AUDIO_DIV_MSB {
3426        pub const offset: u32 = 23;
3427        pub const mask: u32 = 0x01 << offset;
3428        pub mod R {}
3429        pub mod W {}
3430        pub mod RW {
3431            #[doc = "divide by 1 (Default)"]
3432            pub const AUDIO_DIV_MSB_0: u32 = 0;
3433            #[doc = "divide by 2"]
3434            pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3435        }
3436    }
3437    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3438    pub mod REG0_STEP_TIME {
3439        pub const offset: u32 = 24;
3440        pub const mask: u32 = 0x03 << offset;
3441        pub mod R {}
3442        pub mod W {}
3443        pub mod RW {
3444            #[doc = "64"]
3445            pub const _64_CLOCKS: u32 = 0;
3446            #[doc = "128"]
3447            pub const _128_CLOCKS: u32 = 0x01;
3448            #[doc = "256"]
3449            pub const _256_CLOCKS: u32 = 0x02;
3450            #[doc = "512"]
3451            pub const _512_CLOCKS: u32 = 0x03;
3452        }
3453    }
3454    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3455    pub mod REG1_STEP_TIME {
3456        pub const offset: u32 = 26;
3457        pub const mask: u32 = 0x03 << offset;
3458        pub mod R {}
3459        pub mod W {}
3460        pub mod RW {
3461            #[doc = "64"]
3462            pub const _64_CLOCKS: u32 = 0;
3463            #[doc = "128"]
3464            pub const _128_CLOCKS: u32 = 0x01;
3465            #[doc = "256"]
3466            pub const _256_CLOCKS: u32 = 0x02;
3467            #[doc = "512"]
3468            pub const _512_CLOCKS: u32 = 0x03;
3469        }
3470    }
3471    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3472    pub mod REG2_STEP_TIME {
3473        pub const offset: u32 = 28;
3474        pub const mask: u32 = 0x03 << offset;
3475        pub mod R {}
3476        pub mod W {}
3477        pub mod RW {
3478            #[doc = "64"]
3479            pub const _64_CLOCKS: u32 = 0;
3480            #[doc = "128"]
3481            pub const _128_CLOCKS: u32 = 0x01;
3482            #[doc = "256"]
3483            pub const _256_CLOCKS: u32 = 0x02;
3484            #[doc = "512"]
3485            pub const _512_CLOCKS: u32 = 0x03;
3486        }
3487    }
3488}
3489#[doc = "Miscellaneous Register 2"]
3490pub mod MISC2_TOG {
3491    #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3492    pub mod REG0_BO_OFFSET {
3493        pub const offset: u32 = 0;
3494        pub const mask: u32 = 0x07 << offset;
3495        pub mod R {}
3496        pub mod W {}
3497        pub mod RW {
3498            #[doc = "Brownout offset = 0.100V"]
3499            pub const REG0_BO_OFFSET_4: u32 = 0x04;
3500            #[doc = "Brownout offset = 0.175V"]
3501            pub const REG0_BO_OFFSET_7: u32 = 0x07;
3502        }
3503    }
3504    #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
3505    pub mod REG0_BO_STATUS {
3506        pub const offset: u32 = 3;
3507        pub const mask: u32 = 0x01 << offset;
3508        pub mod R {}
3509        pub mod W {}
3510        pub mod RW {
3511            #[doc = "Brownout, supply is below target minus brownout offset."]
3512            pub const REG0_BO_STATUS_1: u32 = 0x01;
3513        }
3514    }
3515    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3516    pub mod REG0_ENABLE_BO {
3517        pub const offset: u32 = 5;
3518        pub const mask: u32 = 0x01 << offset;
3519        pub mod R {}
3520        pub mod W {}
3521        pub mod RW {}
3522    }
3523    #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
3524    pub mod REG0_OK {
3525        pub const offset: u32 = 6;
3526        pub const mask: u32 = 0x01 << offset;
3527        pub mod R {}
3528        pub mod W {}
3529        pub mod RW {}
3530    }
3531    #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
3532    pub mod PLL3_DISABLE {
3533        pub const offset: u32 = 7;
3534        pub const mask: u32 = 0x01 << offset;
3535        pub mod R {}
3536        pub mod W {}
3537        pub mod RW {
3538            #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
3539            pub const PLL3_DISABLE_0: u32 = 0;
3540            #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
3541            pub const PLL3_DISABLE_1: u32 = 0x01;
3542        }
3543    }
3544    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3545    pub mod REG1_BO_OFFSET {
3546        pub const offset: u32 = 8;
3547        pub const mask: u32 = 0x07 << offset;
3548        pub mod R {}
3549        pub mod W {}
3550        pub mod RW {
3551            #[doc = "Brownout offset = 0.100V"]
3552            pub const REG1_BO_OFFSET_4: u32 = 0x04;
3553            #[doc = "Brownout offset = 0.175V"]
3554            pub const REG1_BO_OFFSET_7: u32 = 0x07;
3555        }
3556    }
3557    #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
3558    pub mod REG1_BO_STATUS {
3559        pub const offset: u32 = 11;
3560        pub const mask: u32 = 0x01 << offset;
3561        pub mod R {}
3562        pub mod W {}
3563        pub mod RW {
3564            #[doc = "Brownout, supply is below target minus brownout offset."]
3565            pub const REG1_BO_STATUS_1: u32 = 0x01;
3566        }
3567    }
3568    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3569    pub mod REG1_ENABLE_BO {
3570        pub const offset: u32 = 13;
3571        pub const mask: u32 = 0x01 << offset;
3572        pub mod R {}
3573        pub mod W {}
3574        pub mod RW {}
3575    }
3576    #[doc = "GPU supply Not related to CCM. See Power Management Unit (PMU)"]
3577    pub mod REG1_OK {
3578        pub const offset: u32 = 14;
3579        pub const mask: u32 = 0x01 << offset;
3580        pub mod R {}
3581        pub mod W {}
3582        pub mod RW {}
3583    }
3584    #[doc = "LSB of Post-divider for Audio PLL"]
3585    pub mod AUDIO_DIV_LSB {
3586        pub const offset: u32 = 15;
3587        pub const mask: u32 = 0x01 << offset;
3588        pub mod R {}
3589        pub mod W {}
3590        pub mod RW {
3591            #[doc = "divide by 1 (Default)"]
3592            pub const AUDIO_DIV_LSB_0: u32 = 0;
3593            #[doc = "divide by 2"]
3594            pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3595        }
3596    }
3597    #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3598    pub mod REG2_BO_OFFSET {
3599        pub const offset: u32 = 16;
3600        pub const mask: u32 = 0x07 << offset;
3601        pub mod R {}
3602        pub mod W {}
3603        pub mod RW {
3604            #[doc = "Brownout offset = 0.100V"]
3605            pub const REG2_BO_OFFSET_4: u32 = 0x04;
3606            #[doc = "Brownout offset = 0.175V"]
3607            pub const REG2_BO_OFFSET_7: u32 = 0x07;
3608        }
3609    }
3610    #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
3611    pub mod REG2_BO_STATUS {
3612        pub const offset: u32 = 19;
3613        pub const mask: u32 = 0x01 << offset;
3614        pub mod R {}
3615        pub mod W {}
3616        pub mod RW {}
3617    }
3618    #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
3619    pub mod REG2_ENABLE_BO {
3620        pub const offset: u32 = 21;
3621        pub const mask: u32 = 0x01 << offset;
3622        pub mod R {}
3623        pub mod W {}
3624        pub mod RW {}
3625    }
3626    #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3627    pub mod REG2_OK {
3628        pub const offset: u32 = 22;
3629        pub const mask: u32 = 0x01 << offset;
3630        pub mod R {}
3631        pub mod W {}
3632        pub mod RW {}
3633    }
3634    #[doc = "MSB of Post-divider for Audio PLL"]
3635    pub mod AUDIO_DIV_MSB {
3636        pub const offset: u32 = 23;
3637        pub const mask: u32 = 0x01 << offset;
3638        pub mod R {}
3639        pub mod W {}
3640        pub mod RW {
3641            #[doc = "divide by 1 (Default)"]
3642            pub const AUDIO_DIV_MSB_0: u32 = 0;
3643            #[doc = "divide by 2"]
3644            pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3645        }
3646    }
3647    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3648    pub mod REG0_STEP_TIME {
3649        pub const offset: u32 = 24;
3650        pub const mask: u32 = 0x03 << offset;
3651        pub mod R {}
3652        pub mod W {}
3653        pub mod RW {
3654            #[doc = "64"]
3655            pub const _64_CLOCKS: u32 = 0;
3656            #[doc = "128"]
3657            pub const _128_CLOCKS: u32 = 0x01;
3658            #[doc = "256"]
3659            pub const _256_CLOCKS: u32 = 0x02;
3660            #[doc = "512"]
3661            pub const _512_CLOCKS: u32 = 0x03;
3662        }
3663    }
3664    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3665    pub mod REG1_STEP_TIME {
3666        pub const offset: u32 = 26;
3667        pub const mask: u32 = 0x03 << offset;
3668        pub mod R {}
3669        pub mod W {}
3670        pub mod RW {
3671            #[doc = "64"]
3672            pub const _64_CLOCKS: u32 = 0;
3673            #[doc = "128"]
3674            pub const _128_CLOCKS: u32 = 0x01;
3675            #[doc = "256"]
3676            pub const _256_CLOCKS: u32 = 0x02;
3677            #[doc = "512"]
3678            pub const _512_CLOCKS: u32 = 0x03;
3679        }
3680    }
3681    #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
3682    pub mod REG2_STEP_TIME {
3683        pub const offset: u32 = 28;
3684        pub const mask: u32 = 0x03 << offset;
3685        pub mod R {}
3686        pub mod W {}
3687        pub mod RW {
3688            #[doc = "64"]
3689            pub const _64_CLOCKS: u32 = 0;
3690            #[doc = "128"]
3691            pub const _128_CLOCKS: u32 = 0x01;
3692            #[doc = "256"]
3693            pub const _256_CLOCKS: u32 = 0x02;
3694            #[doc = "512"]
3695            pub const _512_CLOCKS: u32 = 0x03;
3696        }
3697    }
3698}
imxrt_ral/blocks/imxrt1011/ccm_analog.rs

imxrt_ral/blocks/imxrt1011/
ccm_analog.rs
