rp2040_pac/clocks/
clk_gpout1_ctrl.rs

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1#[doc = "Register `CLK_GPOUT1_CTRL` reader"]
2pub type R = crate::R<CLK_GPOUT1_CTRL_SPEC>;
3#[doc = "Register `CLK_GPOUT1_CTRL` writer"]
4pub type W = crate::W<CLK_GPOUT1_CTRL_SPEC>;
5#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
6pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
7#[doc = "Selects the auxiliary clock source, will glitch when switching  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum AUXSRC_A {
13    #[doc = "0: `0`"]
14    CLKSRC_PLL_SYS = 0,
15    #[doc = "1: `1`"]
16    CLKSRC_GPIN0 = 1,
17    #[doc = "2: `10`"]
18    CLKSRC_GPIN1 = 2,
19    #[doc = "3: `11`"]
20    CLKSRC_PLL_USB = 3,
21    #[doc = "4: `100`"]
22    ROSC_CLKSRC = 4,
23    #[doc = "5: `101`"]
24    XOSC_CLKSRC = 5,
25    #[doc = "6: `110`"]
26    CLK_SYS = 6,
27    #[doc = "7: `111`"]
28    CLK_USB = 7,
29    #[doc = "8: `1000`"]
30    CLK_ADC = 8,
31    #[doc = "9: `1001`"]
32    CLK_RTC = 9,
33    #[doc = "10: `1010`"]
34    CLK_REF = 10,
35}
36impl From<AUXSRC_A> for u8 {
37    #[inline(always)]
38    fn from(variant: AUXSRC_A) -> Self {
39        variant as _
40    }
41}
42impl crate::FieldSpec for AUXSRC_A {
43    type Ux = u8;
44}
45impl AUXSRC_R {
46    #[doc = "Get enumerated values variant"]
47    #[inline(always)]
48    pub const fn variant(&self) -> Option<AUXSRC_A> {
49        match self.bits {
50            0 => Some(AUXSRC_A::CLKSRC_PLL_SYS),
51            1 => Some(AUXSRC_A::CLKSRC_GPIN0),
52            2 => Some(AUXSRC_A::CLKSRC_GPIN1),
53            3 => Some(AUXSRC_A::CLKSRC_PLL_USB),
54            4 => Some(AUXSRC_A::ROSC_CLKSRC),
55            5 => Some(AUXSRC_A::XOSC_CLKSRC),
56            6 => Some(AUXSRC_A::CLK_SYS),
57            7 => Some(AUXSRC_A::CLK_USB),
58            8 => Some(AUXSRC_A::CLK_ADC),
59            9 => Some(AUXSRC_A::CLK_RTC),
60            10 => Some(AUXSRC_A::CLK_REF),
61            _ => None,
62        }
63    }
64    #[doc = "`0`"]
65    #[inline(always)]
66    pub fn is_clksrc_pll_sys(&self) -> bool {
67        *self == AUXSRC_A::CLKSRC_PLL_SYS
68    }
69    #[doc = "`1`"]
70    #[inline(always)]
71    pub fn is_clksrc_gpin0(&self) -> bool {
72        *self == AUXSRC_A::CLKSRC_GPIN0
73    }
74    #[doc = "`10`"]
75    #[inline(always)]
76    pub fn is_clksrc_gpin1(&self) -> bool {
77        *self == AUXSRC_A::CLKSRC_GPIN1
78    }
79    #[doc = "`11`"]
80    #[inline(always)]
81    pub fn is_clksrc_pll_usb(&self) -> bool {
82        *self == AUXSRC_A::CLKSRC_PLL_USB
83    }
84    #[doc = "`100`"]
85    #[inline(always)]
86    pub fn is_rosc_clksrc(&self) -> bool {
87        *self == AUXSRC_A::ROSC_CLKSRC
88    }
89    #[doc = "`101`"]
90    #[inline(always)]
91    pub fn is_xosc_clksrc(&self) -> bool {
92        *self == AUXSRC_A::XOSC_CLKSRC
93    }
94    #[doc = "`110`"]
95    #[inline(always)]
96    pub fn is_clk_sys(&self) -> bool {
97        *self == AUXSRC_A::CLK_SYS
98    }
99    #[doc = "`111`"]
100    #[inline(always)]
101    pub fn is_clk_usb(&self) -> bool {
102        *self == AUXSRC_A::CLK_USB
103    }
104    #[doc = "`1000`"]
105    #[inline(always)]
106    pub fn is_clk_adc(&self) -> bool {
107        *self == AUXSRC_A::CLK_ADC
108    }
109    #[doc = "`1001`"]
110    #[inline(always)]
111    pub fn is_clk_rtc(&self) -> bool {
112        *self == AUXSRC_A::CLK_RTC
113    }
114    #[doc = "`1010`"]
115    #[inline(always)]
116    pub fn is_clk_ref(&self) -> bool {
117        *self == AUXSRC_A::CLK_REF
118    }
119}
120#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"]
121pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, AUXSRC_A>;
122impl<'a, REG> AUXSRC_W<'a, REG>
123where
124    REG: crate::Writable + crate::RegisterSpec,
125    REG::Ux: From<u8>,
126{
127    #[doc = "`0`"]
128    #[inline(always)]
129    pub fn clksrc_pll_sys(self) -> &'a mut crate::W<REG> {
130        self.variant(AUXSRC_A::CLKSRC_PLL_SYS)
131    }
132    #[doc = "`1`"]
133    #[inline(always)]
134    pub fn clksrc_gpin0(self) -> &'a mut crate::W<REG> {
135        self.variant(AUXSRC_A::CLKSRC_GPIN0)
136    }
137    #[doc = "`10`"]
138    #[inline(always)]
139    pub fn clksrc_gpin1(self) -> &'a mut crate::W<REG> {
140        self.variant(AUXSRC_A::CLKSRC_GPIN1)
141    }
142    #[doc = "`11`"]
143    #[inline(always)]
144    pub fn clksrc_pll_usb(self) -> &'a mut crate::W<REG> {
145        self.variant(AUXSRC_A::CLKSRC_PLL_USB)
146    }
147    #[doc = "`100`"]
148    #[inline(always)]
149    pub fn rosc_clksrc(self) -> &'a mut crate::W<REG> {
150        self.variant(AUXSRC_A::ROSC_CLKSRC)
151    }
152    #[doc = "`101`"]
153    #[inline(always)]
154    pub fn xosc_clksrc(self) -> &'a mut crate::W<REG> {
155        self.variant(AUXSRC_A::XOSC_CLKSRC)
156    }
157    #[doc = "`110`"]
158    #[inline(always)]
159    pub fn clk_sys(self) -> &'a mut crate::W<REG> {
160        self.variant(AUXSRC_A::CLK_SYS)
161    }
162    #[doc = "`111`"]
163    #[inline(always)]
164    pub fn clk_usb(self) -> &'a mut crate::W<REG> {
165        self.variant(AUXSRC_A::CLK_USB)
166    }
167    #[doc = "`1000`"]
168    #[inline(always)]
169    pub fn clk_adc(self) -> &'a mut crate::W<REG> {
170        self.variant(AUXSRC_A::CLK_ADC)
171    }
172    #[doc = "`1001`"]
173    #[inline(always)]
174    pub fn clk_rtc(self) -> &'a mut crate::W<REG> {
175        self.variant(AUXSRC_A::CLK_RTC)
176    }
177    #[doc = "`1010`"]
178    #[inline(always)]
179    pub fn clk_ref(self) -> &'a mut crate::W<REG> {
180        self.variant(AUXSRC_A::CLK_REF)
181    }
182}
183#[doc = "Field `KILL` reader - Asynchronously kills the clock generator"]
184pub type KILL_R = crate::BitReader;
185#[doc = "Field `KILL` writer - Asynchronously kills the clock generator"]
186pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>;
187#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"]
188pub type ENABLE_R = crate::BitReader;
189#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"]
190pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
191#[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"]
192pub type DC50_R = crate::BitReader;
193#[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"]
194pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>;
195#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock  
196 This must be set before the clock is enabled to have any effect"]
197pub type PHASE_R = crate::FieldReader;
198#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock  
199 This must be set before the clock is enabled to have any effect"]
200pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
201#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
202 This can be done at any time"]
203pub type NUDGE_R = crate::BitReader;
204#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
205 This can be done at any time"]
206pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
207impl R {
208    #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"]
209    #[inline(always)]
210    pub fn auxsrc(&self) -> AUXSRC_R {
211        AUXSRC_R::new(((self.bits >> 5) & 0x0f) as u8)
212    }
213    #[doc = "Bit 10 - Asynchronously kills the clock generator"]
214    #[inline(always)]
215    pub fn kill(&self) -> KILL_R {
216        KILL_R::new(((self.bits >> 10) & 1) != 0)
217    }
218    #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
219    #[inline(always)]
220    pub fn enable(&self) -> ENABLE_R {
221        ENABLE_R::new(((self.bits >> 11) & 1) != 0)
222    }
223    #[doc = "Bit 12 - Enables duty cycle correction for odd divisors"]
224    #[inline(always)]
225    pub fn dc50(&self) -> DC50_R {
226        DC50_R::new(((self.bits >> 12) & 1) != 0)
227    }
228    #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock  
229 This must be set before the clock is enabled to have any effect"]
230    #[inline(always)]
231    pub fn phase(&self) -> PHASE_R {
232        PHASE_R::new(((self.bits >> 16) & 3) as u8)
233    }
234    #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
235 This can be done at any time"]
236    #[inline(always)]
237    pub fn nudge(&self) -> NUDGE_R {
238        NUDGE_R::new(((self.bits >> 20) & 1) != 0)
239    }
240}
241impl W {
242    #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"]
243    #[inline(always)]
244    #[must_use]
245    pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_GPOUT1_CTRL_SPEC> {
246        AUXSRC_W::new(self, 5)
247    }
248    #[doc = "Bit 10 - Asynchronously kills the clock generator"]
249    #[inline(always)]
250    #[must_use]
251    pub fn kill(&mut self) -> KILL_W<CLK_GPOUT1_CTRL_SPEC> {
252        KILL_W::new(self, 10)
253    }
254    #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
255    #[inline(always)]
256    #[must_use]
257    pub fn enable(&mut self) -> ENABLE_W<CLK_GPOUT1_CTRL_SPEC> {
258        ENABLE_W::new(self, 11)
259    }
260    #[doc = "Bit 12 - Enables duty cycle correction for odd divisors"]
261    #[inline(always)]
262    #[must_use]
263    pub fn dc50(&mut self) -> DC50_W<CLK_GPOUT1_CTRL_SPEC> {
264        DC50_W::new(self, 12)
265    }
266    #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock  
267 This must be set before the clock is enabled to have any effect"]
268    #[inline(always)]
269    #[must_use]
270    pub fn phase(&mut self) -> PHASE_W<CLK_GPOUT1_CTRL_SPEC> {
271        PHASE_W::new(self, 16)
272    }
273    #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
274 This can be done at any time"]
275    #[inline(always)]
276    #[must_use]
277    pub fn nudge(&mut self) -> NUDGE_W<CLK_GPOUT1_CTRL_SPEC> {
278        NUDGE_W::new(self, 20)
279    }
280    #[doc = r" Writes raw bits to the register."]
281    #[doc = r""]
282    #[doc = r" # Safety"]
283    #[doc = r""]
284    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
285    #[inline(always)]
286    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
287        self.bits = bits;
288        self
289    }
290}
291#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
292
293You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
294pub struct CLK_GPOUT1_CTRL_SPEC;
295impl crate::RegisterSpec for CLK_GPOUT1_CTRL_SPEC {
296    type Ux = u32;
297}
298#[doc = "`read()` method returns [`clk_gpout1_ctrl::R`](R) reader structure"]
299impl crate::Readable for CLK_GPOUT1_CTRL_SPEC {}
300#[doc = "`write(|w| ..)` method takes [`clk_gpout1_ctrl::W`](W) writer structure"]
301impl crate::Writable for CLK_GPOUT1_CTRL_SPEC {
302    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
303    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
304}
305#[doc = "`reset()` method sets CLK_GPOUT1_CTRL to value 0"]
306impl crate::Resettable for CLK_GPOUT1_CTRL_SPEC {
307    const RESET_VALUE: u32 = 0;
308}
rp2040_pac/clocks/clk_gpout1_ctrl.rs

rp2040_pac/clocks/
clk_gpout1_ctrl.rs
