1#[doc = "Register `IC_RAW_INTR_STAT` reader"]
2pub type R = crate::R<IC_RAW_INTR_STAT_SPEC>;
3#[doc = "Field `RX_UNDER` reader - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
4
5 Reset value: 0x0"]
6pub type RX_UNDER_R = crate::BitReader<RX_UNDER_A>;
7#[doc = "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
8
9 Reset value: 0x0
10
11Value on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum RX_UNDER_A {
14 #[doc = "0: RX_UNDER interrupt is inactive"]
15 INACTIVE = 0,
16 #[doc = "1: RX_UNDER interrupt is active"]
17 ACTIVE = 1,
18}
19impl From<RX_UNDER_A> for bool {
20 #[inline(always)]
21 fn from(variant: RX_UNDER_A) -> Self {
22 variant as u8 != 0
23 }
24}
25impl RX_UNDER_R {
26 #[doc = "Get enumerated values variant"]
27 #[inline(always)]
28 pub const fn variant(&self) -> RX_UNDER_A {
29 match self.bits {
30 false => RX_UNDER_A::INACTIVE,
31 true => RX_UNDER_A::ACTIVE,
32 }
33 }
34 #[doc = "RX_UNDER interrupt is inactive"]
35 #[inline(always)]
36 pub fn is_inactive(&self) -> bool {
37 *self == RX_UNDER_A::INACTIVE
38 }
39 #[doc = "RX_UNDER interrupt is active"]
40 #[inline(always)]
41 pub fn is_active(&self) -> bool {
42 *self == RX_UNDER_A::ACTIVE
43 }
44}
45#[doc = "Field `RX_OVER` reader - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
46
47 Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.
48
49 Reset value: 0x0"]
50pub type RX_OVER_R = crate::BitReader<RX_OVER_A>;
51#[doc = "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
52
53 Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.
54
55 Reset value: 0x0
56
57Value on reset: 0"]
58#[derive(Clone, Copy, Debug, PartialEq, Eq)]
59pub enum RX_OVER_A {
60 #[doc = "0: RX_OVER interrupt is inactive"]
61 INACTIVE = 0,
62 #[doc = "1: RX_OVER interrupt is active"]
63 ACTIVE = 1,
64}
65impl From<RX_OVER_A> for bool {
66 #[inline(always)]
67 fn from(variant: RX_OVER_A) -> Self {
68 variant as u8 != 0
69 }
70}
71impl RX_OVER_R {
72 #[doc = "Get enumerated values variant"]
73 #[inline(always)]
74 pub const fn variant(&self) -> RX_OVER_A {
75 match self.bits {
76 false => RX_OVER_A::INACTIVE,
77 true => RX_OVER_A::ACTIVE,
78 }
79 }
80 #[doc = "RX_OVER interrupt is inactive"]
81 #[inline(always)]
82 pub fn is_inactive(&self) -> bool {
83 *self == RX_OVER_A::INACTIVE
84 }
85 #[doc = "RX_OVER interrupt is active"]
86 #[inline(always)]
87 pub fn is_active(&self) -> bool {
88 *self == RX_OVER_A::ACTIVE
89 }
90}
91#[doc = "Field `RX_FULL` reader - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
92
93 Reset value: 0x0"]
94pub type RX_FULL_R = crate::BitReader<RX_FULL_A>;
95#[doc = "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
96
97 Reset value: 0x0
98
99Value on reset: 0"]
100#[derive(Clone, Copy, Debug, PartialEq, Eq)]
101pub enum RX_FULL_A {
102 #[doc = "0: RX_FULL interrupt is inactive"]
103 INACTIVE = 0,
104 #[doc = "1: RX_FULL interrupt is active"]
105 ACTIVE = 1,
106}
107impl From<RX_FULL_A> for bool {
108 #[inline(always)]
109 fn from(variant: RX_FULL_A) -> Self {
110 variant as u8 != 0
111 }
112}
113impl RX_FULL_R {
114 #[doc = "Get enumerated values variant"]
115 #[inline(always)]
116 pub const fn variant(&self) -> RX_FULL_A {
117 match self.bits {
118 false => RX_FULL_A::INACTIVE,
119 true => RX_FULL_A::ACTIVE,
120 }
121 }
122 #[doc = "RX_FULL interrupt is inactive"]
123 #[inline(always)]
124 pub fn is_inactive(&self) -> bool {
125 *self == RX_FULL_A::INACTIVE
126 }
127 #[doc = "RX_FULL interrupt is active"]
128 #[inline(always)]
129 pub fn is_active(&self) -> bool {
130 *self == RX_FULL_A::ACTIVE
131 }
132}
133#[doc = "Field `TX_OVER` reader - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
134
135 Reset value: 0x0"]
136pub type TX_OVER_R = crate::BitReader<TX_OVER_A>;
137#[doc = "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
138
139 Reset value: 0x0
140
141Value on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum TX_OVER_A {
144 #[doc = "0: TX_OVER interrupt is inactive"]
145 INACTIVE = 0,
146 #[doc = "1: TX_OVER interrupt is active"]
147 ACTIVE = 1,
148}
149impl From<TX_OVER_A> for bool {
150 #[inline(always)]
151 fn from(variant: TX_OVER_A) -> Self {
152 variant as u8 != 0
153 }
154}
155impl TX_OVER_R {
156 #[doc = "Get enumerated values variant"]
157 #[inline(always)]
158 pub const fn variant(&self) -> TX_OVER_A {
159 match self.bits {
160 false => TX_OVER_A::INACTIVE,
161 true => TX_OVER_A::ACTIVE,
162 }
163 }
164 #[doc = "TX_OVER interrupt is inactive"]
165 #[inline(always)]
166 pub fn is_inactive(&self) -> bool {
167 *self == TX_OVER_A::INACTIVE
168 }
169 #[doc = "TX_OVER interrupt is active"]
170 #[inline(always)]
171 pub fn is_active(&self) -> bool {
172 *self == TX_OVER_A::ACTIVE
173 }
174}
175#[doc = "Field `TX_EMPTY` reader - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\]
176is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
177
178 Reset value: 0x0."]
179pub type TX_EMPTY_R = crate::BitReader<TX_EMPTY_A>;
180#[doc = "The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\]
181is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
182
183 Reset value: 0x0.
184
185Value on reset: 0"]
186#[derive(Clone, Copy, Debug, PartialEq, Eq)]
187pub enum TX_EMPTY_A {
188 #[doc = "0: TX_EMPTY interrupt is inactive"]
189 INACTIVE = 0,
190 #[doc = "1: TX_EMPTY interrupt is active"]
191 ACTIVE = 1,
192}
193impl From<TX_EMPTY_A> for bool {
194 #[inline(always)]
195 fn from(variant: TX_EMPTY_A) -> Self {
196 variant as u8 != 0
197 }
198}
199impl TX_EMPTY_R {
200 #[doc = "Get enumerated values variant"]
201 #[inline(always)]
202 pub const fn variant(&self) -> TX_EMPTY_A {
203 match self.bits {
204 false => TX_EMPTY_A::INACTIVE,
205 true => TX_EMPTY_A::ACTIVE,
206 }
207 }
208 #[doc = "TX_EMPTY interrupt is inactive"]
209 #[inline(always)]
210 pub fn is_inactive(&self) -> bool {
211 *self == TX_EMPTY_A::INACTIVE
212 }
213 #[doc = "TX_EMPTY interrupt is active"]
214 #[inline(always)]
215 pub fn is_active(&self) -> bool {
216 *self == TX_EMPTY_A::ACTIVE
217 }
218}
219#[doc = "Field `RD_REQ` reader - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.
220
221 Reset value: 0x0"]
222pub type RD_REQ_R = crate::BitReader<RD_REQ_A>;
223#[doc = "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.
224
225 Reset value: 0x0
226
227Value on reset: 0"]
228#[derive(Clone, Copy, Debug, PartialEq, Eq)]
229pub enum RD_REQ_A {
230 #[doc = "0: RD_REQ interrupt is inactive"]
231 INACTIVE = 0,
232 #[doc = "1: RD_REQ interrupt is active"]
233 ACTIVE = 1,
234}
235impl From<RD_REQ_A> for bool {
236 #[inline(always)]
237 fn from(variant: RD_REQ_A) -> Self {
238 variant as u8 != 0
239 }
240}
241impl RD_REQ_R {
242 #[doc = "Get enumerated values variant"]
243 #[inline(always)]
244 pub const fn variant(&self) -> RD_REQ_A {
245 match self.bits {
246 false => RD_REQ_A::INACTIVE,
247 true => RD_REQ_A::ACTIVE,
248 }
249 }
250 #[doc = "RD_REQ interrupt is inactive"]
251 #[inline(always)]
252 pub fn is_inactive(&self) -> bool {
253 *self == RD_REQ_A::INACTIVE
254 }
255 #[doc = "RD_REQ interrupt is active"]
256 #[inline(always)]
257 pub fn is_active(&self) -> bool {
258 *self == RD_REQ_A::ACTIVE
259 }
260}
261#[doc = "Field `TX_ABRT` reader - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
262
263 Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.
264
265 Reset value: 0x0"]
266pub type TX_ABRT_R = crate::BitReader<TX_ABRT_A>;
267#[doc = "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
268
269 Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.
270
271 Reset value: 0x0
272
273Value on reset: 0"]
274#[derive(Clone, Copy, Debug, PartialEq, Eq)]
275pub enum TX_ABRT_A {
276 #[doc = "0: TX_ABRT interrupt is inactive"]
277 INACTIVE = 0,
278 #[doc = "1: TX_ABRT interrupt is active"]
279 ACTIVE = 1,
280}
281impl From<TX_ABRT_A> for bool {
282 #[inline(always)]
283 fn from(variant: TX_ABRT_A) -> Self {
284 variant as u8 != 0
285 }
286}
287impl TX_ABRT_R {
288 #[doc = "Get enumerated values variant"]
289 #[inline(always)]
290 pub const fn variant(&self) -> TX_ABRT_A {
291 match self.bits {
292 false => TX_ABRT_A::INACTIVE,
293 true => TX_ABRT_A::ACTIVE,
294 }
295 }
296 #[doc = "TX_ABRT interrupt is inactive"]
297 #[inline(always)]
298 pub fn is_inactive(&self) -> bool {
299 *self == TX_ABRT_A::INACTIVE
300 }
301 #[doc = "TX_ABRT interrupt is active"]
302 #[inline(always)]
303 pub fn is_active(&self) -> bool {
304 *self == TX_ABRT_A::ACTIVE
305 }
306}
307#[doc = "Field `RX_DONE` reader - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
308
309 Reset value: 0x0"]
310pub type RX_DONE_R = crate::BitReader<RX_DONE_A>;
311#[doc = "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
312
313 Reset value: 0x0
314
315Value on reset: 0"]
316#[derive(Clone, Copy, Debug, PartialEq, Eq)]
317pub enum RX_DONE_A {
318 #[doc = "0: RX_DONE interrupt is inactive"]
319 INACTIVE = 0,
320 #[doc = "1: RX_DONE interrupt is active"]
321 ACTIVE = 1,
322}
323impl From<RX_DONE_A> for bool {
324 #[inline(always)]
325 fn from(variant: RX_DONE_A) -> Self {
326 variant as u8 != 0
327 }
328}
329impl RX_DONE_R {
330 #[doc = "Get enumerated values variant"]
331 #[inline(always)]
332 pub const fn variant(&self) -> RX_DONE_A {
333 match self.bits {
334 false => RX_DONE_A::INACTIVE,
335 true => RX_DONE_A::ACTIVE,
336 }
337 }
338 #[doc = "RX_DONE interrupt is inactive"]
339 #[inline(always)]
340 pub fn is_inactive(&self) -> bool {
341 *self == RX_DONE_A::INACTIVE
342 }
343 #[doc = "RX_DONE interrupt is active"]
344 #[inline(always)]
345 pub fn is_active(&self) -> bool {
346 *self == RX_DONE_A::ACTIVE
347 }
348}
349#[doc = "Field `ACTIVITY` reader - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
350
351 Reset value: 0x0"]
352pub type ACTIVITY_R = crate::BitReader<ACTIVITY_A>;
353#[doc = "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
354
355 Reset value: 0x0
356
357Value on reset: 0"]
358#[derive(Clone, Copy, Debug, PartialEq, Eq)]
359pub enum ACTIVITY_A {
360 #[doc = "0: RAW_INTR_ACTIVITY interrupt is inactive"]
361 INACTIVE = 0,
362 #[doc = "1: RAW_INTR_ACTIVITY interrupt is active"]
363 ACTIVE = 1,
364}
365impl From<ACTIVITY_A> for bool {
366 #[inline(always)]
367 fn from(variant: ACTIVITY_A) -> Self {
368 variant as u8 != 0
369 }
370}
371impl ACTIVITY_R {
372 #[doc = "Get enumerated values variant"]
373 #[inline(always)]
374 pub const fn variant(&self) -> ACTIVITY_A {
375 match self.bits {
376 false => ACTIVITY_A::INACTIVE,
377 true => ACTIVITY_A::ACTIVE,
378 }
379 }
380 #[doc = "RAW_INTR_ACTIVITY interrupt is inactive"]
381 #[inline(always)]
382 pub fn is_inactive(&self) -> bool {
383 *self == ACTIVITY_A::INACTIVE
384 }
385 #[doc = "RAW_INTR_ACTIVITY interrupt is active"]
386 #[inline(always)]
387 pub fn is_active(&self) -> bool {
388 *self == ACTIVITY_A::ACTIVE
389 }
390}
391#[doc = "Field `STOP_DET` reader - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
392
393 In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"]
394pub type STOP_DET_R = crate::BitReader<STOP_DET_A>;
395#[doc = "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
396
397 In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0
398
399Value on reset: 0"]
400#[derive(Clone, Copy, Debug, PartialEq, Eq)]
401pub enum STOP_DET_A {
402 #[doc = "0: STOP_DET interrupt is inactive"]
403 INACTIVE = 0,
404 #[doc = "1: STOP_DET interrupt is active"]
405 ACTIVE = 1,
406}
407impl From<STOP_DET_A> for bool {
408 #[inline(always)]
409 fn from(variant: STOP_DET_A) -> Self {
410 variant as u8 != 0
411 }
412}
413impl STOP_DET_R {
414 #[doc = "Get enumerated values variant"]
415 #[inline(always)]
416 pub const fn variant(&self) -> STOP_DET_A {
417 match self.bits {
418 false => STOP_DET_A::INACTIVE,
419 true => STOP_DET_A::ACTIVE,
420 }
421 }
422 #[doc = "STOP_DET interrupt is inactive"]
423 #[inline(always)]
424 pub fn is_inactive(&self) -> bool {
425 *self == STOP_DET_A::INACTIVE
426 }
427 #[doc = "STOP_DET interrupt is active"]
428 #[inline(always)]
429 pub fn is_active(&self) -> bool {
430 *self == STOP_DET_A::ACTIVE
431 }
432}
433#[doc = "Field `START_DET` reader - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
434
435 Reset value: 0x0"]
436pub type START_DET_R = crate::BitReader<START_DET_A>;
437#[doc = "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
438
439 Reset value: 0x0
440
441Value on reset: 0"]
442#[derive(Clone, Copy, Debug, PartialEq, Eq)]
443pub enum START_DET_A {
444 #[doc = "0: START_DET interrupt is inactive"]
445 INACTIVE = 0,
446 #[doc = "1: START_DET interrupt is active"]
447 ACTIVE = 1,
448}
449impl From<START_DET_A> for bool {
450 #[inline(always)]
451 fn from(variant: START_DET_A) -> Self {
452 variant as u8 != 0
453 }
454}
455impl START_DET_R {
456 #[doc = "Get enumerated values variant"]
457 #[inline(always)]
458 pub const fn variant(&self) -> START_DET_A {
459 match self.bits {
460 false => START_DET_A::INACTIVE,
461 true => START_DET_A::ACTIVE,
462 }
463 }
464 #[doc = "START_DET interrupt is inactive"]
465 #[inline(always)]
466 pub fn is_inactive(&self) -> bool {
467 *self == START_DET_A::INACTIVE
468 }
469 #[doc = "START_DET interrupt is active"]
470 #[inline(always)]
471 pub fn is_active(&self) -> bool {
472 *self == START_DET_A::ACTIVE
473 }
474}
475#[doc = "Field `GEN_CALL` reader - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.
476
477 Reset value: 0x0"]
478pub type GEN_CALL_R = crate::BitReader<GEN_CALL_A>;
479#[doc = "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.
480
481 Reset value: 0x0
482
483Value on reset: 0"]
484#[derive(Clone, Copy, Debug, PartialEq, Eq)]
485pub enum GEN_CALL_A {
486 #[doc = "0: GEN_CALL interrupt is inactive"]
487 INACTIVE = 0,
488 #[doc = "1: GEN_CALL interrupt is active"]
489 ACTIVE = 1,
490}
491impl From<GEN_CALL_A> for bool {
492 #[inline(always)]
493 fn from(variant: GEN_CALL_A) -> Self {
494 variant as u8 != 0
495 }
496}
497impl GEN_CALL_R {
498 #[doc = "Get enumerated values variant"]
499 #[inline(always)]
500 pub const fn variant(&self) -> GEN_CALL_A {
501 match self.bits {
502 false => GEN_CALL_A::INACTIVE,
503 true => GEN_CALL_A::ACTIVE,
504 }
505 }
506 #[doc = "GEN_CALL interrupt is inactive"]
507 #[inline(always)]
508 pub fn is_inactive(&self) -> bool {
509 *self == GEN_CALL_A::INACTIVE
510 }
511 #[doc = "GEN_CALL interrupt is active"]
512 #[inline(always)]
513 pub fn is_active(&self) -> bool {
514 *self == GEN_CALL_A::ACTIVE
515 }
516}
517#[doc = "Field `RESTART_DET` reader - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
518
519 Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.
520
521 Reset value: 0x0"]
522pub type RESTART_DET_R = crate::BitReader<RESTART_DET_A>;
523#[doc = "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
524
525 Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.
526
527 Reset value: 0x0
528
529Value on reset: 0"]
530#[derive(Clone, Copy, Debug, PartialEq, Eq)]
531pub enum RESTART_DET_A {
532 #[doc = "0: RESTART_DET interrupt is inactive"]
533 INACTIVE = 0,
534 #[doc = "1: RESTART_DET interrupt is active"]
535 ACTIVE = 1,
536}
537impl From<RESTART_DET_A> for bool {
538 #[inline(always)]
539 fn from(variant: RESTART_DET_A) -> Self {
540 variant as u8 != 0
541 }
542}
543impl RESTART_DET_R {
544 #[doc = "Get enumerated values variant"]
545 #[inline(always)]
546 pub const fn variant(&self) -> RESTART_DET_A {
547 match self.bits {
548 false => RESTART_DET_A::INACTIVE,
549 true => RESTART_DET_A::ACTIVE,
550 }
551 }
552 #[doc = "RESTART_DET interrupt is inactive"]
553 #[inline(always)]
554 pub fn is_inactive(&self) -> bool {
555 *self == RESTART_DET_A::INACTIVE
556 }
557 #[doc = "RESTART_DET interrupt is active"]
558 #[inline(always)]
559 pub fn is_active(&self) -> bool {
560 *self == RESTART_DET_A::ACTIVE
561 }
562}
563impl R {
564 #[doc = "Bit 0 - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
565
566 Reset value: 0x0"]
567 #[inline(always)]
568 pub fn rx_under(&self) -> RX_UNDER_R {
569 RX_UNDER_R::new((self.bits & 1) != 0)
570 }
571 #[doc = "Bit 1 - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
572
573 Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.
574
575 Reset value: 0x0"]
576 #[inline(always)]
577 pub fn rx_over(&self) -> RX_OVER_R {
578 RX_OVER_R::new(((self.bits >> 1) & 1) != 0)
579 }
580 #[doc = "Bit 2 - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
581
582 Reset value: 0x0"]
583 #[inline(always)]
584 pub fn rx_full(&self) -> RX_FULL_R {
585 RX_FULL_R::new(((self.bits >> 2) & 1) != 0)
586 }
587 #[doc = "Bit 3 - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
588
589 Reset value: 0x0"]
590 #[inline(always)]
591 pub fn tx_over(&self) -> TX_OVER_R {
592 TX_OVER_R::new(((self.bits >> 3) & 1) != 0)
593 }
594 #[doc = "Bit 4 - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\]
595is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
596
597 Reset value: 0x0."]
598 #[inline(always)]
599 pub fn tx_empty(&self) -> TX_EMPTY_R {
600 TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
601 }
602 #[doc = "Bit 5 - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.
603
604 Reset value: 0x0"]
605 #[inline(always)]
606 pub fn rd_req(&self) -> RD_REQ_R {
607 RD_REQ_R::new(((self.bits >> 5) & 1) != 0)
608 }
609 #[doc = "Bit 6 - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
610
611 Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.
612
613 Reset value: 0x0"]
614 #[inline(always)]
615 pub fn tx_abrt(&self) -> TX_ABRT_R {
616 TX_ABRT_R::new(((self.bits >> 6) & 1) != 0)
617 }
618 #[doc = "Bit 7 - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
619
620 Reset value: 0x0"]
621 #[inline(always)]
622 pub fn rx_done(&self) -> RX_DONE_R {
623 RX_DONE_R::new(((self.bits >> 7) & 1) != 0)
624 }
625 #[doc = "Bit 8 - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
626
627 Reset value: 0x0"]
628 #[inline(always)]
629 pub fn activity(&self) -> ACTIVITY_R {
630 ACTIVITY_R::new(((self.bits >> 8) & 1) != 0)
631 }
632 #[doc = "Bit 9 - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
633
634 In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"]
635 #[inline(always)]
636 pub fn stop_det(&self) -> STOP_DET_R {
637 STOP_DET_R::new(((self.bits >> 9) & 1) != 0)
638 }
639 #[doc = "Bit 10 - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
640
641 Reset value: 0x0"]
642 #[inline(always)]
643 pub fn start_det(&self) -> START_DET_R {
644 START_DET_R::new(((self.bits >> 10) & 1) != 0)
645 }
646 #[doc = "Bit 11 - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.
647
648 Reset value: 0x0"]
649 #[inline(always)]
650 pub fn gen_call(&self) -> GEN_CALL_R {
651 GEN_CALL_R::new(((self.bits >> 11) & 1) != 0)
652 }
653 #[doc = "Bit 12 - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
654
655 Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.
656
657 Reset value: 0x0"]
658 #[inline(always)]
659 pub fn restart_det(&self) -> RESTART_DET_R {
660 RESTART_DET_R::new(((self.bits >> 12) & 1) != 0)
661 }
662}
663#[doc = "I2C Raw Interrupt Status Register
664
665 Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.
666
667You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
668pub struct IC_RAW_INTR_STAT_SPEC;
669impl crate::RegisterSpec for IC_RAW_INTR_STAT_SPEC {
670 type Ux = u32;
671}
672#[doc = "`read()` method returns [`ic_raw_intr_stat::R`](R) reader structure"]
673impl crate::Readable for IC_RAW_INTR_STAT_SPEC {}
674#[doc = "`reset()` method sets IC_RAW_INTR_STAT to value 0"]
675impl crate::Resettable for IC_RAW_INTR_STAT_SPEC {
676 const RESET_VALUE: u32 = 0;
677}