rp2040_pac/clocks/
clk_gpout2_div.rs

Help
1#[doc = "Register `CLK_GPOUT2_DIV` reader"]
2pub type R = crate::R<CLK_GPOUT2_DIV_SPEC>;
3#[doc = "Register `CLK_GPOUT2_DIV` writer"]
4pub type W = crate::W<CLK_GPOUT2_DIV_SPEC>;
5#[doc = "Field `FRAC` reader - Fractional component of the divisor"]
6pub type FRAC_R = crate::FieldReader;
7#[doc = "Field `FRAC` writer - Fractional component of the divisor"]
8pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"]
10pub type INT_R = crate::FieldReader<u32>;
11#[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"]
12pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
13impl R {
14    #[doc = "Bits 0:7 - Fractional component of the divisor"]
15    #[inline(always)]
16    pub fn frac(&self) -> FRAC_R {
17        FRAC_R::new((self.bits & 0xff) as u8)
18    }
19    #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"]
20    #[inline(always)]
21    pub fn int(&self) -> INT_R {
22        INT_R::new((self.bits >> 8) & 0x00ff_ffff)
23    }
24}
25impl W {
26    #[doc = "Bits 0:7 - Fractional component of the divisor"]
27    #[inline(always)]
28    #[must_use]
29    pub fn frac(&mut self) -> FRAC_W<CLK_GPOUT2_DIV_SPEC> {
30        FRAC_W::new(self, 0)
31    }
32    #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"]
33    #[inline(always)]
34    #[must_use]
35    pub fn int(&mut self) -> INT_W<CLK_GPOUT2_DIV_SPEC> {
36        INT_W::new(self, 8)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "Clock divisor, can be changed on-the-fly  
50
51You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
52pub struct CLK_GPOUT2_DIV_SPEC;
53impl crate::RegisterSpec for CLK_GPOUT2_DIV_SPEC {
54    type Ux = u32;
55}
56#[doc = "`read()` method returns [`clk_gpout2_div::R`](R) reader structure"]
57impl crate::Readable for CLK_GPOUT2_DIV_SPEC {}
58#[doc = "`write(|w| ..)` method takes [`clk_gpout2_div::W`](W) writer structure"]
59impl crate::Writable for CLK_GPOUT2_DIV_SPEC {
60    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
61    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62}
63#[doc = "`reset()` method sets CLK_GPOUT2_DIV to value 0x0100"]
64impl crate::Resettable for CLK_GPOUT2_DIV_SPEC {
65    const RESET_VALUE: u32 = 0x0100;
66}
rp2040_pac/clocks/clk_gpout2_div.rs

rp2040_pac/clocks/
clk_gpout2_div.rs
