nrf52840_pac/i2s/config/
mckfreq.rs

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1#[doc = "Register `MCKFREQ` reader"]
2pub struct R(crate::R<MCKFREQ_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MCKFREQ_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MCKFREQ_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MCKFREQ_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MCKFREQ` writer"]
17pub struct W(crate::W<MCKFREQ_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MCKFREQ_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MCKFREQ_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MCKFREQ_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MCKFREQ` reader - Master clock generator frequency."]
38pub type MCKFREQ_R = crate::FieldReader<u32, MCKFREQ_A>;
39#[doc = "Master clock generator frequency.\n\nValue on reset: 536870912"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41#[repr(u32)]
42pub enum MCKFREQ_A {
43    #[doc = "2147483648: 32 MHz / 2 = 16.0 MHz"]
44    _32MDIV2 = 2147483648,
45    #[doc = "1342177280: 32 MHz / 3 = 10.6666667 MHz"]
46    _32MDIV3 = 1342177280,
47    #[doc = "1073741824: 32 MHz / 4 = 8.0 MHz"]
48    _32MDIV4 = 1073741824,
49    #[doc = "805306368: 32 MHz / 5 = 6.4 MHz"]
50    _32MDIV5 = 805306368,
51    #[doc = "671088640: 32 MHz / 6 = 5.3333333 MHz"]
52    _32MDIV6 = 671088640,
53    #[doc = "536870912: 32 MHz / 8 = 4.0 MHz"]
54    _32MDIV8 = 536870912,
55    #[doc = "402653184: 32 MHz / 10 = 3.2 MHz"]
56    _32MDIV10 = 402653184,
57    #[doc = "369098752: 32 MHz / 11 = 2.9090909 MHz"]
58    _32MDIV11 = 369098752,
59    #[doc = "285212672: 32 MHz / 15 = 2.1333333 MHz"]
60    _32MDIV15 = 285212672,
61    #[doc = "268435456: 32 MHz / 16 = 2.0 MHz"]
62    _32MDIV16 = 268435456,
63    #[doc = "201326592: 32 MHz / 21 = 1.5238095"]
64    _32MDIV21 = 201326592,
65    #[doc = "184549376: 32 MHz / 23 = 1.3913043 MHz"]
66    _32MDIV23 = 184549376,
67    #[doc = "142606336: 32 MHz / 30 = 1.0666667 MHz"]
68    _32MDIV30 = 142606336,
69    #[doc = "138412032: 32 MHz / 31 = 1.0322581 MHz"]
70    _32MDIV31 = 138412032,
71    #[doc = "134217728: 32 MHz / 32 = 1.0 MHz"]
72    _32MDIV32 = 134217728,
73    #[doc = "100663296: 32 MHz / 42 = 0.7619048 MHz"]
74    _32MDIV42 = 100663296,
75    #[doc = "68157440: 32 MHz / 63 = 0.5079365 MHz"]
76    _32MDIV63 = 68157440,
77    #[doc = "34340864: 32 MHz / 125 = 0.256 MHz"]
78    _32MDIV125 = 34340864,
79}
80impl From<MCKFREQ_A> for u32 {
81    #[inline(always)]
82    fn from(variant: MCKFREQ_A) -> Self {
83        variant as _
84    }
85}
86impl MCKFREQ_R {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub fn variant(&self) -> Option<MCKFREQ_A> {
90        match self.bits {
91            2147483648 => Some(MCKFREQ_A::_32MDIV2),
92            1342177280 => Some(MCKFREQ_A::_32MDIV3),
93            1073741824 => Some(MCKFREQ_A::_32MDIV4),
94            805306368 => Some(MCKFREQ_A::_32MDIV5),
95            671088640 => Some(MCKFREQ_A::_32MDIV6),
96            536870912 => Some(MCKFREQ_A::_32MDIV8),
97            402653184 => Some(MCKFREQ_A::_32MDIV10),
98            369098752 => Some(MCKFREQ_A::_32MDIV11),
99            285212672 => Some(MCKFREQ_A::_32MDIV15),
100            268435456 => Some(MCKFREQ_A::_32MDIV16),
101            201326592 => Some(MCKFREQ_A::_32MDIV21),
102            184549376 => Some(MCKFREQ_A::_32MDIV23),
103            142606336 => Some(MCKFREQ_A::_32MDIV30),
104            138412032 => Some(MCKFREQ_A::_32MDIV31),
105            134217728 => Some(MCKFREQ_A::_32MDIV32),
106            100663296 => Some(MCKFREQ_A::_32MDIV42),
107            68157440 => Some(MCKFREQ_A::_32MDIV63),
108            34340864 => Some(MCKFREQ_A::_32MDIV125),
109            _ => None,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_32MDIV2`"]
113    #[inline(always)]
114    pub fn is_32mdiv2(&self) -> bool {
115        *self == MCKFREQ_A::_32MDIV2
116    }
117    #[doc = "Checks if the value of the field is `_32MDIV3`"]
118    #[inline(always)]
119    pub fn is_32mdiv3(&self) -> bool {
120        *self == MCKFREQ_A::_32MDIV3
121    }
122    #[doc = "Checks if the value of the field is `_32MDIV4`"]
123    #[inline(always)]
124    pub fn is_32mdiv4(&self) -> bool {
125        *self == MCKFREQ_A::_32MDIV4
126    }
127    #[doc = "Checks if the value of the field is `_32MDIV5`"]
128    #[inline(always)]
129    pub fn is_32mdiv5(&self) -> bool {
130        *self == MCKFREQ_A::_32MDIV5
131    }
132    #[doc = "Checks if the value of the field is `_32MDIV6`"]
133    #[inline(always)]
134    pub fn is_32mdiv6(&self) -> bool {
135        *self == MCKFREQ_A::_32MDIV6
136    }
137    #[doc = "Checks if the value of the field is `_32MDIV8`"]
138    #[inline(always)]
139    pub fn is_32mdiv8(&self) -> bool {
140        *self == MCKFREQ_A::_32MDIV8
141    }
142    #[doc = "Checks if the value of the field is `_32MDIV10`"]
143    #[inline(always)]
144    pub fn is_32mdiv10(&self) -> bool {
145        *self == MCKFREQ_A::_32MDIV10
146    }
147    #[doc = "Checks if the value of the field is `_32MDIV11`"]
148    #[inline(always)]
149    pub fn is_32mdiv11(&self) -> bool {
150        *self == MCKFREQ_A::_32MDIV11
151    }
152    #[doc = "Checks if the value of the field is `_32MDIV15`"]
153    #[inline(always)]
154    pub fn is_32mdiv15(&self) -> bool {
155        *self == MCKFREQ_A::_32MDIV15
156    }
157    #[doc = "Checks if the value of the field is `_32MDIV16`"]
158    #[inline(always)]
159    pub fn is_32mdiv16(&self) -> bool {
160        *self == MCKFREQ_A::_32MDIV16
161    }
162    #[doc = "Checks if the value of the field is `_32MDIV21`"]
163    #[inline(always)]
164    pub fn is_32mdiv21(&self) -> bool {
165        *self == MCKFREQ_A::_32MDIV21
166    }
167    #[doc = "Checks if the value of the field is `_32MDIV23`"]
168    #[inline(always)]
169    pub fn is_32mdiv23(&self) -> bool {
170        *self == MCKFREQ_A::_32MDIV23
171    }
172    #[doc = "Checks if the value of the field is `_32MDIV30`"]
173    #[inline(always)]
174    pub fn is_32mdiv30(&self) -> bool {
175        *self == MCKFREQ_A::_32MDIV30
176    }
177    #[doc = "Checks if the value of the field is `_32MDIV31`"]
178    #[inline(always)]
179    pub fn is_32mdiv31(&self) -> bool {
180        *self == MCKFREQ_A::_32MDIV31
181    }
182    #[doc = "Checks if the value of the field is `_32MDIV32`"]
183    #[inline(always)]
184    pub fn is_32mdiv32(&self) -> bool {
185        *self == MCKFREQ_A::_32MDIV32
186    }
187    #[doc = "Checks if the value of the field is `_32MDIV42`"]
188    #[inline(always)]
189    pub fn is_32mdiv42(&self) -> bool {
190        *self == MCKFREQ_A::_32MDIV42
191    }
192    #[doc = "Checks if the value of the field is `_32MDIV63`"]
193    #[inline(always)]
194    pub fn is_32mdiv63(&self) -> bool {
195        *self == MCKFREQ_A::_32MDIV63
196    }
197    #[doc = "Checks if the value of the field is `_32MDIV125`"]
198    #[inline(always)]
199    pub fn is_32mdiv125(&self) -> bool {
200        *self == MCKFREQ_A::_32MDIV125
201    }
202}
203#[doc = "Field `MCKFREQ` writer - Master clock generator frequency."]
204pub type MCKFREQ_W<'a, const O: u8> =
205    crate::FieldWriter<'a, u32, MCKFREQ_SPEC, u32, MCKFREQ_A, 32, O>;
206impl<'a, const O: u8> MCKFREQ_W<'a, O> {
207    #[doc = "32 MHz / 2 = 16.0 MHz"]
208    #[inline(always)]
209    pub fn _32mdiv2(self) -> &'a mut W {
210        self.variant(MCKFREQ_A::_32MDIV2)
211    }
212    #[doc = "32 MHz / 3 = 10.6666667 MHz"]
213    #[inline(always)]
214    pub fn _32mdiv3(self) -> &'a mut W {
215        self.variant(MCKFREQ_A::_32MDIV3)
216    }
217    #[doc = "32 MHz / 4 = 8.0 MHz"]
218    #[inline(always)]
219    pub fn _32mdiv4(self) -> &'a mut W {
220        self.variant(MCKFREQ_A::_32MDIV4)
221    }
222    #[doc = "32 MHz / 5 = 6.4 MHz"]
223    #[inline(always)]
224    pub fn _32mdiv5(self) -> &'a mut W {
225        self.variant(MCKFREQ_A::_32MDIV5)
226    }
227    #[doc = "32 MHz / 6 = 5.3333333 MHz"]
228    #[inline(always)]
229    pub fn _32mdiv6(self) -> &'a mut W {
230        self.variant(MCKFREQ_A::_32MDIV6)
231    }
232    #[doc = "32 MHz / 8 = 4.0 MHz"]
233    #[inline(always)]
234    pub fn _32mdiv8(self) -> &'a mut W {
235        self.variant(MCKFREQ_A::_32MDIV8)
236    }
237    #[doc = "32 MHz / 10 = 3.2 MHz"]
238    #[inline(always)]
239    pub fn _32mdiv10(self) -> &'a mut W {
240        self.variant(MCKFREQ_A::_32MDIV10)
241    }
242    #[doc = "32 MHz / 11 = 2.9090909 MHz"]
243    #[inline(always)]
244    pub fn _32mdiv11(self) -> &'a mut W {
245        self.variant(MCKFREQ_A::_32MDIV11)
246    }
247    #[doc = "32 MHz / 15 = 2.1333333 MHz"]
248    #[inline(always)]
249    pub fn _32mdiv15(self) -> &'a mut W {
250        self.variant(MCKFREQ_A::_32MDIV15)
251    }
252    #[doc = "32 MHz / 16 = 2.0 MHz"]
253    #[inline(always)]
254    pub fn _32mdiv16(self) -> &'a mut W {
255        self.variant(MCKFREQ_A::_32MDIV16)
256    }
257    #[doc = "32 MHz / 21 = 1.5238095"]
258    #[inline(always)]
259    pub fn _32mdiv21(self) -> &'a mut W {
260        self.variant(MCKFREQ_A::_32MDIV21)
261    }
262    #[doc = "32 MHz / 23 = 1.3913043 MHz"]
263    #[inline(always)]
264    pub fn _32mdiv23(self) -> &'a mut W {
265        self.variant(MCKFREQ_A::_32MDIV23)
266    }
267    #[doc = "32 MHz / 30 = 1.0666667 MHz"]
268    #[inline(always)]
269    pub fn _32mdiv30(self) -> &'a mut W {
270        self.variant(MCKFREQ_A::_32MDIV30)
271    }
272    #[doc = "32 MHz / 31 = 1.0322581 MHz"]
273    #[inline(always)]
274    pub fn _32mdiv31(self) -> &'a mut W {
275        self.variant(MCKFREQ_A::_32MDIV31)
276    }
277    #[doc = "32 MHz / 32 = 1.0 MHz"]
278    #[inline(always)]
279    pub fn _32mdiv32(self) -> &'a mut W {
280        self.variant(MCKFREQ_A::_32MDIV32)
281    }
282    #[doc = "32 MHz / 42 = 0.7619048 MHz"]
283    #[inline(always)]
284    pub fn _32mdiv42(self) -> &'a mut W {
285        self.variant(MCKFREQ_A::_32MDIV42)
286    }
287    #[doc = "32 MHz / 63 = 0.5079365 MHz"]
288    #[inline(always)]
289    pub fn _32mdiv63(self) -> &'a mut W {
290        self.variant(MCKFREQ_A::_32MDIV63)
291    }
292    #[doc = "32 MHz / 125 = 0.256 MHz"]
293    #[inline(always)]
294    pub fn _32mdiv125(self) -> &'a mut W {
295        self.variant(MCKFREQ_A::_32MDIV125)
296    }
297}
298impl R {
299    #[doc = "Bits 0:31 - Master clock generator frequency."]
300    #[inline(always)]
301    pub fn mckfreq(&self) -> MCKFREQ_R {
302        MCKFREQ_R::new(self.bits)
303    }
304}
305impl W {
306    #[doc = "Bits 0:31 - Master clock generator frequency."]
307    #[inline(always)]
308    pub fn mckfreq(&mut self) -> MCKFREQ_W<0> {
309        MCKFREQ_W::new(self)
310    }
311    #[doc = "Writes raw bits to the register."]
312    #[inline(always)]
313    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
314        self.0.bits(bits);
315        self
316    }
317}
318#[doc = "Master clock generator frequency.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mckfreq](index.html) module"]
319pub struct MCKFREQ_SPEC;
320impl crate::RegisterSpec for MCKFREQ_SPEC {
321    type Ux = u32;
322}
323#[doc = "`read()` method returns [mckfreq::R](R) reader structure"]
324impl crate::Readable for MCKFREQ_SPEC {
325    type Reader = R;
326}
327#[doc = "`write(|w| ..)` method takes [mckfreq::W](W) writer structure"]
328impl crate::Writable for MCKFREQ_SPEC {
329    type Writer = W;
330}
331#[doc = "`reset()` method sets MCKFREQ to value 0x2000_0000"]
332impl crate::Resettable for MCKFREQ_SPEC {
333    #[inline(always)]
334    fn reset_value() -> Self::Ux {
335        0x2000_0000
336    }
337}
nrf52840_pac/i2s/config/mckfreq.rs

nrf52840_pac/i2s/config/
mckfreq.rs
