imxrt_ral/blocks/imxrt1011/
gpc.rs

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1#[doc = "GPC"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "GPC Interface control register"]
5    pub CNTR: crate::RWRegister<u32>,
6    _reserved0: [u8; 0x04],
7    #[doc = "IRQ masking register 1"]
8    pub IMR1: crate::RWRegister<u32>,
9    #[doc = "IRQ masking register 2"]
10    pub IMR2: crate::RWRegister<u32>,
11    #[doc = "IRQ masking register 3"]
12    pub IMR3: crate::RWRegister<u32>,
13    #[doc = "IRQ masking register 4"]
14    pub IMR4: crate::RWRegister<u32>,
15    #[doc = "IRQ status resister 1"]
16    pub ISR1: crate::RORegister<u32>,
17    #[doc = "IRQ status resister 2"]
18    pub ISR2: crate::RORegister<u32>,
19    #[doc = "IRQ status resister 3"]
20    pub ISR3: crate::RORegister<u32>,
21    #[doc = "IRQ status resister 4"]
22    pub ISR4: crate::RORegister<u32>,
23    _reserved1: [u8; 0x0c],
24    #[doc = "IRQ masking register 5"]
25    pub IMR5: crate::RWRegister<u32>,
26    #[doc = "IRQ status resister 5"]
27    pub ISR5: crate::RORegister<u32>,
28}
29#[doc = "GPC Interface control register"]
30pub mod CNTR {
31    #[doc = "MEGA domain power down request"]
32    pub mod MEGA_PDN_REQ {
33        pub const offset: u32 = 2;
34        pub const mask: u32 = 0x01 << offset;
35        pub mod R {}
36        pub mod W {}
37        pub mod RW {
38            #[doc = "No Request"]
39            pub const MEGA_PDN_REQ_0: u32 = 0;
40            #[doc = "Request power down sequence"]
41            pub const MEGA_PDN_REQ_1: u32 = 0x01;
42        }
43    }
44    #[doc = "MEGA domain power up request"]
45    pub mod MEGA_PUP_REQ {
46        pub const offset: u32 = 3;
47        pub const mask: u32 = 0x01 << offset;
48        pub mod R {}
49        pub mod W {}
50        pub mod RW {
51            #[doc = "No Request"]
52            pub const MEGA_PUP_REQ_0: u32 = 0;
53            #[doc = "Request power up sequence"]
54            pub const MEGA_PUP_REQ_1: u32 = 0x01;
55        }
56    }
57    #[doc = "FlexRAM PDRAM0 Power Gate Enable"]
58    pub mod PDRAM0_PGE {
59        pub const offset: u32 = 22;
60        pub const mask: u32 = 0x01 << offset;
61        pub mod R {}
62        pub mod W {}
63        pub mod RW {
64            #[doc = "FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down."]
65            pub const PDRAM0_PGE_0: u32 = 0;
66            #[doc = "FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down.."]
67            pub const PDRAM0_PGE_1: u32 = 0x01;
68        }
69    }
70}
71#[doc = "IRQ masking register 1"]
72pub mod IMR1 {
73    #[doc = "IRQ\\[31:0\\] masking bits: 1-irq masked, 0-irq is not masked"]
74    pub mod IMR1 {
75        pub const offset: u32 = 0;
76        pub const mask: u32 = 0xffff_ffff << offset;
77        pub mod R {}
78        pub mod W {}
79        pub mod RW {}
80    }
81}
82#[doc = "IRQ masking register 2"]
83pub mod IMR2 {
84    #[doc = "IRQ\\[63:32\\] masking bits: 1-irq masked, 0-irq is not masked"]
85    pub mod IMR2 {
86        pub const offset: u32 = 0;
87        pub const mask: u32 = 0xffff_ffff << offset;
88        pub mod R {}
89        pub mod W {}
90        pub mod RW {}
91    }
92}
93#[doc = "IRQ masking register 3"]
94pub mod IMR3 {
95    #[doc = "IRQ\\[95:64\\] masking bits: 1-irq masked, 0-irq is not masked"]
96    pub mod IMR3 {
97        pub const offset: u32 = 0;
98        pub const mask: u32 = 0xffff_ffff << offset;
99        pub mod R {}
100        pub mod W {}
101        pub mod RW {}
102    }
103}
104#[doc = "IRQ masking register 4"]
105pub mod IMR4 {
106    #[doc = "IRQ\\[127:96\\] masking bits: 1-irq masked, 0-irq is not masked"]
107    pub mod IMR4 {
108        pub const offset: u32 = 0;
109        pub const mask: u32 = 0xffff_ffff << offset;
110        pub mod R {}
111        pub mod W {}
112        pub mod RW {}
113    }
114}
115#[doc = "IRQ status resister 1"]
116pub mod ISR1 {
117    #[doc = "IRQ\\[31:0\\] status, read only"]
118    pub mod ISR1 {
119        pub const offset: u32 = 0;
120        pub const mask: u32 = 0xffff_ffff << offset;
121        pub mod R {}
122        pub mod W {}
123        pub mod RW {}
124    }
125}
126#[doc = "IRQ status resister 2"]
127pub mod ISR2 {
128    #[doc = "IRQ\\[63:32\\] status, read only"]
129    pub mod ISR2 {
130        pub const offset: u32 = 0;
131        pub const mask: u32 = 0xffff_ffff << offset;
132        pub mod R {}
133        pub mod W {}
134        pub mod RW {}
135    }
136}
137#[doc = "IRQ status resister 3"]
138pub mod ISR3 {
139    #[doc = "IRQ\\[95:64\\] status, read only"]
140    pub mod ISR3 {
141        pub const offset: u32 = 0;
142        pub const mask: u32 = 0xffff_ffff << offset;
143        pub mod R {}
144        pub mod W {}
145        pub mod RW {}
146    }
147}
148#[doc = "IRQ status resister 4"]
149pub mod ISR4 {
150    #[doc = "IRQ\\[127:96\\] status, read only"]
151    pub mod ISR4 {
152        pub const offset: u32 = 0;
153        pub const mask: u32 = 0xffff_ffff << offset;
154        pub mod R {}
155        pub mod W {}
156        pub mod RW {}
157    }
158}
159#[doc = "IRQ masking register 5"]
160pub mod IMR5 {
161    #[doc = "IRQ\\[159:128\\] masking bits: 1-irq masked, 0-irq is not masked"]
162    pub mod IMR5 {
163        pub const offset: u32 = 0;
164        pub const mask: u32 = 0xffff_ffff << offset;
165        pub mod R {}
166        pub mod W {}
167        pub mod RW {}
168    }
169}
170#[doc = "IRQ status resister 5"]
171pub mod ISR5 {
172    #[doc = "IRQ\\[159:128\\] status, read only"]
173    pub mod ISR4 {
174        pub const offset: u32 = 0;
175        pub const mask: u32 = 0xffff_ffff << offset;
176        pub mod R {}
177        pub mod W {}
178        pub mod RW {}
179    }
180}
imxrt_ral/blocks/imxrt1011/gpc.rs

imxrt_ral/blocks/imxrt1011/
gpc.rs
