1#[doc = "IOMUXC"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x10],
5 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register"]
6 pub SW_MUX_CTL_PAD_GPIO_AD_14: crate::RWRegister<u32>,
7 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register"]
8 pub SW_MUX_CTL_PAD_GPIO_AD_13: crate::RWRegister<u32>,
9 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register"]
10 pub SW_MUX_CTL_PAD_GPIO_AD_12: crate::RWRegister<u32>,
11 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register"]
12 pub SW_MUX_CTL_PAD_GPIO_AD_11: crate::RWRegister<u32>,
13 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register"]
14 pub SW_MUX_CTL_PAD_GPIO_AD_10: crate::RWRegister<u32>,
15 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register"]
16 pub SW_MUX_CTL_PAD_GPIO_AD_09: crate::RWRegister<u32>,
17 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register"]
18 pub SW_MUX_CTL_PAD_GPIO_AD_08: crate::RWRegister<u32>,
19 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register"]
20 pub SW_MUX_CTL_PAD_GPIO_AD_07: crate::RWRegister<u32>,
21 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register"]
22 pub SW_MUX_CTL_PAD_GPIO_AD_06: crate::RWRegister<u32>,
23 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register"]
24 pub SW_MUX_CTL_PAD_GPIO_AD_05: crate::RWRegister<u32>,
25 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register"]
26 pub SW_MUX_CTL_PAD_GPIO_AD_04: crate::RWRegister<u32>,
27 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register"]
28 pub SW_MUX_CTL_PAD_GPIO_AD_03: crate::RWRegister<u32>,
29 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register"]
30 pub SW_MUX_CTL_PAD_GPIO_AD_02: crate::RWRegister<u32>,
31 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register"]
32 pub SW_MUX_CTL_PAD_GPIO_AD_01: crate::RWRegister<u32>,
33 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register"]
34 pub SW_MUX_CTL_PAD_GPIO_AD_00: crate::RWRegister<u32>,
35 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register"]
36 pub SW_MUX_CTL_PAD_GPIO_SD_14: crate::RWRegister<u32>,
37 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register"]
38 pub SW_MUX_CTL_PAD_GPIO_SD_13: crate::RWRegister<u32>,
39 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register"]
40 pub SW_MUX_CTL_PAD_GPIO_SD_12: crate::RWRegister<u32>,
41 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register"]
42 pub SW_MUX_CTL_PAD_GPIO_SD_11: crate::RWRegister<u32>,
43 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register"]
44 pub SW_MUX_CTL_PAD_GPIO_SD_10: crate::RWRegister<u32>,
45 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register"]
46 pub SW_MUX_CTL_PAD_GPIO_SD_09: crate::RWRegister<u32>,
47 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register"]
48 pub SW_MUX_CTL_PAD_GPIO_SD_08: crate::RWRegister<u32>,
49 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register"]
50 pub SW_MUX_CTL_PAD_GPIO_SD_07: crate::RWRegister<u32>,
51 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register"]
52 pub SW_MUX_CTL_PAD_GPIO_SD_06: crate::RWRegister<u32>,
53 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register"]
54 pub SW_MUX_CTL_PAD_GPIO_SD_05: crate::RWRegister<u32>,
55 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register"]
56 pub SW_MUX_CTL_PAD_GPIO_SD_04: crate::RWRegister<u32>,
57 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register"]
58 pub SW_MUX_CTL_PAD_GPIO_SD_03: crate::RWRegister<u32>,
59 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register"]
60 pub SW_MUX_CTL_PAD_GPIO_SD_02: crate::RWRegister<u32>,
61 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register"]
62 pub SW_MUX_CTL_PAD_GPIO_SD_01: crate::RWRegister<u32>,
63 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register"]
64 pub SW_MUX_CTL_PAD_GPIO_SD_00: crate::RWRegister<u32>,
65 #[doc = "SW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register"]
66 pub SW_MUX_CTL_PAD_GPIO_13: crate::RWRegister<u32>,
67 #[doc = "SW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register"]
68 pub SW_MUX_CTL_PAD_GPIO_12: crate::RWRegister<u32>,
69 #[doc = "SW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register"]
70 pub SW_MUX_CTL_PAD_GPIO_11: crate::RWRegister<u32>,
71 #[doc = "SW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register"]
72 pub SW_MUX_CTL_PAD_GPIO_10: crate::RWRegister<u32>,
73 #[doc = "SW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register"]
74 pub SW_MUX_CTL_PAD_GPIO_09: crate::RWRegister<u32>,
75 #[doc = "SW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register"]
76 pub SW_MUX_CTL_PAD_GPIO_08: crate::RWRegister<u32>,
77 #[doc = "SW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register"]
78 pub SW_MUX_CTL_PAD_GPIO_07: crate::RWRegister<u32>,
79 #[doc = "SW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register"]
80 pub SW_MUX_CTL_PAD_GPIO_06: crate::RWRegister<u32>,
81 #[doc = "SW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register"]
82 pub SW_MUX_CTL_PAD_GPIO_05: crate::RWRegister<u32>,
83 #[doc = "SW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register"]
84 pub SW_MUX_CTL_PAD_GPIO_04: crate::RWRegister<u32>,
85 #[doc = "SW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register"]
86 pub SW_MUX_CTL_PAD_GPIO_03: crate::RWRegister<u32>,
87 #[doc = "SW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register"]
88 pub SW_MUX_CTL_PAD_GPIO_02: crate::RWRegister<u32>,
89 #[doc = "SW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register"]
90 pub SW_MUX_CTL_PAD_GPIO_01: crate::RWRegister<u32>,
91 #[doc = "SW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register"]
92 pub SW_MUX_CTL_PAD_GPIO_00: crate::RWRegister<u32>,
93 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register"]
94 pub SW_PAD_CTL_PAD_GPIO_AD_14: crate::RWRegister<u32>,
95 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register"]
96 pub SW_PAD_CTL_PAD_GPIO_AD_13: crate::RWRegister<u32>,
97 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register"]
98 pub SW_PAD_CTL_PAD_GPIO_AD_12: crate::RWRegister<u32>,
99 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register"]
100 pub SW_PAD_CTL_PAD_GPIO_AD_11: crate::RWRegister<u32>,
101 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register"]
102 pub SW_PAD_CTL_PAD_GPIO_AD_10: crate::RWRegister<u32>,
103 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register"]
104 pub SW_PAD_CTL_PAD_GPIO_AD_09: crate::RWRegister<u32>,
105 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register"]
106 pub SW_PAD_CTL_PAD_GPIO_AD_08: crate::RWRegister<u32>,
107 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register"]
108 pub SW_PAD_CTL_PAD_GPIO_AD_07: crate::RWRegister<u32>,
109 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register"]
110 pub SW_PAD_CTL_PAD_GPIO_AD_06: crate::RWRegister<u32>,
111 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register"]
112 pub SW_PAD_CTL_PAD_GPIO_AD_05: crate::RWRegister<u32>,
113 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register"]
114 pub SW_PAD_CTL_PAD_GPIO_AD_04: crate::RWRegister<u32>,
115 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register"]
116 pub SW_PAD_CTL_PAD_GPIO_AD_03: crate::RWRegister<u32>,
117 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register"]
118 pub SW_PAD_CTL_PAD_GPIO_AD_02: crate::RWRegister<u32>,
119 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register"]
120 pub SW_PAD_CTL_PAD_GPIO_AD_01: crate::RWRegister<u32>,
121 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register"]
122 pub SW_PAD_CTL_PAD_GPIO_AD_00: crate::RWRegister<u32>,
123 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register"]
124 pub SW_PAD_CTL_PAD_GPIO_SD_14: crate::RWRegister<u32>,
125 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register"]
126 pub SW_PAD_CTL_PAD_GPIO_SD_13: crate::RWRegister<u32>,
127 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register"]
128 pub SW_PAD_CTL_PAD_GPIO_SD_12: crate::RWRegister<u32>,
129 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register"]
130 pub SW_PAD_CTL_PAD_GPIO_SD_11: crate::RWRegister<u32>,
131 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register"]
132 pub SW_PAD_CTL_PAD_GPIO_SD_10: crate::RWRegister<u32>,
133 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register"]
134 pub SW_PAD_CTL_PAD_GPIO_SD_09: crate::RWRegister<u32>,
135 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register"]
136 pub SW_PAD_CTL_PAD_GPIO_SD_08: crate::RWRegister<u32>,
137 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register"]
138 pub SW_PAD_CTL_PAD_GPIO_SD_07: crate::RWRegister<u32>,
139 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register"]
140 pub SW_PAD_CTL_PAD_GPIO_SD_06: crate::RWRegister<u32>,
141 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register"]
142 pub SW_PAD_CTL_PAD_GPIO_SD_05: crate::RWRegister<u32>,
143 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register"]
144 pub SW_PAD_CTL_PAD_GPIO_SD_04: crate::RWRegister<u32>,
145 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register"]
146 pub SW_PAD_CTL_PAD_GPIO_SD_03: crate::RWRegister<u32>,
147 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register"]
148 pub SW_PAD_CTL_PAD_GPIO_SD_02: crate::RWRegister<u32>,
149 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register"]
150 pub SW_PAD_CTL_PAD_GPIO_SD_01: crate::RWRegister<u32>,
151 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register"]
152 pub SW_PAD_CTL_PAD_GPIO_SD_00: crate::RWRegister<u32>,
153 #[doc = "SW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register"]
154 pub SW_PAD_CTL_PAD_GPIO_13: crate::RWRegister<u32>,
155 #[doc = "SW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register"]
156 pub SW_PAD_CTL_PAD_GPIO_12: crate::RWRegister<u32>,
157 #[doc = "SW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register"]
158 pub SW_PAD_CTL_PAD_GPIO_11: crate::RWRegister<u32>,
159 #[doc = "SW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register"]
160 pub SW_PAD_CTL_PAD_GPIO_10: crate::RWRegister<u32>,
161 #[doc = "SW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register"]
162 pub SW_PAD_CTL_PAD_GPIO_09: crate::RWRegister<u32>,
163 #[doc = "SW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register"]
164 pub SW_PAD_CTL_PAD_GPIO_08: crate::RWRegister<u32>,
165 #[doc = "SW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register"]
166 pub SW_PAD_CTL_PAD_GPIO_07: crate::RWRegister<u32>,
167 #[doc = "SW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register"]
168 pub SW_PAD_CTL_PAD_GPIO_06: crate::RWRegister<u32>,
169 #[doc = "SW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register"]
170 pub SW_PAD_CTL_PAD_GPIO_05: crate::RWRegister<u32>,
171 #[doc = "SW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register"]
172 pub SW_PAD_CTL_PAD_GPIO_04: crate::RWRegister<u32>,
173 #[doc = "SW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register"]
174 pub SW_PAD_CTL_PAD_GPIO_03: crate::RWRegister<u32>,
175 #[doc = "SW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register"]
176 pub SW_PAD_CTL_PAD_GPIO_02: crate::RWRegister<u32>,
177 #[doc = "SW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register"]
178 pub SW_PAD_CTL_PAD_GPIO_01: crate::RWRegister<u32>,
179 #[doc = "SW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register"]
180 pub SW_PAD_CTL_PAD_GPIO_00: crate::RWRegister<u32>,
181 #[doc = "USB_OTG_ID_SELECT_INPUT DAISY Register"]
182 pub USB_OTG_ID_SELECT_INPUT: crate::RWRegister<u32>,
183 #[doc = "FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register"]
184 pub FLEXPWM1_PWMA_SELECT_INPUT_0: crate::RWRegister<u32>,
185 #[doc = "FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register"]
186 pub FLEXPWM1_PWMA_SELECT_INPUT_1: crate::RWRegister<u32>,
187 #[doc = "FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register"]
188 pub FLEXPWM1_PWMA_SELECT_INPUT_2: crate::RWRegister<u32>,
189 #[doc = "FLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register"]
190 pub FLEXPWM1_PWMA_SELECT_INPUT_3: crate::RWRegister<u32>,
191 #[doc = "FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register"]
192 pub FLEXPWM1_PWMB_SELECT_INPUT_0: crate::RWRegister<u32>,
193 #[doc = "FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register"]
194 pub FLEXPWM1_PWMB_SELECT_INPUT_1: crate::RWRegister<u32>,
195 #[doc = "FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register"]
196 pub FLEXPWM1_PWMB_SELECT_INPUT_2: crate::RWRegister<u32>,
197 #[doc = "FLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register"]
198 pub FLEXPWM1_PWMB_SELECT_INPUT_3: crate::RWRegister<u32>,
199 #[doc = "FLEXSPI_DQS_FA_SELECT_INPUT DAISY Register"]
200 pub FLEXSPI_DQS_FA_SELECT_INPUT: crate::RWRegister<u32>,
201 #[doc = "FLEXSPI_DQS_FB_SELECT_INPUT DAISY Register"]
202 pub FLEXSPI_DQS_FB_SELECT_INPUT: crate::RWRegister<u32>,
203 #[doc = "KPP_COL_SELECT_INPUT_0 DAISY Register"]
204 pub KPP_COL_SELECT_INPUT_0: crate::RWRegister<u32>,
205 #[doc = "KPP_COL_SELECT_INPUT_1 DAISY Register"]
206 pub KPP_COL_SELECT_INPUT_1: crate::RWRegister<u32>,
207 #[doc = "KPP_COL_SELECT_INPUT_2 DAISY Register"]
208 pub KPP_COL_SELECT_INPUT_2: crate::RWRegister<u32>,
209 #[doc = "KPP_COL_SELECT_INPUT_3 DAISY Register"]
210 pub KPP_COL_SELECT_INPUT_3: crate::RWRegister<u32>,
211 #[doc = "KPP_ROW_SELECT_INPUT_0 DAISY Register"]
212 pub KPP_ROW_SELECT_INPUT_0: crate::RWRegister<u32>,
213 #[doc = "KPP_ROW_SELECT_INPUT_1 DAISY Register"]
214 pub KPP_ROW_SELECT_INPUT_1: crate::RWRegister<u32>,
215 #[doc = "KPP_ROW_SELECT_INPUT_2 DAISY Register"]
216 pub KPP_ROW_SELECT_INPUT_2: crate::RWRegister<u32>,
217 #[doc = "KPP_ROW_SELECT_INPUT_3 DAISY Register"]
218 pub KPP_ROW_SELECT_INPUT_3: crate::RWRegister<u32>,
219 #[doc = "LPI2C1_HREQ_SELECT_INPUT DAISY Register"]
220 pub LPI2C1_HREQ_SELECT_INPUT: crate::RWRegister<u32>,
221 #[doc = "LPI2C1_SCL_SELECT_INPUT DAISY Register"]
222 pub LPI2C1_SCL_SELECT_INPUT: crate::RWRegister<u32>,
223 #[doc = "LPI2C1_SDA_SELECT_INPUT DAISY Register"]
224 pub LPI2C1_SDA_SELECT_INPUT: crate::RWRegister<u32>,
225 #[doc = "LPI2C2_SCL_SELECT_INPUT DAISY Register"]
226 pub LPI2C2_SCL_SELECT_INPUT: crate::RWRegister<u32>,
227 #[doc = "LPI2C2_SDA_SELECT_INPUT DAISY Register"]
228 pub LPI2C2_SDA_SELECT_INPUT: crate::RWRegister<u32>,
229 #[doc = "LPSPI1_PCS_SELECT_INPUT_0 DAISY Register"]
230 pub LPSPI1_PCS_SELECT_INPUT_0: crate::RWRegister<u32>,
231 #[doc = "LPSPI1_SCK_SELECT_INPUT DAISY Register"]
232 pub LPSPI1_SCK_SELECT_INPUT: crate::RWRegister<u32>,
233 #[doc = "LPSPI1_SDI_SELECT_INPUT DAISY Register"]
234 pub LPSPI1_SDI_SELECT_INPUT: crate::RWRegister<u32>,
235 #[doc = "LPSPI1_SDO_SELECT_INPUT DAISY Register"]
236 pub LPSPI1_SDO_SELECT_INPUT: crate::RWRegister<u32>,
237 #[doc = "LPSPI2_PCS_SELECT_INPUT_0 DAISY Register"]
238 pub LPSPI2_PCS_SELECT_INPUT_0: crate::RWRegister<u32>,
239 #[doc = "LPSPI2_SCK_SELECT_INPUT DAISY Register"]
240 pub LPSPI2_SCK_SELECT_INPUT: crate::RWRegister<u32>,
241 #[doc = "LPSPI2_SDI_SELECT_INPUT DAISY Register"]
242 pub LPSPI2_SDI_SELECT_INPUT: crate::RWRegister<u32>,
243 #[doc = "LPSPI2_SDO_SELECT_INPUT DAISY Register"]
244 pub LPSPI2_SDO_SELECT_INPUT: crate::RWRegister<u32>,
245 #[doc = "LPUART1_RXD_SELECT_INPUT DAISY Register"]
246 pub LPUART1_RXD_SELECT_INPUT: crate::RWRegister<u32>,
247 #[doc = "LPUART1_TXD_SELECT_INPUT DAISY Register"]
248 pub LPUART1_TXD_SELECT_INPUT: crate::RWRegister<u32>,
249 #[doc = "LPUART2_RXD_SELECT_INPUT DAISY Register"]
250 pub LPUART2_RXD_SELECT_INPUT: crate::RWRegister<u32>,
251 #[doc = "LPUART2_TXD_SELECT_INPUT DAISY Register"]
252 pub LPUART2_TXD_SELECT_INPUT: crate::RWRegister<u32>,
253 #[doc = "LPUART3_RXD_SELECT_INPUT DAISY Register"]
254 pub LPUART3_RXD_SELECT_INPUT: crate::RWRegister<u32>,
255 #[doc = "LPUART3_TXD_SELECT_INPUT DAISY Register"]
256 pub LPUART3_TXD_SELECT_INPUT: crate::RWRegister<u32>,
257 #[doc = "LPUART4_RXD_SELECT_INPUT DAISY Register"]
258 pub LPUART4_RXD_SELECT_INPUT: crate::RWRegister<u32>,
259 #[doc = "LPUART4_TXD_SELECT_INPUT DAISY Register"]
260 pub LPUART4_TXD_SELECT_INPUT: crate::RWRegister<u32>,
261 #[doc = "NMI_GLUE_NMI_SELECT_INPUT DAISY Register"]
262 pub NMI_GLUE_NMI_SELECT_INPUT: crate::RWRegister<u32>,
263 #[doc = "SPDIF_IN1_SELECT_INPUT DAISY Register"]
264 pub SPDIF_IN1_SELECT_INPUT: crate::RWRegister<u32>,
265 #[doc = "SPDIF_TX_CLK2_SELECT_INPUT DAISY Register"]
266 pub SPDIF_TX_CLK2_SELECT_INPUT: crate::RWRegister<u32>,
267 #[doc = "USB_OTG_OC_SELECT_INPUT DAISY Register"]
268 pub USB_OTG_OC_SELECT_INPUT: crate::RWRegister<u32>,
269 #[doc = "XEV_GLUE_RXEV_SELECT_INPUT DAISY Register"]
270 pub XEV_GLUE_RXEV_SELECT_INPUT: crate::RWRegister<u32>,
271}
272#[doc = "SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register"]
273pub mod SW_MUX_CTL_PAD_GPIO_AD_14 {
274 #[doc = "MUX Mode Select Field."]
275 pub mod MUX_MODE {
276 pub const offset: u32 = 0;
277 pub const mask: u32 = 0x07 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {
281 #[doc = "Select mux mode: ALT0 mux port: LPI2C1_SCL of instance: LPI2C1"]
282 pub const ALT0: u32 = 0;
283 #[doc = "Select mux mode: ALT1 mux port: LPUART3_CTS_B of instance: LPUART3"]
284 pub const ALT1: u32 = 0x01;
285 #[doc = "Select mux mode: ALT2 mux port: KPP_COL00 of instance: KPP"]
286 pub const ALT2: u32 = 0x02;
287 #[doc = "Select mux mode: ALT3 mux port: LPUART4_CTS_B of instance: LPUART4"]
288 pub const ALT3: u32 = 0x03;
289 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO26 of instance: FLEXIO1"]
290 pub const ALT4: u32 = 0x04;
291 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO28 of instance: GPIOMUX"]
292 pub const ALT5: u32 = 0x05;
293 #[doc = "Select mux mode: ALT6 mux port: REF_CLK_24M of instance: XTAL OSC"]
294 pub const ALT6: u32 = 0x06;
295 #[doc = "Select mux mode: ALT7 mux port: XBAR1_INOUT02 of instance: XBAR1"]
296 pub const ALT7: u32 = 0x07;
297 }
298 }
299 #[doc = "Software Input On Field."]
300 pub mod SION {
301 pub const offset: u32 = 4;
302 pub const mask: u32 = 0x01 << offset;
303 pub mod R {}
304 pub mod W {}
305 pub mod RW {
306 #[doc = "Input Path is determined by functionality"]
307 pub const DISABLED: u32 = 0;
308 #[doc = "Force input path of pad GPIO_AD_14"]
309 pub const ENABLED: u32 = 0x01;
310 }
311 }
312}
313#[doc = "SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register"]
314pub mod SW_MUX_CTL_PAD_GPIO_AD_13 {
315 #[doc = "MUX Mode Select Field."]
316 pub mod MUX_MODE {
317 pub const offset: u32 = 0;
318 pub const mask: u32 = 0x07 << offset;
319 pub mod R {}
320 pub mod W {}
321 pub mod RW {
322 #[doc = "Select mux mode: ALT0 mux port: LPI2C1_SDA of instance: LPI2C1"]
323 pub const ALT0: u32 = 0;
324 #[doc = "Select mux mode: ALT1 mux port: LPUART3_RTS_B of instance: LPUART3"]
325 pub const ALT1: u32 = 0x01;
326 #[doc = "Select mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP"]
327 pub const ALT2: u32 = 0x02;
328 #[doc = "Select mux mode: ALT3 mux port: LPUART4_RTS_B of instance: LPUART4"]
329 pub const ALT3: u32 = 0x03;
330 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO25 of instance: FLEXIO1"]
331 pub const ALT4: u32 = 0x04;
332 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO27 of instance: GPIOMUX"]
333 pub const ALT5: u32 = 0x05;
334 #[doc = "Select mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: NMI_GLUE"]
335 pub const ALT6: u32 = 0x06;
336 #[doc = "Select mux mode: ALT7 mux port: JTAG_TMS of instance: JTAG"]
337 pub const ALT7: u32 = 0x07;
338 }
339 }
340 #[doc = "Software Input On Field."]
341 pub mod SION {
342 pub const offset: u32 = 4;
343 pub const mask: u32 = 0x01 << offset;
344 pub mod R {}
345 pub mod W {}
346 pub mod RW {
347 #[doc = "Input Path is determined by functionality"]
348 pub const DISABLED: u32 = 0;
349 #[doc = "Force input path of pad GPIO_AD_13"]
350 pub const ENABLED: u32 = 0x01;
351 }
352 }
353}
354#[doc = "SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register"]
355pub mod SW_MUX_CTL_PAD_GPIO_AD_12 {
356 #[doc = "MUX Mode Select Field."]
357 pub mod MUX_MODE {
358 pub const offset: u32 = 0;
359 pub const mask: u32 = 0x07 << offset;
360 pub mod R {}
361 pub mod W {}
362 pub mod RW {
363 #[doc = "Select mux mode: ALT0 mux port: LPSPI2_SCK of instance: LPSPI2"]
364 pub const ALT0: u32 = 0;
365 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_X of instance: FLEXPWM1"]
366 pub const ALT1: u32 = 0x01;
367 #[doc = "Select mux mode: ALT2 mux port: KPP_COL01 of instance: KPP"]
368 pub const ALT2: u32 = 0x02;
369 #[doc = "Select mux mode: ALT3 mux port: PIT_TRIGGER01 of instance: PIT"]
370 pub const ALT3: u32 = 0x03;
371 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO24 of instance: FLEXIO1"]
372 pub const ALT4: u32 = 0x04;
373 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO26 of instance: GPIOMUX"]
374 pub const ALT5: u32 = 0x05;
375 #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_PWR of instance: USB"]
376 pub const ALT6: u32 = 0x06;
377 #[doc = "Select mux mode: ALT7 mux port: JTAG_TCK of instance: JTAG"]
378 pub const ALT7: u32 = 0x07;
379 }
380 }
381 #[doc = "Software Input On Field."]
382 pub mod SION {
383 pub const offset: u32 = 4;
384 pub const mask: u32 = 0x01 << offset;
385 pub mod R {}
386 pub mod W {}
387 pub mod RW {
388 #[doc = "Input Path is determined by functionality"]
389 pub const DISABLED: u32 = 0;
390 #[doc = "Force input path of pad GPIO_AD_12"]
391 pub const ENABLED: u32 = 0x01;
392 }
393 }
394}
395#[doc = "SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register"]
396pub mod SW_MUX_CTL_PAD_GPIO_AD_11 {
397 #[doc = "MUX Mode Select Field."]
398 pub mod MUX_MODE {
399 pub const offset: u32 = 0;
400 pub const mask: u32 = 0x07 << offset;
401 pub mod R {}
402 pub mod W {}
403 pub mod RW {
404 #[doc = "Select mux mode: ALT0 mux port: LPSPI2_PCS0 of instance: LPSPI2"]
405 pub const ALT0: u32 = 0;
406 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_X of instance: FLEXPWM1"]
407 pub const ALT1: u32 = 0x01;
408 #[doc = "Select mux mode: ALT2 mux port: KPP_ROW01 of instance: KPP"]
409 pub const ALT2: u32 = 0x02;
410 #[doc = "Select mux mode: ALT3 mux port: PIT_TRIGGER02 of instance: PIT"]
411 pub const ALT3: u32 = 0x03;
412 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO23 of instance: FLEXIO1"]
413 pub const ALT4: u32 = 0x04;
414 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO25 of instance: GPIOMUX"]
415 pub const ALT5: u32 = 0x05;
416 #[doc = "Select mux mode: ALT6 mux port: WDOG1_B of instance: WDOG1"]
417 pub const ALT6: u32 = 0x06;
418 #[doc = "Select mux mode: ALT7 mux port: JTAG_MOD of instance: JTAG"]
419 pub const ALT7: u32 = 0x07;
420 }
421 }
422 #[doc = "Software Input On Field."]
423 pub mod SION {
424 pub const offset: u32 = 4;
425 pub const mask: u32 = 0x01 << offset;
426 pub mod R {}
427 pub mod W {}
428 pub mod RW {
429 #[doc = "Input Path is determined by functionality"]
430 pub const DISABLED: u32 = 0;
431 #[doc = "Force input path of pad GPIO_AD_11"]
432 pub const ENABLED: u32 = 0x01;
433 }
434 }
435}
436#[doc = "SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register"]
437pub mod SW_MUX_CTL_PAD_GPIO_AD_10 {
438 #[doc = "MUX Mode Select Field."]
439 pub mod MUX_MODE {
440 pub const offset: u32 = 0;
441 pub const mask: u32 = 0x07 << offset;
442 pub mod R {}
443 pub mod W {}
444 pub mod RW {
445 #[doc = "Select mux mode: ALT0 mux port: LPSPI2_SDO of instance: LPSPI2"]
446 pub const ALT0: u32 = 0;
447 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_X of instance: FLEXPWM1"]
448 pub const ALT1: u32 = 0x01;
449 #[doc = "Select mux mode: ALT2 mux port: KPP_COL02 of instance: KPP"]
450 pub const ALT2: u32 = 0x02;
451 #[doc = "Select mux mode: ALT3 mux port: PIT_TRIGGER03 of instance: PIT"]
452 pub const ALT3: u32 = 0x03;
453 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO22 of instance: FLEXIO1"]
454 pub const ALT4: u32 = 0x04;
455 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO24 of instance: GPIOMUX"]
456 pub const ALT5: u32 = 0x05;
457 #[doc = "Select mux mode: ALT6 mux port: OTG1_ID of instance: anatop"]
458 pub const ALT6: u32 = 0x06;
459 #[doc = "Select mux mode: ALT7 mux port: JTAG_TDI of instance: JTAG"]
460 pub const ALT7: u32 = 0x07;
461 }
462 }
463 #[doc = "Software Input On Field."]
464 pub mod SION {
465 pub const offset: u32 = 4;
466 pub const mask: u32 = 0x01 << offset;
467 pub mod R {}
468 pub mod W {}
469 pub mod RW {
470 #[doc = "Input Path is determined by functionality"]
471 pub const DISABLED: u32 = 0;
472 #[doc = "Force input path of pad GPIO_AD_10"]
473 pub const ENABLED: u32 = 0x01;
474 }
475 }
476}
477#[doc = "SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register"]
478pub mod SW_MUX_CTL_PAD_GPIO_AD_09 {
479 #[doc = "MUX Mode Select Field."]
480 pub mod MUX_MODE {
481 pub const offset: u32 = 0;
482 pub const mask: u32 = 0x07 << offset;
483 pub mod R {}
484 pub mod W {}
485 pub mod RW {
486 #[doc = "Select mux mode: ALT0 mux port: LPSPI2_SDI of instance: LPSPI2"]
487 pub const ALT0: u32 = 0;
488 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_X of instance: FLEXPWM1"]
489 pub const ALT1: u32 = 0x01;
490 #[doc = "Select mux mode: ALT2 mux port: KPP_ROW02 of instance: KPP"]
491 pub const ALT2: u32 = 0x02;
492 #[doc = "Select mux mode: ALT3 mux port: ARM_TRACE_SWO of instance: cm7_mxrt"]
493 pub const ALT3: u32 = 0x03;
494 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO21 of instance: FLEXIO1"]
495 pub const ALT4: u32 = 0x04;
496 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO23 of instance: GPIOMUX"]
497 pub const ALT5: u32 = 0x05;
498 #[doc = "Select mux mode: ALT6 mux port: REF_32K_OUT of instance: anatop"]
499 pub const ALT6: u32 = 0x06;
500 #[doc = "Select mux mode: ALT7 mux port: JTAG_TDO of instance: JTAG"]
501 pub const ALT7: u32 = 0x07;
502 }
503 }
504 #[doc = "Software Input On Field."]
505 pub mod SION {
506 pub const offset: u32 = 4;
507 pub const mask: u32 = 0x01 << offset;
508 pub mod R {}
509 pub mod W {}
510 pub mod RW {
511 #[doc = "Input Path is determined by functionality"]
512 pub const DISABLED: u32 = 0;
513 #[doc = "Force input path of pad GPIO_AD_09"]
514 pub const ENABLED: u32 = 0x01;
515 }
516 }
517}
518#[doc = "SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register"]
519pub mod SW_MUX_CTL_PAD_GPIO_AD_08 {
520 #[doc = "MUX Mode Select Field."]
521 pub mod MUX_MODE {
522 pub const offset: u32 = 0;
523 pub const mask: u32 = 0x07 << offset;
524 pub mod R {}
525 pub mod W {}
526 pub mod RW {
527 #[doc = "Select mux mode: ALT0 mux port: LPI2C2_SCL of instance: LPI2C2"]
528 pub const ALT0: u32 = 0;
529 #[doc = "Select mux mode: ALT1 mux port: LPUART3_TXD of instance: LPUART3"]
530 pub const ALT1: u32 = 0x01;
531 #[doc = "Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mxrt"]
532 pub const ALT2: u32 = 0x02;
533 #[doc = "Select mux mode: ALT3 mux port: LPUART2_CTS_B of instance: LPUART2"]
534 pub const ALT3: u32 = 0x03;
535 #[doc = "Select mux mode: ALT4 mux port: GPT2_COMPARE3 of instance: GPT2"]
536 pub const ALT4: u32 = 0x04;
537 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO22 of instance: GPIOMUX"]
538 pub const ALT5: u32 = 0x05;
539 #[doc = "Select mux mode: ALT6 mux port: EWM_OUT_B of instance: EWM"]
540 pub const ALT6: u32 = 0x06;
541 #[doc = "Select mux mode: ALT7 mux port: JTAG_TRSTB of instance: JTAG"]
542 pub const ALT7: u32 = 0x07;
543 }
544 }
545 #[doc = "Software Input On Field."]
546 pub mod SION {
547 pub const offset: u32 = 4;
548 pub const mask: u32 = 0x01 << offset;
549 pub mod R {}
550 pub mod W {}
551 pub mod RW {
552 #[doc = "Input Path is determined by functionality"]
553 pub const DISABLED: u32 = 0;
554 #[doc = "Force input path of pad GPIO_AD_08"]
555 pub const ENABLED: u32 = 0x01;
556 }
557 }
558}
559#[doc = "SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register"]
560pub mod SW_MUX_CTL_PAD_GPIO_AD_07 {
561 #[doc = "MUX Mode Select Field."]
562 pub mod MUX_MODE {
563 pub const offset: u32 = 0;
564 pub const mask: u32 = 0x07 << offset;
565 pub mod R {}
566 pub mod W {}
567 pub mod RW {
568 #[doc = "Select mux mode: ALT0 mux port: LPI2C2_SDA of instance: LPI2C2"]
569 pub const ALT0: u32 = 0;
570 #[doc = "Select mux mode: ALT1 mux port: LPUART3_RXD of instance: LPUART3"]
571 pub const ALT1: u32 = 0x01;
572 #[doc = "Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mxrt"]
573 pub const ALT2: u32 = 0x02;
574 #[doc = "Select mux mode: ALT3 mux port: LPUART2_RTS_B of instance: LPUART2"]
575 pub const ALT3: u32 = 0x03;
576 #[doc = "Select mux mode: ALT4 mux port: GPT2_CAPTURE2 of instance: GPT2"]
577 pub const ALT4: u32 = 0x04;
578 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO21 of instance: GPIOMUX"]
579 pub const ALT5: u32 = 0x05;
580 #[doc = "Select mux mode: ALT6 mux port: OCOTP_FUSE_LATCHED of instance: OCOTP"]
581 pub const ALT6: u32 = 0x06;
582 #[doc = "Select mux mode: ALT7 mux port: XBAR1_INOUT03 of instance: XBAR1"]
583 pub const ALT7: u32 = 0x07;
584 }
585 }
586 #[doc = "Software Input On Field."]
587 pub mod SION {
588 pub const offset: u32 = 4;
589 pub const mask: u32 = 0x01 << offset;
590 pub mod R {}
591 pub mod W {}
592 pub mod RW {
593 #[doc = "Input Path is determined by functionality"]
594 pub const DISABLED: u32 = 0;
595 #[doc = "Force input path of pad GPIO_AD_07"]
596 pub const ENABLED: u32 = 0x01;
597 }
598 }
599}
600#[doc = "SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register"]
601pub mod SW_MUX_CTL_PAD_GPIO_AD_06 {
602 #[doc = "MUX Mode Select Field."]
603 pub mod MUX_MODE {
604 pub const offset: u32 = 0;
605 pub const mask: u32 = 0x07 << offset;
606 pub mod R {}
607 pub mod W {}
608 pub mod RW {
609 #[doc = "Select mux mode: ALT0 mux port: LPSPI1_SCK of instance: LPSPI1"]
610 pub const ALT0: u32 = 0;
611 #[doc = "Select mux mode: ALT1 mux port: PIT_TRIGGER00 of instance: PIT"]
612 pub const ALT1: u32 = 0x01;
613 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1"]
614 pub const ALT2: u32 = 0x02;
615 #[doc = "Select mux mode: ALT3 mux port: KPP_COL01 of instance: KPP"]
616 pub const ALT3: u32 = 0x03;
617 #[doc = "Select mux mode: ALT4 mux port: GPT2_COMPARE2 of instance: GPT2"]
618 pub const ALT4: u32 = 0x04;
619 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO20 of instance: GPIOMUX"]
620 pub const ALT5: u32 = 0x05;
621 #[doc = "Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: LPI2C1"]
622 pub const ALT6: u32 = 0x06;
623 }
624 }
625 #[doc = "Software Input On Field."]
626 pub mod SION {
627 pub const offset: u32 = 4;
628 pub const mask: u32 = 0x01 << offset;
629 pub mod R {}
630 pub mod W {}
631 pub mod RW {
632 #[doc = "Input Path is determined by functionality"]
633 pub const DISABLED: u32 = 0;
634 #[doc = "Force input path of pad GPIO_AD_06"]
635 pub const ENABLED: u32 = 0x01;
636 }
637 }
638}
639#[doc = "SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register"]
640pub mod SW_MUX_CTL_PAD_GPIO_AD_05 {
641 #[doc = "MUX Mode Select Field."]
642 pub mod MUX_MODE {
643 pub const offset: u32 = 0;
644 pub const mask: u32 = 0x07 << offset;
645 pub mod R {}
646 pub mod W {}
647 pub mod RW {
648 #[doc = "Select mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: LPSPI1"]
649 pub const ALT0: u32 = 0;
650 #[doc = "Select mux mode: ALT1 mux port: PIT_TRIGGER01 of instance: PIT"]
651 pub const ALT1: u32 = 0x01;
652 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1"]
653 pub const ALT2: u32 = 0x02;
654 #[doc = "Select mux mode: ALT3 mux port: KPP_ROW01 of instance: KPP"]
655 pub const ALT3: u32 = 0x03;
656 #[doc = "Select mux mode: ALT4 mux port: GPT2_CAPTURE1 of instance: GPT2"]
657 pub const ALT4: u32 = 0x04;
658 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO19 of instance: GPIOMUX"]
659 pub const ALT5: u32 = 0x05;
660 }
661 }
662 #[doc = "Software Input On Field."]
663 pub mod SION {
664 pub const offset: u32 = 4;
665 pub const mask: u32 = 0x01 << offset;
666 pub mod R {}
667 pub mod W {}
668 pub mod RW {
669 #[doc = "Input Path is determined by functionality"]
670 pub const DISABLED: u32 = 0;
671 #[doc = "Force input path of pad GPIO_AD_05"]
672 pub const ENABLED: u32 = 0x01;
673 }
674 }
675}
676#[doc = "SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register"]
677pub mod SW_MUX_CTL_PAD_GPIO_AD_04 {
678 #[doc = "MUX Mode Select Field."]
679 pub mod MUX_MODE {
680 pub const offset: u32 = 0;
681 pub const mask: u32 = 0x07 << offset;
682 pub mod R {}
683 pub mod W {}
684 pub mod RW {
685 #[doc = "Select mux mode: ALT0 mux port: LPSPI1_SDO of instance: LPSPI1"]
686 pub const ALT0: u32 = 0;
687 #[doc = "Select mux mode: ALT1 mux port: PIT_TRIGGER02 of instance: PIT"]
688 pub const ALT1: u32 = 0x01;
689 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1"]
690 pub const ALT2: u32 = 0x02;
691 #[doc = "Select mux mode: ALT3 mux port: KPP_COL02 of instance: KPP"]
692 pub const ALT3: u32 = 0x03;
693 #[doc = "Select mux mode: ALT4 mux port: GPT2_COMPARE1 of instance: GPT2"]
694 pub const ALT4: u32 = 0x04;
695 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO18 of instance: GPIOMUX"]
696 pub const ALT5: u32 = 0x05;
697 #[doc = "Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp"]
698 pub const ALT6: u32 = 0x06;
699 }
700 }
701 #[doc = "Software Input On Field."]
702 pub mod SION {
703 pub const offset: u32 = 4;
704 pub const mask: u32 = 0x01 << offset;
705 pub mod R {}
706 pub mod W {}
707 pub mod RW {
708 #[doc = "Input Path is determined by functionality"]
709 pub const DISABLED: u32 = 0;
710 #[doc = "Force input path of pad GPIO_AD_04"]
711 pub const ENABLED: u32 = 0x01;
712 }
713 }
714}
715#[doc = "SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register"]
716pub mod SW_MUX_CTL_PAD_GPIO_AD_03 {
717 #[doc = "MUX Mode Select Field."]
718 pub mod MUX_MODE {
719 pub const offset: u32 = 0;
720 pub const mask: u32 = 0x07 << offset;
721 pub mod R {}
722 pub mod W {}
723 pub mod RW {
724 #[doc = "Select mux mode: ALT0 mux port: LPSPI1_SDI of instance: LPSPI1"]
725 pub const ALT0: u32 = 0;
726 #[doc = "Select mux mode: ALT1 mux port: PIT_TRIGGER03 of instance: PIT"]
727 pub const ALT1: u32 = 0x01;
728 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1"]
729 pub const ALT2: u32 = 0x02;
730 #[doc = "Select mux mode: ALT3 mux port: KPP_ROW02 of instance: KPP"]
731 pub const ALT3: u32 = 0x03;
732 #[doc = "Select mux mode: ALT4 mux port: GPT2_CLK of instance: GPT2"]
733 pub const ALT4: u32 = 0x04;
734 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO17 of instance: GPIOMUX"]
735 pub const ALT5: u32 = 0x05;
736 #[doc = "Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_B of instance: snvs_hp"]
737 pub const ALT6: u32 = 0x06;
738 #[doc = "Select mux mode: ALT7 mux port: JTAG_DE_B of instance: JTAG"]
739 pub const ALT7: u32 = 0x07;
740 }
741 }
742 #[doc = "Software Input On Field."]
743 pub mod SION {
744 pub const offset: u32 = 4;
745 pub const mask: u32 = 0x01 << offset;
746 pub mod R {}
747 pub mod W {}
748 pub mod RW {
749 #[doc = "Input Path is determined by functionality"]
750 pub const DISABLED: u32 = 0;
751 #[doc = "Force input path of pad GPIO_AD_03"]
752 pub const ENABLED: u32 = 0x01;
753 }
754 }
755}
756#[doc = "SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register"]
757pub mod SW_MUX_CTL_PAD_GPIO_AD_02 {
758 #[doc = "MUX Mode Select Field."]
759 pub mod MUX_MODE {
760 pub const offset: u32 = 0;
761 pub const mask: u32 = 0x07 << offset;
762 pub mod R {}
763 pub mod W {}
764 pub mod RW {
765 #[doc = "Select mux mode: ALT0 mux port: LPUART4_TXD of instance: LPUART4"]
766 pub const ALT0: u32 = 0;
767 #[doc = "Select mux mode: ALT1 mux port: LPSPI1_PCS1 of instance: LPSPI1"]
768 pub const ALT1: u32 = 0x01;
769 #[doc = "Select mux mode: ALT2 mux port: WDOG2_B of instance: WDOG2"]
770 pub const ALT2: u32 = 0x02;
771 #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: LPI2C2"]
772 pub const ALT3: u32 = 0x03;
773 #[doc = "Select mux mode: ALT4 mux port: MQS_RIGHT of instance: MQS"]
774 pub const ALT4: u32 = 0x04;
775 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO16 of instance: GPIOMUX"]
776 pub const ALT5: u32 = 0x05;
777 #[doc = "Select mux mode: ALT7 mux port: ARM_CM7_TRACE_CLK of instance: cm7_mxrt"]
778 pub const ALT7: u32 = 0x07;
779 }
780 }
781 #[doc = "Software Input On Field."]
782 pub mod SION {
783 pub const offset: u32 = 4;
784 pub const mask: u32 = 0x01 << offset;
785 pub mod R {}
786 pub mod W {}
787 pub mod RW {
788 #[doc = "Input Path is determined by functionality"]
789 pub const DISABLED: u32 = 0;
790 #[doc = "Force input path of pad GPIO_AD_02"]
791 pub const ENABLED: u32 = 0x01;
792 }
793 }
794}
795#[doc = "SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register"]
796pub mod SW_MUX_CTL_PAD_GPIO_AD_01 {
797 #[doc = "MUX Mode Select Field."]
798 pub mod MUX_MODE {
799 pub const offset: u32 = 0;
800 pub const mask: u32 = 0x07 << offset;
801 pub mod R {}
802 pub mod W {}
803 pub mod RW {
804 #[doc = "Select mux mode: ALT0 mux port: LPUART4_RXD of instance: LPUART4"]
805 pub const ALT0: u32 = 0;
806 #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS1 of instance: LPSPI2"]
807 pub const ALT1: u32 = 0x01;
808 #[doc = "Select mux mode: ALT2 mux port: WDOG1_ANY of instance: WDOG1"]
809 pub const ALT2: u32 = 0x02;
810 #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: LPI2C2"]
811 pub const ALT3: u32 = 0x03;
812 #[doc = "Select mux mode: ALT4 mux port: MQS_LEFT of instance: MQS"]
813 pub const ALT4: u32 = 0x04;
814 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO15 of instance: GPIOMUX"]
815 pub const ALT5: u32 = 0x05;
816 #[doc = "Select mux mode: ALT6 mux port: USB_OTG1_OC of instance: USB"]
817 pub const ALT6: u32 = 0x06;
818 #[doc = "Select mux mode: ALT7 mux port: ARM_CM7_TRACE_SWO of instance: cm7_mxrt"]
819 pub const ALT7: u32 = 0x07;
820 }
821 }
822 #[doc = "Software Input On Field."]
823 pub mod SION {
824 pub const offset: u32 = 4;
825 pub const mask: u32 = 0x01 << offset;
826 pub mod R {}
827 pub mod W {}
828 pub mod RW {
829 #[doc = "Input Path is determined by functionality"]
830 pub const DISABLED: u32 = 0;
831 #[doc = "Force input path of pad GPIO_AD_01"]
832 pub const ENABLED: u32 = 0x01;
833 }
834 }
835}
836#[doc = "SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register"]
837pub mod SW_MUX_CTL_PAD_GPIO_AD_00 {
838 #[doc = "MUX Mode Select Field."]
839 pub mod MUX_MODE {
840 pub const offset: u32 = 0;
841 pub const mask: u32 = 0x07 << offset;
842 pub mod R {}
843 pub mod W {}
844 pub mod RW {
845 #[doc = "Select mux mode: ALT0 mux port: LPUART2_TXD of instance: LPUART2"]
846 pub const ALT0: u32 = 0;
847 #[doc = "Select mux mode: ALT1 mux port: LPSPI1_PCS2 of instance: LPSPI1"]
848 pub const ALT1: u32 = 0x01;
849 #[doc = "Select mux mode: ALT2 mux port: KPP_COL03 of instance: KPP"]
850 pub const ALT2: u32 = 0x02;
851 #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_PWR of instance: USB"]
852 pub const ALT3: u32 = 0x03;
853 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO20 of instance: FLEXIO1"]
854 pub const ALT4: u32 = 0x04;
855 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO14 of instance: GPIOMUX"]
856 pub const ALT5: u32 = 0x05;
857 #[doc = "Select mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: NMI_GLUE"]
858 pub const ALT6: u32 = 0x06;
859 #[doc = "Select mux mode: ALT7 mux port: ARM_CM7_TRACE00 of instance: cm7_mxrt"]
860 pub const ALT7: u32 = 0x07;
861 }
862 }
863 #[doc = "Software Input On Field."]
864 pub mod SION {
865 pub const offset: u32 = 4;
866 pub const mask: u32 = 0x01 << offset;
867 pub mod R {}
868 pub mod W {}
869 pub mod RW {
870 #[doc = "Input Path is determined by functionality"]
871 pub const DISABLED: u32 = 0;
872 #[doc = "Force input path of pad GPIO_AD_00"]
873 pub const ENABLED: u32 = 0x01;
874 }
875 }
876}
877#[doc = "SW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register"]
878pub mod SW_MUX_CTL_PAD_GPIO_SD_14 {
879 #[doc = "MUX Mode Select Field."]
880 pub mod MUX_MODE {
881 pub const offset: u32 = 0;
882 pub const mask: u32 = 0x01 << offset;
883 pub mod R {}
884 pub mod W {}
885 pub mod RW {
886 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: FLEXSPI"]
887 pub const ALT0: u32 = 0;
888 #[doc = "Select mux mode: ALT1 mux port: FLEXSPI_B_DQS of instance: FLEXSPI"]
889 pub const ALT1: u32 = 0x01;
890 }
891 }
892 #[doc = "Software Input On Field."]
893 pub mod SION {
894 pub const offset: u32 = 4;
895 pub const mask: u32 = 0x01 << offset;
896 pub mod R {}
897 pub mod W {}
898 pub mod RW {
899 #[doc = "Input Path is determined by functionality"]
900 pub const DISABLED: u32 = 0;
901 #[doc = "Force input path of pad GPIO_SD_14"]
902 pub const ENABLED: u32 = 0x01;
903 }
904 }
905}
906#[doc = "SW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register"]
907pub mod SW_MUX_CTL_PAD_GPIO_SD_13 {
908 #[doc = "MUX Mode Select Field."]
909 pub mod MUX_MODE {
910 pub const offset: u32 = 0;
911 pub const mask: u32 = 0x07 << offset;
912 pub mod R {}
913 pub mod W {}
914 pub mod RW {
915 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_B_SCLK of instance: FLEXSPI"]
916 pub const ALT0: u32 = 0;
917 #[doc = "Select mux mode: ALT1 mux port: SAI3_RX_BCLK of instance: SAI3"]
918 pub const ALT1: u32 = 0x01;
919 #[doc = "Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mxrt"]
920 pub const ALT2: u32 = 0x02;
921 #[doc = "Select mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: CCM"]
922 pub const ALT3: u32 = 0x03;
923 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO19 of instance: FLEXIO1"]
924 pub const ALT4: u32 = 0x04;
925 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: GPIO2"]
926 pub const ALT5: u32 = 0x05;
927 #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: SRC"]
928 pub const ALT6: u32 = 0x06;
929 }
930 }
931 #[doc = "Software Input On Field."]
932 pub mod SION {
933 pub const offset: u32 = 4;
934 pub const mask: u32 = 0x01 << offset;
935 pub mod R {}
936 pub mod W {}
937 pub mod RW {
938 #[doc = "Input Path is determined by functionality"]
939 pub const DISABLED: u32 = 0;
940 #[doc = "Force input path of pad GPIO_SD_13"]
941 pub const ENABLED: u32 = 0x01;
942 }
943 }
944}
945#[doc = "SW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register"]
946pub mod SW_MUX_CTL_PAD_GPIO_SD_12 {
947 #[doc = "MUX Mode Select Field."]
948 pub mod MUX_MODE {
949 pub const offset: u32 = 0;
950 pub const mask: u32 = 0x07 << offset;
951 pub mod R {}
952 pub mod W {}
953 pub mod RW {
954 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: FLEXSPI"]
955 pub const ALT0: u32 = 0;
956 #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: LPSPI2"]
957 pub const ALT1: u32 = 0x01;
958 #[doc = "Select mux mode: ALT2 mux port: LPUART1_TXD of instance: LPUART1"]
959 pub const ALT2: u32 = 0x02;
960 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO18 of instance: FLEXIO1"]
961 pub const ALT4: u32 = 0x04;
962 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: GPIO2"]
963 pub const ALT5: u32 = 0x05;
964 #[doc = "Select mux mode: ALT6 mux port: WDOG2_RST_B_DEB of instance: WDOG2"]
965 pub const ALT6: u32 = 0x06;
966 }
967 }
968 #[doc = "Software Input On Field."]
969 pub mod SION {
970 pub const offset: u32 = 4;
971 pub const mask: u32 = 0x01 << offset;
972 pub mod R {}
973 pub mod W {}
974 pub mod RW {
975 #[doc = "Input Path is determined by functionality"]
976 pub const DISABLED: u32 = 0;
977 #[doc = "Force input path of pad GPIO_SD_12"]
978 pub const ENABLED: u32 = 0x01;
979 }
980 }
981}
982#[doc = "SW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register"]
983pub mod SW_MUX_CTL_PAD_GPIO_SD_11 {
984 #[doc = "MUX Mode Select Field."]
985 pub mod MUX_MODE {
986 pub const offset: u32 = 0;
987 pub const mask: u32 = 0x07 << offset;
988 pub mod R {}
989 pub mod W {}
990 pub mod RW {
991 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_DATA3 of instance: FLEXSPI"]
992 pub const ALT0: u32 = 0;
993 #[doc = "Select mux mode: ALT1 mux port: LPSPI2_SCK of instance: LPSPI2"]
994 pub const ALT1: u32 = 0x01;
995 #[doc = "Select mux mode: ALT2 mux port: LPUART1_RXD of instance: LPUART1"]
996 pub const ALT2: u32 = 0x02;
997 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO17 of instance: FLEXIO1"]
998 pub const ALT4: u32 = 0x04;
999 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: GPIO2"]
1000 pub const ALT5: u32 = 0x05;
1001 #[doc = "Select mux mode: ALT6 mux port: WDOG1_RST_B_DEB of instance: WDOG1"]
1002 pub const ALT6: u32 = 0x06;
1003 }
1004 }
1005 #[doc = "Software Input On Field."]
1006 pub mod SION {
1007 pub const offset: u32 = 4;
1008 pub const mask: u32 = 0x01 << offset;
1009 pub mod R {}
1010 pub mod W {}
1011 pub mod RW {
1012 #[doc = "Input Path is determined by functionality"]
1013 pub const DISABLED: u32 = 0;
1014 #[doc = "Force input path of pad GPIO_SD_11"]
1015 pub const ENABLED: u32 = 0x01;
1016 }
1017 }
1018}
1019#[doc = "SW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register"]
1020pub mod SW_MUX_CTL_PAD_GPIO_SD_10 {
1021 #[doc = "MUX Mode Select Field."]
1022 pub mod MUX_MODE {
1023 pub const offset: u32 = 0;
1024 pub const mask: u32 = 0x07 << offset;
1025 pub mod R {}
1026 pub mod W {}
1027 pub mod RW {
1028 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_SCLK of instance: FLEXSPI"]
1029 pub const ALT0: u32 = 0;
1030 #[doc = "Select mux mode: ALT1 mux port: LPSPI2_SDO of instance: LPSPI2"]
1031 pub const ALT1: u32 = 0x01;
1032 #[doc = "Select mux mode: ALT2 mux port: LPUART2_TXD of instance: LPUART2"]
1033 pub const ALT2: u32 = 0x02;
1034 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO16 of instance: FLEXIO1"]
1035 pub const ALT4: u32 = 0x04;
1036 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: GPIO2"]
1037 pub const ALT5: u32 = 0x05;
1038 }
1039 }
1040 #[doc = "Software Input On Field."]
1041 pub mod SION {
1042 pub const offset: u32 = 4;
1043 pub const mask: u32 = 0x01 << offset;
1044 pub mod R {}
1045 pub mod W {}
1046 pub mod RW {
1047 #[doc = "Input Path is determined by functionality"]
1048 pub const DISABLED: u32 = 0;
1049 #[doc = "Force input path of pad GPIO_SD_10"]
1050 pub const ENABLED: u32 = 0x01;
1051 }
1052 }
1053}
1054#[doc = "SW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register"]
1055pub mod SW_MUX_CTL_PAD_GPIO_SD_09 {
1056 #[doc = "MUX Mode Select Field."]
1057 pub mod MUX_MODE {
1058 pub const offset: u32 = 0;
1059 pub const mask: u32 = 0x07 << offset;
1060 pub mod R {}
1061 pub mod W {}
1062 pub mod RW {
1063 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_DATA0 of instance: FLEXSPI"]
1064 pub const ALT0: u32 = 0;
1065 #[doc = "Select mux mode: ALT1 mux port: LPSPI2_SDI of instance: LPSPI2"]
1066 pub const ALT1: u32 = 0x01;
1067 #[doc = "Select mux mode: ALT2 mux port: LPUART2_RXD of instance: LPUART2"]
1068 pub const ALT2: u32 = 0x02;
1069 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO15 of instance: FLEXIO1"]
1070 pub const ALT4: u32 = 0x04;
1071 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: GPIO2"]
1072 pub const ALT5: u32 = 0x05;
1073 }
1074 }
1075 #[doc = "Software Input On Field."]
1076 pub mod SION {
1077 pub const offset: u32 = 4;
1078 pub const mask: u32 = 0x01 << offset;
1079 pub mod R {}
1080 pub mod W {}
1081 pub mod RW {
1082 #[doc = "Input Path is determined by functionality"]
1083 pub const DISABLED: u32 = 0;
1084 #[doc = "Force input path of pad GPIO_SD_09"]
1085 pub const ENABLED: u32 = 0x01;
1086 }
1087 }
1088}
1089#[doc = "SW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register"]
1090pub mod SW_MUX_CTL_PAD_GPIO_SD_08 {
1091 #[doc = "MUX Mode Select Field."]
1092 pub mod MUX_MODE {
1093 pub const offset: u32 = 0;
1094 pub const mask: u32 = 0x07 << offset;
1095 pub mod R {}
1096 pub mod W {}
1097 pub mod RW {
1098 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_DATA2 of instance: FLEXSPI"]
1099 pub const ALT0: u32 = 0;
1100 #[doc = "Select mux mode: ALT1 mux port: LPI2C2_SCL of instance: LPI2C2"]
1101 pub const ALT1: u32 = 0x01;
1102 #[doc = "Select mux mode: ALT2 mux port: LPSPI1_SCK of instance: LPSPI1"]
1103 pub const ALT2: u32 = 0x02;
1104 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO14 of instance: FLEXIO1"]
1105 pub const ALT4: u32 = 0x04;
1106 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: GPIO2"]
1107 pub const ALT5: u32 = 0x05;
1108 }
1109 }
1110 #[doc = "Software Input On Field."]
1111 pub mod SION {
1112 pub const offset: u32 = 4;
1113 pub const mask: u32 = 0x01 << offset;
1114 pub mod R {}
1115 pub mod W {}
1116 pub mod RW {
1117 #[doc = "Input Path is determined by functionality"]
1118 pub const DISABLED: u32 = 0;
1119 #[doc = "Force input path of pad GPIO_SD_08"]
1120 pub const ENABLED: u32 = 0x01;
1121 }
1122 }
1123}
1124#[doc = "SW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register"]
1125pub mod SW_MUX_CTL_PAD_GPIO_SD_07 {
1126 #[doc = "MUX Mode Select Field."]
1127 pub mod MUX_MODE {
1128 pub const offset: u32 = 0;
1129 pub const mask: u32 = 0x07 << offset;
1130 pub mod R {}
1131 pub mod W {}
1132 pub mod RW {
1133 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_DATA1 of instance: FLEXSPI"]
1134 pub const ALT0: u32 = 0;
1135 #[doc = "Select mux mode: ALT1 mux port: LPI2C2_SDA of instance: LPI2C2"]
1136 pub const ALT1: u32 = 0x01;
1137 #[doc = "Select mux mode: ALT2 mux port: LPSPI1_PCS0 of instance: LPSPI1"]
1138 pub const ALT2: u32 = 0x02;
1139 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO13 of instance: FLEXIO1"]
1140 pub const ALT4: u32 = 0x04;
1141 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: GPIO2"]
1142 pub const ALT5: u32 = 0x05;
1143 }
1144 }
1145 #[doc = "Software Input On Field."]
1146 pub mod SION {
1147 pub const offset: u32 = 4;
1148 pub const mask: u32 = 0x01 << offset;
1149 pub mod R {}
1150 pub mod W {}
1151 pub mod RW {
1152 #[doc = "Input Path is determined by functionality"]
1153 pub const DISABLED: u32 = 0;
1154 #[doc = "Force input path of pad GPIO_SD_07"]
1155 pub const ENABLED: u32 = 0x01;
1156 }
1157 }
1158}
1159#[doc = "SW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register"]
1160pub mod SW_MUX_CTL_PAD_GPIO_SD_06 {
1161 #[doc = "MUX Mode Select Field."]
1162 pub mod MUX_MODE {
1163 pub const offset: u32 = 0;
1164 pub const mask: u32 = 0x07 << offset;
1165 pub mod R {}
1166 pub mod W {}
1167 pub mod RW {
1168 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_SS0_B of instance: FLEXSPI"]
1169 pub const ALT0: u32 = 0;
1170 #[doc = "Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1"]
1171 pub const ALT1: u32 = 0x01;
1172 #[doc = "Select mux mode: ALT2 mux port: LPSPI1_SDO of instance: LPSPI1"]
1173 pub const ALT2: u32 = 0x02;
1174 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO12 of instance: FLEXIO1"]
1175 pub const ALT4: u32 = 0x04;
1176 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: GPIO2"]
1177 pub const ALT5: u32 = 0x05;
1178 }
1179 }
1180 #[doc = "Software Input On Field."]
1181 pub mod SION {
1182 pub const offset: u32 = 4;
1183 pub const mask: u32 = 0x01 << offset;
1184 pub mod R {}
1185 pub mod W {}
1186 pub mod RW {
1187 #[doc = "Input Path is determined by functionality"]
1188 pub const DISABLED: u32 = 0;
1189 #[doc = "Force input path of pad GPIO_SD_06"]
1190 pub const ENABLED: u32 = 0x01;
1191 }
1192 }
1193}
1194#[doc = "SW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register"]
1195pub mod SW_MUX_CTL_PAD_GPIO_SD_05 {
1196 #[doc = "MUX Mode Select Field."]
1197 pub mod MUX_MODE {
1198 pub const offset: u32 = 0;
1199 pub const mask: u32 = 0x07 << offset;
1200 pub mod R {}
1201 pub mod W {}
1202 pub mod RW {
1203 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_A_SS1_B of instance: FLEXSPI"]
1204 pub const ALT0: u32 = 0;
1205 #[doc = "Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1"]
1206 pub const ALT1: u32 = 0x01;
1207 #[doc = "Select mux mode: ALT2 mux port: LPSPI1_SDI of instance: LPSPI1"]
1208 pub const ALT2: u32 = 0x02;
1209 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO11 of instance: FLEXIO1"]
1210 pub const ALT4: u32 = 0x04;
1211 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: GPIO2"]
1212 pub const ALT5: u32 = 0x05;
1213 }
1214 }
1215 #[doc = "Software Input On Field."]
1216 pub mod SION {
1217 pub const offset: u32 = 4;
1218 pub const mask: u32 = 0x01 << offset;
1219 pub mod R {}
1220 pub mod W {}
1221 pub mod RW {
1222 #[doc = "Input Path is determined by functionality"]
1223 pub const DISABLED: u32 = 0;
1224 #[doc = "Force input path of pad GPIO_SD_05"]
1225 pub const ENABLED: u32 = 0x01;
1226 }
1227 }
1228}
1229#[doc = "SW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register"]
1230pub mod SW_MUX_CTL_PAD_GPIO_SD_04 {
1231 #[doc = "MUX Mode Select Field."]
1232 pub mod MUX_MODE {
1233 pub const offset: u32 = 0;
1234 pub const mask: u32 = 0x07 << offset;
1235 pub mod R {}
1236 pub mod W {}
1237 pub mod RW {
1238 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_B_DATA03 of instance: FLEXSPI"]
1239 pub const ALT0: u32 = 0;
1240 #[doc = "Select mux mode: ALT1 mux port: SAI3_RX_SYNC of instance: SAI3"]
1241 pub const ALT1: u32 = 0x01;
1242 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1"]
1243 pub const ALT2: u32 = 0x02;
1244 #[doc = "Select mux mode: ALT3 mux port: CCM_WAIT of instance: CCM"]
1245 pub const ALT3: u32 = 0x03;
1246 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO10 of instance: FLEXIO1"]
1247 pub const ALT4: u32 = 0x04;
1248 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: GPIO2"]
1249 pub const ALT5: u32 = 0x05;
1250 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_MODE00 of instance: SRC"]
1251 pub const ALT6: u32 = 0x06;
1252 }
1253 }
1254 #[doc = "Software Input On Field."]
1255 pub mod SION {
1256 pub const offset: u32 = 4;
1257 pub const mask: u32 = 0x01 << offset;
1258 pub mod R {}
1259 pub mod W {}
1260 pub mod RW {
1261 #[doc = "Input Path is determined by functionality"]
1262 pub const DISABLED: u32 = 0;
1263 #[doc = "Force input path of pad GPIO_SD_04"]
1264 pub const ENABLED: u32 = 0x01;
1265 }
1266 }
1267}
1268#[doc = "SW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register"]
1269pub mod SW_MUX_CTL_PAD_GPIO_SD_03 {
1270 #[doc = "MUX Mode Select Field."]
1271 pub mod MUX_MODE {
1272 pub const offset: u32 = 0;
1273 pub const mask: u32 = 0x07 << offset;
1274 pub mod R {}
1275 pub mod W {}
1276 pub mod RW {
1277 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_B_DATA00 of instance: FLEXSPI"]
1278 pub const ALT0: u32 = 0;
1279 #[doc = "Select mux mode: ALT1 mux port: SAI3_RX_DATA of instance: SAI3"]
1280 pub const ALT1: u32 = 0x01;
1281 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1"]
1282 pub const ALT2: u32 = 0x02;
1283 #[doc = "Select mux mode: ALT3 mux port: CCM_REF_EN_B of instance: CCM"]
1284 pub const ALT3: u32 = 0x03;
1285 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO09 of instance: FLEXIO1"]
1286 pub const ALT4: u32 = 0x04;
1287 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: GPIO2"]
1288 pub const ALT5: u32 = 0x05;
1289 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_MODE01 of instance: SRC"]
1290 pub const ALT6: u32 = 0x06;
1291 }
1292 }
1293 #[doc = "Software Input On Field."]
1294 pub mod SION {
1295 pub const offset: u32 = 4;
1296 pub const mask: u32 = 0x01 << offset;
1297 pub mod R {}
1298 pub mod W {}
1299 pub mod RW {
1300 #[doc = "Input Path is determined by functionality"]
1301 pub const DISABLED: u32 = 0;
1302 #[doc = "Force input path of pad GPIO_SD_03"]
1303 pub const ENABLED: u32 = 0x01;
1304 }
1305 }
1306}
1307#[doc = "SW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register"]
1308pub mod SW_MUX_CTL_PAD_GPIO_SD_02 {
1309 #[doc = "MUX Mode Select Field."]
1310 pub mod MUX_MODE {
1311 pub const offset: u32 = 0;
1312 pub const mask: u32 = 0x07 << offset;
1313 pub mod R {}
1314 pub mod W {}
1315 pub mod RW {
1316 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_B_DATA02 of instance: FLEXSPI"]
1317 pub const ALT0: u32 = 0;
1318 #[doc = "Select mux mode: ALT1 mux port: SAI3_TX_DATA of instance: SAI3"]
1319 pub const ALT1: u32 = 0x01;
1320 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1"]
1321 pub const ALT2: u32 = 0x02;
1322 #[doc = "Select mux mode: ALT3 mux port: CCM_CLKO1 of instance: CCM"]
1323 pub const ALT3: u32 = 0x03;
1324 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO08 of instance: FLEXIO1"]
1325 pub const ALT4: u32 = 0x04;
1326 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: GPIO2"]
1327 pub const ALT5: u32 = 0x05;
1328 #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: SRC"]
1329 pub const ALT6: u32 = 0x06;
1330 }
1331 }
1332 #[doc = "Software Input On Field."]
1333 pub mod SION {
1334 pub const offset: u32 = 4;
1335 pub const mask: u32 = 0x01 << offset;
1336 pub mod R {}
1337 pub mod W {}
1338 pub mod RW {
1339 #[doc = "Input Path is determined by functionality"]
1340 pub const DISABLED: u32 = 0;
1341 #[doc = "Force input path of pad GPIO_SD_02"]
1342 pub const ENABLED: u32 = 0x01;
1343 }
1344 }
1345}
1346#[doc = "SW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register"]
1347pub mod SW_MUX_CTL_PAD_GPIO_SD_01 {
1348 #[doc = "MUX Mode Select Field."]
1349 pub mod MUX_MODE {
1350 pub const offset: u32 = 0;
1351 pub const mask: u32 = 0x07 << offset;
1352 pub mod R {}
1353 pub mod W {}
1354 pub mod RW {
1355 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_B_DATA01 of instance: FLEXSPI"]
1356 pub const ALT0: u32 = 0;
1357 #[doc = "Select mux mode: ALT1 mux port: SAI3_TX_BCLK of instance: SAI3"]
1358 pub const ALT1: u32 = 0x01;
1359 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1"]
1360 pub const ALT2: u32 = 0x02;
1361 #[doc = "Select mux mode: ALT3 mux port: CCM_CLKO2 of instance: CCM"]
1362 pub const ALT3: u32 = 0x03;
1363 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO07 of instance: FLEXIO1"]
1364 pub const ALT4: u32 = 0x04;
1365 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: GPIO2"]
1366 pub const ALT5: u32 = 0x05;
1367 #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: SRC"]
1368 pub const ALT6: u32 = 0x06;
1369 }
1370 }
1371 #[doc = "Software Input On Field."]
1372 pub mod SION {
1373 pub const offset: u32 = 4;
1374 pub const mask: u32 = 0x01 << offset;
1375 pub mod R {}
1376 pub mod W {}
1377 pub mod RW {
1378 #[doc = "Input Path is determined by functionality"]
1379 pub const DISABLED: u32 = 0;
1380 #[doc = "Force input path of pad GPIO_SD_01"]
1381 pub const ENABLED: u32 = 0x01;
1382 }
1383 }
1384}
1385#[doc = "SW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register"]
1386pub mod SW_MUX_CTL_PAD_GPIO_SD_00 {
1387 #[doc = "MUX Mode Select Field."]
1388 pub mod MUX_MODE {
1389 pub const offset: u32 = 0;
1390 pub const mask: u32 = 0x07 << offset;
1391 pub mod R {}
1392 pub mod W {}
1393 pub mod RW {
1394 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_B_SS0_B of instance: FLEXSPI"]
1395 pub const ALT0: u32 = 0;
1396 #[doc = "Select mux mode: ALT1 mux port: SAI3_TX_SYNC of instance: SAI3"]
1397 pub const ALT1: u32 = 0x01;
1398 #[doc = "Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mxrt"]
1399 pub const ALT2: u32 = 0x02;
1400 #[doc = "Select mux mode: ALT3 mux port: CCM_STOP of instance: CCM"]
1401 pub const ALT3: u32 = 0x03;
1402 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO06 of instance: FLEXIO1"]
1403 pub const ALT4: u32 = 0x04;
1404 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: GPIO2"]
1405 pub const ALT5: u32 = 0x05;
1406 #[doc = "Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: SRC"]
1407 pub const ALT6: u32 = 0x06;
1408 }
1409 }
1410 #[doc = "Software Input On Field."]
1411 pub mod SION {
1412 pub const offset: u32 = 4;
1413 pub const mask: u32 = 0x01 << offset;
1414 pub mod R {}
1415 pub mod W {}
1416 pub mod RW {
1417 #[doc = "Input Path is determined by functionality"]
1418 pub const DISABLED: u32 = 0;
1419 #[doc = "Force input path of pad GPIO_SD_00"]
1420 pub const ENABLED: u32 = 0x01;
1421 }
1422 }
1423}
1424#[doc = "SW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register"]
1425pub mod SW_MUX_CTL_PAD_GPIO_13 {
1426 #[doc = "MUX Mode Select Field."]
1427 pub mod MUX_MODE {
1428 pub const offset: u32 = 0;
1429 pub const mask: u32 = 0x07 << offset;
1430 pub mod R {}
1431 pub mod W {}
1432 pub mod RW {
1433 #[doc = "Select mux mode: ALT0 mux port: LPUART2_RXD of instance: LPUART2"]
1434 pub const ALT0: u32 = 0;
1435 #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS2 of instance: LPSPI2"]
1436 pub const ALT1: u32 = 0x01;
1437 #[doc = "Select mux mode: ALT2 mux port: KPP_ROW03 of instance: KPP"]
1438 pub const ALT2: u32 = 0x02;
1439 #[doc = "Select mux mode: ALT3 mux port: OTG1_ID of instance: anatop"]
1440 pub const ALT3: u32 = 0x03;
1441 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO05 of instance: FLEXIO1"]
1442 pub const ALT4: u32 = 0x04;
1443 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO13 of instance: GPIOMUX"]
1444 pub const ALT5: u32 = 0x05;
1445 #[doc = "Select mux mode: ALT6 mux port: SPDIF_LOCK of instance: SPDIF"]
1446 pub const ALT6: u32 = 0x06;
1447 #[doc = "Select mux mode: ALT7 mux port: ARM_CM7_TRACE01 of instance: cm7_mxrt"]
1448 pub const ALT7: u32 = 0x07;
1449 }
1450 }
1451 #[doc = "Software Input On Field."]
1452 pub mod SION {
1453 pub const offset: u32 = 4;
1454 pub const mask: u32 = 0x01 << offset;
1455 pub mod R {}
1456 pub mod W {}
1457 pub mod RW {
1458 #[doc = "Input Path is determined by functionality"]
1459 pub const DISABLED: u32 = 0;
1460 #[doc = "Force input path of pad GPIO_13"]
1461 pub const ENABLED: u32 = 0x01;
1462 }
1463 }
1464}
1465#[doc = "SW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register"]
1466pub mod SW_MUX_CTL_PAD_GPIO_12 {
1467 #[doc = "MUX Mode Select Field."]
1468 pub mod MUX_MODE {
1469 pub const offset: u32 = 0;
1470 pub const mask: u32 = 0x07 << offset;
1471 pub mod R {}
1472 pub mod W {}
1473 pub mod RW {
1474 #[doc = "Select mux mode: ALT0 mux port: LPUART3_TXD of instance: LPUART3"]
1475 pub const ALT0: u32 = 0;
1476 #[doc = "Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1"]
1477 pub const ALT1: u32 = 0x01;
1478 #[doc = "Select mux mode: ALT2 mux port: KPP_COL00 of instance: KPP"]
1479 pub const ALT2: u32 = 0x02;
1480 #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: USB"]
1481 pub const ALT3: u32 = 0x03;
1482 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO04 of instance: FLEXIO1"]
1483 pub const ALT4: u32 = 0x04;
1484 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO12 of instance: GPIOMUX"]
1485 pub const ALT5: u32 = 0x05;
1486 #[doc = "Select mux mode: ALT6 mux port: SPDIF_EXT_CLK of instance: SPDIF"]
1487 pub const ALT6: u32 = 0x06;
1488 #[doc = "Select mux mode: ALT7 mux port: ARM_CM7_TRACE02 of instance: cm7_mxrt"]
1489 pub const ALT7: u32 = 0x07;
1490 }
1491 }
1492 #[doc = "Software Input On Field."]
1493 pub mod SION {
1494 pub const offset: u32 = 4;
1495 pub const mask: u32 = 0x01 << offset;
1496 pub mod R {}
1497 pub mod W {}
1498 pub mod RW {
1499 #[doc = "Input Path is determined by functionality"]
1500 pub const DISABLED: u32 = 0;
1501 #[doc = "Force input path of pad GPIO_12"]
1502 pub const ENABLED: u32 = 0x01;
1503 }
1504 }
1505}
1506#[doc = "SW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register"]
1507pub mod SW_MUX_CTL_PAD_GPIO_11 {
1508 #[doc = "MUX Mode Select Field."]
1509 pub mod MUX_MODE {
1510 pub const offset: u32 = 0;
1511 pub const mask: u32 = 0x07 << offset;
1512 pub mod R {}
1513 pub mod W {}
1514 pub mod RW {
1515 #[doc = "Select mux mode: ALT0 mux port: LPUART3_RXD of instance: LPUART3"]
1516 pub const ALT0: u32 = 0;
1517 #[doc = "Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1"]
1518 pub const ALT1: u32 = 0x01;
1519 #[doc = "Select mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP"]
1520 pub const ALT2: u32 = 0x02;
1521 #[doc = "Select mux mode: ALT3 mux port: FLEXSPI_B_SS1_B of instance: FLEXSPI"]
1522 pub const ALT3: u32 = 0x03;
1523 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO03 of instance: FLEXIO1"]
1524 pub const ALT4: u32 = 0x04;
1525 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO11 of instance: GPIOMUX"]
1526 pub const ALT5: u32 = 0x05;
1527 #[doc = "Select mux mode: ALT6 mux port: SPDIF_OUT of instance: SPDIF"]
1528 pub const ALT6: u32 = 0x06;
1529 #[doc = "Select mux mode: ALT7 mux port: ARM_CM7_TRACE03 of instance: cm7_mxrt"]
1530 pub const ALT7: u32 = 0x07;
1531 }
1532 }
1533 #[doc = "Software Input On Field."]
1534 pub mod SION {
1535 pub const offset: u32 = 4;
1536 pub const mask: u32 = 0x01 << offset;
1537 pub mod R {}
1538 pub mod W {}
1539 pub mod RW {
1540 #[doc = "Input Path is determined by functionality"]
1541 pub const DISABLED: u32 = 0;
1542 #[doc = "Force input path of pad GPIO_11"]
1543 pub const ENABLED: u32 = 0x01;
1544 }
1545 }
1546}
1547#[doc = "SW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register"]
1548pub mod SW_MUX_CTL_PAD_GPIO_10 {
1549 #[doc = "MUX Mode Select Field."]
1550 pub mod MUX_MODE {
1551 pub const offset: u32 = 0;
1552 pub const mask: u32 = 0x07 << offset;
1553 pub mod R {}
1554 pub mod W {}
1555 pub mod RW {
1556 #[doc = "Select mux mode: ALT0 mux port: LPUART1_TXD of instance: LPUART1"]
1557 pub const ALT0: u32 = 0;
1558 #[doc = "Select mux mode: ALT1 mux port: LPI2C1_HREQ of instance: LPI2C1"]
1559 pub const ALT1: u32 = 0x01;
1560 #[doc = "Select mux mode: ALT2 mux port: EWM_OUT_B of instance: EWM"]
1561 pub const ALT2: u32 = 0x02;
1562 #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: LPI2C2"]
1563 pub const ALT3: u32 = 0x03;
1564 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO02 of instance: FLEXIO1"]
1565 pub const ALT4: u32 = 0x04;
1566 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO10 of instance: GPIOMUX"]
1567 pub const ALT5: u32 = 0x05;
1568 #[doc = "Select mux mode: ALT6 mux port: SPDIF_IN of instance: SPDIF"]
1569 pub const ALT6: u32 = 0x06;
1570 }
1571 }
1572 #[doc = "Software Input On Field."]
1573 pub mod SION {
1574 pub const offset: u32 = 4;
1575 pub const mask: u32 = 0x01 << offset;
1576 pub mod R {}
1577 pub mod W {}
1578 pub mod RW {
1579 #[doc = "Input Path is determined by functionality"]
1580 pub const DISABLED: u32 = 0;
1581 #[doc = "Force input path of pad GPIO_10"]
1582 pub const ENABLED: u32 = 0x01;
1583 }
1584 }
1585}
1586#[doc = "SW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register"]
1587pub mod SW_MUX_CTL_PAD_GPIO_09 {
1588 #[doc = "MUX Mode Select Field."]
1589 pub mod MUX_MODE {
1590 pub const offset: u32 = 0;
1591 pub const mask: u32 = 0x07 << offset;
1592 pub mod R {}
1593 pub mod W {}
1594 pub mod RW {
1595 #[doc = "Select mux mode: ALT0 mux port: LPUART1_RXD of instance: LPUART1"]
1596 pub const ALT0: u32 = 0;
1597 #[doc = "Select mux mode: ALT1 mux port: WDOG1_B of instance: WDOG1"]
1598 pub const ALT1: u32 = 0x01;
1599 #[doc = "Select mux mode: ALT2 mux port: FLEXSPI_A_SS1_B of instance: FLEXSPI"]
1600 pub const ALT2: u32 = 0x02;
1601 #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: LPI2C2"]
1602 pub const ALT3: u32 = 0x03;
1603 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO01 of instance: FLEXIO1"]
1604 pub const ALT4: u32 = 0x04;
1605 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO09 of instance: GPIOMUX"]
1606 pub const ALT5: u32 = 0x05;
1607 #[doc = "Select mux mode: ALT6 mux port: SPDIF_SR_CLK of instance: SPDIF"]
1608 pub const ALT6: u32 = 0x06;
1609 }
1610 }
1611 #[doc = "Software Input On Field."]
1612 pub mod SION {
1613 pub const offset: u32 = 4;
1614 pub const mask: u32 = 0x01 << offset;
1615 pub mod R {}
1616 pub mod W {}
1617 pub mod RW {
1618 #[doc = "Input Path is determined by functionality"]
1619 pub const DISABLED: u32 = 0;
1620 #[doc = "Force input path of pad GPIO_09"]
1621 pub const ENABLED: u32 = 0x01;
1622 }
1623 }
1624}
1625#[doc = "SW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register"]
1626pub mod SW_MUX_CTL_PAD_GPIO_08 {
1627 #[doc = "MUX Mode Select Field."]
1628 pub mod MUX_MODE {
1629 pub const offset: u32 = 0;
1630 pub const mask: u32 = 0x07 << offset;
1631 pub mod R {}
1632 pub mod W {}
1633 pub mod RW {
1634 #[doc = "Select mux mode: ALT0 mux port: SAI1_MCLK of instance: SAI1"]
1635 pub const ALT0: u32 = 0;
1636 #[doc = "Select mux mode: ALT1 mux port: GPT1_CLK of instance: GPT1"]
1637 pub const ALT1: u32 = 0x01;
1638 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1"]
1639 pub const ALT2: u32 = 0x02;
1640 #[doc = "Select mux mode: ALT3 mux port: LPUART3_TXD of instance: LPUART3"]
1641 pub const ALT3: u32 = 0x03;
1642 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_IO00 of instance: FLEXIO1"]
1643 pub const ALT4: u32 = 0x04;
1644 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO08 of instance: GPIOMUX"]
1645 pub const ALT5: u32 = 0x05;
1646 #[doc = "Select mux mode: ALT6 mux port: LPUART1_CTS_B of instance: LPUART1"]
1647 pub const ALT6: u32 = 0x06;
1648 }
1649 }
1650 #[doc = "Software Input On Field."]
1651 pub mod SION {
1652 pub const offset: u32 = 4;
1653 pub const mask: u32 = 0x01 << offset;
1654 pub mod R {}
1655 pub mod W {}
1656 pub mod RW {
1657 #[doc = "Input Path is determined by functionality"]
1658 pub const DISABLED: u32 = 0;
1659 #[doc = "Force input path of pad GPIO_08"]
1660 pub const ENABLED: u32 = 0x01;
1661 }
1662 }
1663}
1664#[doc = "SW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register"]
1665pub mod SW_MUX_CTL_PAD_GPIO_07 {
1666 #[doc = "MUX Mode Select Field."]
1667 pub mod MUX_MODE {
1668 pub const offset: u32 = 0;
1669 pub const mask: u32 = 0x07 << offset;
1670 pub mod R {}
1671 pub mod W {}
1672 pub mod RW {
1673 #[doc = "Select mux mode: ALT0 mux port: SAI1_TX_SYNC of instance: SAI1"]
1674 pub const ALT0: u32 = 0;
1675 #[doc = "Select mux mode: ALT1 mux port: GPT1_COMPARE1 of instance: GPT1"]
1676 pub const ALT1: u32 = 0x01;
1677 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1"]
1678 pub const ALT2: u32 = 0x02;
1679 #[doc = "Select mux mode: ALT3 mux port: LPUART3_RXD of instance: LPUART3"]
1680 pub const ALT3: u32 = 0x03;
1681 #[doc = "Select mux mode: ALT4 mux port: SPDIF_LOCK of instance: SPDIF"]
1682 pub const ALT4: u32 = 0x04;
1683 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO07 of instance: GPIOMUX"]
1684 pub const ALT5: u32 = 0x05;
1685 #[doc = "Select mux mode: ALT6 mux port: LPUART1_RTS_B of instance: LPUART1"]
1686 pub const ALT6: u32 = 0x06;
1687 }
1688 }
1689 #[doc = "Software Input On Field."]
1690 pub mod SION {
1691 pub const offset: u32 = 4;
1692 pub const mask: u32 = 0x01 << offset;
1693 pub mod R {}
1694 pub mod W {}
1695 pub mod RW {
1696 #[doc = "Input Path is determined by functionality"]
1697 pub const DISABLED: u32 = 0;
1698 #[doc = "Force input path of pad GPIO_07"]
1699 pub const ENABLED: u32 = 0x01;
1700 }
1701 }
1702}
1703#[doc = "SW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register"]
1704pub mod SW_MUX_CTL_PAD_GPIO_06 {
1705 #[doc = "MUX Mode Select Field."]
1706 pub mod MUX_MODE {
1707 pub const offset: u32 = 0;
1708 pub const mask: u32 = 0x07 << offset;
1709 pub mod R {}
1710 pub mod W {}
1711 pub mod RW {
1712 #[doc = "Select mux mode: ALT0 mux port: SAI1_TX_BCLK of instance: SAI1"]
1713 pub const ALT0: u32 = 0;
1714 #[doc = "Select mux mode: ALT1 mux port: GPT1_CAPTURE1 of instance: GPT1"]
1715 pub const ALT1: u32 = 0x01;
1716 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1"]
1717 pub const ALT2: u32 = 0x02;
1718 #[doc = "Select mux mode: ALT3 mux port: LPUART4_TXD of instance: LPUART4"]
1719 pub const ALT3: u32 = 0x03;
1720 #[doc = "Select mux mode: ALT4 mux port: SPDIF_EXT_CLK of instance: SPDIF"]
1721 pub const ALT4: u32 = 0x04;
1722 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO06 of instance: GPIOMUX"]
1723 pub const ALT5: u32 = 0x05;
1724 }
1725 }
1726 #[doc = "Software Input On Field."]
1727 pub mod SION {
1728 pub const offset: u32 = 4;
1729 pub const mask: u32 = 0x01 << offset;
1730 pub mod R {}
1731 pub mod W {}
1732 pub mod RW {
1733 #[doc = "Input Path is determined by functionality"]
1734 pub const DISABLED: u32 = 0;
1735 #[doc = "Force input path of pad GPIO_06"]
1736 pub const ENABLED: u32 = 0x01;
1737 }
1738 }
1739}
1740#[doc = "SW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register"]
1741pub mod SW_MUX_CTL_PAD_GPIO_05 {
1742 #[doc = "MUX Mode Select Field."]
1743 pub mod MUX_MODE {
1744 pub const offset: u32 = 0;
1745 pub const mask: u32 = 0x07 << offset;
1746 pub mod R {}
1747 pub mod W {}
1748 pub mod RW {
1749 #[doc = "Select mux mode: ALT0 mux port: SAI1_TX_DATA01 of instance: SAI1"]
1750 pub const ALT0: u32 = 0;
1751 #[doc = "Select mux mode: ALT1 mux port: GPT1_COMPARE2 of instance: GPT1"]
1752 pub const ALT1: u32 = 0x01;
1753 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1"]
1754 pub const ALT2: u32 = 0x02;
1755 #[doc = "Select mux mode: ALT3 mux port: LPUART4_RXD of instance: LPUART4"]
1756 pub const ALT3: u32 = 0x03;
1757 #[doc = "Select mux mode: ALT4 mux port: SPDIF_OUT of instance: SPDIF"]
1758 pub const ALT4: u32 = 0x04;
1759 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO05 of instance: GPIOMUX"]
1760 pub const ALT5: u32 = 0x05;
1761 }
1762 }
1763 #[doc = "Software Input On Field."]
1764 pub mod SION {
1765 pub const offset: u32 = 4;
1766 pub const mask: u32 = 0x01 << offset;
1767 pub mod R {}
1768 pub mod W {}
1769 pub mod RW {
1770 #[doc = "Input Path is determined by functionality"]
1771 pub const DISABLED: u32 = 0;
1772 #[doc = "Force input path of pad GPIO_05"]
1773 pub const ENABLED: u32 = 0x01;
1774 }
1775 }
1776}
1777#[doc = "SW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register"]
1778pub mod SW_MUX_CTL_PAD_GPIO_04 {
1779 #[doc = "MUX Mode Select Field."]
1780 pub mod MUX_MODE {
1781 pub const offset: u32 = 0;
1782 pub const mask: u32 = 0x07 << offset;
1783 pub mod R {}
1784 pub mod W {}
1785 pub mod RW {
1786 #[doc = "Select mux mode: ALT0 mux port: SAI1_TX_DATA00 of instance: SAI1"]
1787 pub const ALT0: u32 = 0;
1788 #[doc = "Select mux mode: ALT1 mux port: GPT1_CAPTURE2 of instance: GPT1"]
1789 pub const ALT1: u32 = 0x01;
1790 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1"]
1791 pub const ALT2: u32 = 0x02;
1792 #[doc = "Select mux mode: ALT4 mux port: SPDIF_IN of instance: SPDIF"]
1793 pub const ALT4: u32 = 0x04;
1794 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO04 of instance: GPIOMUX"]
1795 pub const ALT5: u32 = 0x05;
1796 }
1797 }
1798 #[doc = "Software Input On Field."]
1799 pub mod SION {
1800 pub const offset: u32 = 4;
1801 pub const mask: u32 = 0x01 << offset;
1802 pub mod R {}
1803 pub mod W {}
1804 pub mod RW {
1805 #[doc = "Input Path is determined by functionality"]
1806 pub const DISABLED: u32 = 0;
1807 #[doc = "Force input path of pad GPIO_04"]
1808 pub const ENABLED: u32 = 0x01;
1809 }
1810 }
1811}
1812#[doc = "SW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register"]
1813pub mod SW_MUX_CTL_PAD_GPIO_03 {
1814 #[doc = "MUX Mode Select Field."]
1815 pub mod MUX_MODE {
1816 pub const offset: u32 = 0;
1817 pub const mask: u32 = 0x07 << offset;
1818 pub mod R {}
1819 pub mod W {}
1820 pub mod RW {
1821 #[doc = "Select mux mode: ALT0 mux port: SAI1_RX_DATA00 of instance: SAI1"]
1822 pub const ALT0: u32 = 0;
1823 #[doc = "Select mux mode: ALT1 mux port: GPT1_COMPARE3 of instance: GPT1"]
1824 pub const ALT1: u32 = 0x01;
1825 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1"]
1826 pub const ALT2: u32 = 0x02;
1827 #[doc = "Select mux mode: ALT4 mux port: SPDIF_SR_CLK of instance: SPDIF"]
1828 pub const ALT4: u32 = 0x04;
1829 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO03 of instance: GPIOMUX"]
1830 pub const ALT5: u32 = 0x05;
1831 }
1832 }
1833 #[doc = "Software Input On Field."]
1834 pub mod SION {
1835 pub const offset: u32 = 4;
1836 pub const mask: u32 = 0x01 << offset;
1837 pub mod R {}
1838 pub mod W {}
1839 pub mod RW {
1840 #[doc = "Input Path is determined by functionality"]
1841 pub const DISABLED: u32 = 0;
1842 #[doc = "Force input path of pad GPIO_03"]
1843 pub const ENABLED: u32 = 0x01;
1844 }
1845 }
1846}
1847#[doc = "SW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register"]
1848pub mod SW_MUX_CTL_PAD_GPIO_02 {
1849 #[doc = "MUX Mode Select Field."]
1850 pub mod MUX_MODE {
1851 pub const offset: u32 = 0;
1852 pub const mask: u32 = 0x07 << offset;
1853 pub mod R {}
1854 pub mod W {}
1855 pub mod RW {
1856 #[doc = "Select mux mode: ALT0 mux port: SAI1_RX_SYNC of instance: SAI1"]
1857 pub const ALT0: u32 = 0;
1858 #[doc = "Select mux mode: ALT1 mux port: WDOG2_B of instance: WDOG2"]
1859 pub const ALT1: u32 = 0x01;
1860 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1"]
1861 pub const ALT2: u32 = 0x02;
1862 #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: LPI2C1"]
1863 pub const ALT3: u32 = 0x03;
1864 #[doc = "Select mux mode: ALT4 mux port: KPP_COL03 of instance: KPP"]
1865 pub const ALT4: u32 = 0x04;
1866 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO02 of instance: GPIOMUX"]
1867 pub const ALT5: u32 = 0x05;
1868 }
1869 }
1870 #[doc = "Software Input On Field."]
1871 pub mod SION {
1872 pub const offset: u32 = 4;
1873 pub const mask: u32 = 0x01 << offset;
1874 pub mod R {}
1875 pub mod W {}
1876 pub mod RW {
1877 #[doc = "Input Path is determined by functionality"]
1878 pub const DISABLED: u32 = 0;
1879 #[doc = "Force input path of pad GPIO_02"]
1880 pub const ENABLED: u32 = 0x01;
1881 }
1882 }
1883}
1884#[doc = "SW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register"]
1885pub mod SW_MUX_CTL_PAD_GPIO_01 {
1886 #[doc = "MUX Mode Select Field."]
1887 pub mod MUX_MODE {
1888 pub const offset: u32 = 0;
1889 pub const mask: u32 = 0x07 << offset;
1890 pub mod R {}
1891 pub mod W {}
1892 pub mod RW {
1893 #[doc = "Select mux mode: ALT0 mux port: SAI1_RX_BCLK of instance: SAI1"]
1894 pub const ALT0: u32 = 0;
1895 #[doc = "Select mux mode: ALT1 mux port: WDOG1_ANY of instance: WDOG1"]
1896 pub const ALT1: u32 = 0x01;
1897 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1"]
1898 pub const ALT2: u32 = 0x02;
1899 #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: LPI2C1"]
1900 pub const ALT3: u32 = 0x03;
1901 #[doc = "Select mux mode: ALT4 mux port: KPP_ROW03 of instance: KPP"]
1902 pub const ALT4: u32 = 0x04;
1903 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO01 of instance: GPIOMUX"]
1904 pub const ALT5: u32 = 0x05;
1905 }
1906 }
1907 #[doc = "Software Input On Field."]
1908 pub mod SION {
1909 pub const offset: u32 = 4;
1910 pub const mask: u32 = 0x01 << offset;
1911 pub mod R {}
1912 pub mod W {}
1913 pub mod RW {
1914 #[doc = "Input Path is determined by functionality"]
1915 pub const DISABLED: u32 = 0;
1916 #[doc = "Force input path of pad GPIO_01"]
1917 pub const ENABLED: u32 = 0x01;
1918 }
1919 }
1920}
1921#[doc = "SW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register"]
1922pub mod SW_MUX_CTL_PAD_GPIO_00 {
1923 #[doc = "MUX Mode Select Field."]
1924 pub mod MUX_MODE {
1925 pub const offset: u32 = 0;
1926 pub const mask: u32 = 0x07 << offset;
1927 pub mod R {}
1928 pub mod W {}
1929 pub mod RW {
1930 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI_B_DQS of instance: FLEXSPI"]
1931 pub const ALT0: u32 = 0;
1932 #[doc = "Select mux mode: ALT1 mux port: SAI3_MCLK of instance: SAI3"]
1933 pub const ALT1: u32 = 0x01;
1934 #[doc = "Select mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: LPSPI2"]
1935 pub const ALT2: u32 = 0x02;
1936 #[doc = "Select mux mode: ALT3 mux port: LPSPI1_PCS3 of instance: LPSPI1"]
1937 pub const ALT3: u32 = 0x03;
1938 #[doc = "Select mux mode: ALT4 mux port: PIT_TRIGGER00 of instance: PIT"]
1939 pub const ALT4: u32 = 0x04;
1940 #[doc = "Select mux mode: ALT5 mux port: GPIOMUX_IO00 of instance: GPIOMUX"]
1941 pub const ALT5: u32 = 0x05;
1942 }
1943 }
1944 #[doc = "Software Input On Field."]
1945 pub mod SION {
1946 pub const offset: u32 = 4;
1947 pub const mask: u32 = 0x01 << offset;
1948 pub mod R {}
1949 pub mod W {}
1950 pub mod RW {
1951 #[doc = "Input Path is determined by functionality"]
1952 pub const DISABLED: u32 = 0;
1953 #[doc = "Force input path of pad GPIO_00"]
1954 pub const ENABLED: u32 = 0x01;
1955 }
1956 }
1957}
1958#[doc = "SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register"]
1959pub mod SW_PAD_CTL_PAD_GPIO_AD_14 {
1960 #[doc = "Slew Rate Field"]
1961 pub mod SRE {
1962 pub const offset: u32 = 0;
1963 pub const mask: u32 = 0x01 << offset;
1964 pub mod R {}
1965 pub mod W {}
1966 pub mod RW {
1967 #[doc = "Slow Slew Rate"]
1968 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
1969 #[doc = "Fast Slew Rate"]
1970 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
1971 }
1972 }
1973 #[doc = "Drive Strength Field"]
1974 pub mod DSE {
1975 pub const offset: u32 = 3;
1976 pub const mask: u32 = 0x07 << offset;
1977 pub mod R {}
1978 pub mod W {}
1979 pub mod RW {
1980 #[doc = "output driver disabled;"]
1981 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
1982 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
1983 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
1984 #[doc = "R0/2"]
1985 pub const DSE_2_R0_2: u32 = 0x02;
1986 #[doc = "R0/3"]
1987 pub const DSE_3_R0_3: u32 = 0x03;
1988 #[doc = "R0/4"]
1989 pub const DSE_4_R0_4: u32 = 0x04;
1990 #[doc = "R0/5"]
1991 pub const DSE_5_R0_5: u32 = 0x05;
1992 #[doc = "R0/6"]
1993 pub const DSE_6_R0_6: u32 = 0x06;
1994 #[doc = "R0/7"]
1995 pub const DSE_7_R0_7: u32 = 0x07;
1996 }
1997 }
1998 #[doc = "Speed Field"]
1999 pub mod SPEED {
2000 pub const offset: u32 = 6;
2001 pub const mask: u32 = 0x03 << offset;
2002 pub mod R {}
2003 pub mod W {}
2004 pub mod RW {
2005 #[doc = "low(50MHz)"]
2006 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2007 #[doc = "medium(100MHz)"]
2008 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2009 #[doc = "fast(150MHz)"]
2010 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2011 #[doc = "max(200MHz)"]
2012 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2013 }
2014 }
2015 #[doc = "Open Drain Enable Field"]
2016 pub mod ODE {
2017 pub const offset: u32 = 11;
2018 pub const mask: u32 = 0x01 << offset;
2019 pub mod R {}
2020 pub mod W {}
2021 pub mod RW {
2022 #[doc = "Open Drain Disabled"]
2023 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2024 #[doc = "Open Drain Enabled"]
2025 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2026 }
2027 }
2028 #[doc = "Pull / Keep Enable Field"]
2029 pub mod PKE {
2030 pub const offset: u32 = 12;
2031 pub const mask: u32 = 0x01 << offset;
2032 pub mod R {}
2033 pub mod W {}
2034 pub mod RW {
2035 #[doc = "Pull/Keeper Disabled"]
2036 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2037 #[doc = "Pull/Keeper Enabled"]
2038 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2039 }
2040 }
2041 #[doc = "Pull / Keep Select Field"]
2042 pub mod PUE {
2043 pub const offset: u32 = 13;
2044 pub const mask: u32 = 0x01 << offset;
2045 pub mod R {}
2046 pub mod W {}
2047 pub mod RW {
2048 #[doc = "Keeper"]
2049 pub const PUE_0_KEEPER: u32 = 0;
2050 #[doc = "Pull"]
2051 pub const PUE_1_PULL: u32 = 0x01;
2052 }
2053 }
2054 #[doc = "Pull Up / Down Config. Field"]
2055 pub mod PUS {
2056 pub const offset: u32 = 14;
2057 pub const mask: u32 = 0x03 << offset;
2058 pub mod R {}
2059 pub mod W {}
2060 pub mod RW {
2061 #[doc = "100K Ohm Pull Down"]
2062 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2063 #[doc = "47K Ohm Pull Up"]
2064 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2065 #[doc = "100K Ohm Pull Up"]
2066 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2067 #[doc = "22K Ohm Pull Up"]
2068 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2069 }
2070 }
2071 #[doc = "Hyst. Enable Field"]
2072 pub mod HYS {
2073 pub const offset: u32 = 16;
2074 pub const mask: u32 = 0x01 << offset;
2075 pub mod R {}
2076 pub mod W {}
2077 pub mod RW {
2078 #[doc = "Hysteresis Disabled"]
2079 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2080 #[doc = "Hysteresis Enabled"]
2081 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2082 }
2083 }
2084}
2085#[doc = "SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register"]
2086pub mod SW_PAD_CTL_PAD_GPIO_AD_13 {
2087 #[doc = "Slew Rate Field"]
2088 pub mod SRE {
2089 pub const offset: u32 = 0;
2090 pub const mask: u32 = 0x01 << offset;
2091 pub mod R {}
2092 pub mod W {}
2093 pub mod RW {
2094 #[doc = "Slow Slew Rate"]
2095 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2096 #[doc = "Fast Slew Rate"]
2097 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2098 }
2099 }
2100 #[doc = "Drive Strength Field"]
2101 pub mod DSE {
2102 pub const offset: u32 = 3;
2103 pub const mask: u32 = 0x07 << offset;
2104 pub mod R {}
2105 pub mod W {}
2106 pub mod RW {
2107 #[doc = "output driver disabled;"]
2108 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2109 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2110 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
2111 #[doc = "R0/2"]
2112 pub const DSE_2_R0_2: u32 = 0x02;
2113 #[doc = "R0/3"]
2114 pub const DSE_3_R0_3: u32 = 0x03;
2115 #[doc = "R0/4"]
2116 pub const DSE_4_R0_4: u32 = 0x04;
2117 #[doc = "R0/5"]
2118 pub const DSE_5_R0_5: u32 = 0x05;
2119 #[doc = "R0/6"]
2120 pub const DSE_6_R0_6: u32 = 0x06;
2121 #[doc = "R0/7"]
2122 pub const DSE_7_R0_7: u32 = 0x07;
2123 }
2124 }
2125 #[doc = "Speed Field"]
2126 pub mod SPEED {
2127 pub const offset: u32 = 6;
2128 pub const mask: u32 = 0x03 << offset;
2129 pub mod R {}
2130 pub mod W {}
2131 pub mod RW {
2132 #[doc = "low(50MHz)"]
2133 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2134 #[doc = "medium(100MHz)"]
2135 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2136 #[doc = "fast(150MHz)"]
2137 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2138 #[doc = "max(200MHz)"]
2139 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2140 }
2141 }
2142 #[doc = "Open Drain Enable Field"]
2143 pub mod ODE {
2144 pub const offset: u32 = 11;
2145 pub const mask: u32 = 0x01 << offset;
2146 pub mod R {}
2147 pub mod W {}
2148 pub mod RW {
2149 #[doc = "Open Drain Disabled"]
2150 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2151 #[doc = "Open Drain Enabled"]
2152 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2153 }
2154 }
2155 #[doc = "Pull / Keep Enable Field"]
2156 pub mod PKE {
2157 pub const offset: u32 = 12;
2158 pub const mask: u32 = 0x01 << offset;
2159 pub mod R {}
2160 pub mod W {}
2161 pub mod RW {
2162 #[doc = "Pull/Keeper Disabled"]
2163 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2164 #[doc = "Pull/Keeper Enabled"]
2165 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2166 }
2167 }
2168 #[doc = "Pull / Keep Select Field"]
2169 pub mod PUE {
2170 pub const offset: u32 = 13;
2171 pub const mask: u32 = 0x01 << offset;
2172 pub mod R {}
2173 pub mod W {}
2174 pub mod RW {
2175 #[doc = "Keeper"]
2176 pub const PUE_0_KEEPER: u32 = 0;
2177 #[doc = "Pull"]
2178 pub const PUE_1_PULL: u32 = 0x01;
2179 }
2180 }
2181 #[doc = "Pull Up / Down Config. Field"]
2182 pub mod PUS {
2183 pub const offset: u32 = 14;
2184 pub const mask: u32 = 0x03 << offset;
2185 pub mod R {}
2186 pub mod W {}
2187 pub mod RW {
2188 #[doc = "100K Ohm Pull Down"]
2189 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2190 #[doc = "47K Ohm Pull Up"]
2191 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2192 #[doc = "100K Ohm Pull Up"]
2193 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2194 #[doc = "22K Ohm Pull Up"]
2195 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2196 }
2197 }
2198 #[doc = "Hyst. Enable Field"]
2199 pub mod HYS {
2200 pub const offset: u32 = 16;
2201 pub const mask: u32 = 0x01 << offset;
2202 pub mod R {}
2203 pub mod W {}
2204 pub mod RW {
2205 #[doc = "Hysteresis Disabled"]
2206 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2207 #[doc = "Hysteresis Enabled"]
2208 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2209 }
2210 }
2211}
2212#[doc = "SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register"]
2213pub mod SW_PAD_CTL_PAD_GPIO_AD_12 {
2214 #[doc = "Slew Rate Field"]
2215 pub mod SRE {
2216 pub const offset: u32 = 0;
2217 pub const mask: u32 = 0x01 << offset;
2218 pub mod R {}
2219 pub mod W {}
2220 pub mod RW {
2221 #[doc = "Slow Slew Rate"]
2222 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2223 #[doc = "Fast Slew Rate"]
2224 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2225 }
2226 }
2227 #[doc = "Drive Strength Field"]
2228 pub mod DSE {
2229 pub const offset: u32 = 3;
2230 pub const mask: u32 = 0x07 << offset;
2231 pub mod R {}
2232 pub mod W {}
2233 pub mod RW {
2234 #[doc = "output driver disabled;"]
2235 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2236 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2237 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
2238 #[doc = "R0/2"]
2239 pub const DSE_2_R0_2: u32 = 0x02;
2240 #[doc = "R0/3"]
2241 pub const DSE_3_R0_3: u32 = 0x03;
2242 #[doc = "R0/4"]
2243 pub const DSE_4_R0_4: u32 = 0x04;
2244 #[doc = "R0/5"]
2245 pub const DSE_5_R0_5: u32 = 0x05;
2246 #[doc = "R0/6"]
2247 pub const DSE_6_R0_6: u32 = 0x06;
2248 #[doc = "R0/7"]
2249 pub const DSE_7_R0_7: u32 = 0x07;
2250 }
2251 }
2252 #[doc = "Speed Field"]
2253 pub mod SPEED {
2254 pub const offset: u32 = 6;
2255 pub const mask: u32 = 0x03 << offset;
2256 pub mod R {}
2257 pub mod W {}
2258 pub mod RW {
2259 #[doc = "low(50MHz)"]
2260 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2261 #[doc = "medium(100MHz)"]
2262 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2263 #[doc = "fast(150MHz)"]
2264 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2265 #[doc = "max(200MHz)"]
2266 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2267 }
2268 }
2269 #[doc = "Open Drain Enable Field"]
2270 pub mod ODE {
2271 pub const offset: u32 = 11;
2272 pub const mask: u32 = 0x01 << offset;
2273 pub mod R {}
2274 pub mod W {}
2275 pub mod RW {
2276 #[doc = "Open Drain Disabled"]
2277 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2278 #[doc = "Open Drain Enabled"]
2279 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2280 }
2281 }
2282 #[doc = "Pull / Keep Enable Field"]
2283 pub mod PKE {
2284 pub const offset: u32 = 12;
2285 pub const mask: u32 = 0x01 << offset;
2286 pub mod R {}
2287 pub mod W {}
2288 pub mod RW {
2289 #[doc = "Pull/Keeper Disabled"]
2290 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2291 #[doc = "Pull/Keeper Enabled"]
2292 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2293 }
2294 }
2295 #[doc = "Pull / Keep Select Field"]
2296 pub mod PUE {
2297 pub const offset: u32 = 13;
2298 pub const mask: u32 = 0x01 << offset;
2299 pub mod R {}
2300 pub mod W {}
2301 pub mod RW {
2302 #[doc = "Keeper"]
2303 pub const PUE_0_KEEPER: u32 = 0;
2304 #[doc = "Pull"]
2305 pub const PUE_1_PULL: u32 = 0x01;
2306 }
2307 }
2308 #[doc = "Pull Up / Down Config. Field"]
2309 pub mod PUS {
2310 pub const offset: u32 = 14;
2311 pub const mask: u32 = 0x03 << offset;
2312 pub mod R {}
2313 pub mod W {}
2314 pub mod RW {
2315 #[doc = "100K Ohm Pull Down"]
2316 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2317 #[doc = "47K Ohm Pull Up"]
2318 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2319 #[doc = "100K Ohm Pull Up"]
2320 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2321 #[doc = "22K Ohm Pull Up"]
2322 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2323 }
2324 }
2325 #[doc = "Hyst. Enable Field"]
2326 pub mod HYS {
2327 pub const offset: u32 = 16;
2328 pub const mask: u32 = 0x01 << offset;
2329 pub mod R {}
2330 pub mod W {}
2331 pub mod RW {
2332 #[doc = "Hysteresis Disabled"]
2333 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2334 #[doc = "Hysteresis Enabled"]
2335 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2336 }
2337 }
2338}
2339#[doc = "SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register"]
2340pub mod SW_PAD_CTL_PAD_GPIO_AD_11 {
2341 #[doc = "Slew Rate Field"]
2342 pub mod SRE {
2343 pub const offset: u32 = 0;
2344 pub const mask: u32 = 0x01 << offset;
2345 pub mod R {}
2346 pub mod W {}
2347 pub mod RW {
2348 #[doc = "Slow Slew Rate"]
2349 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2350 #[doc = "Fast Slew Rate"]
2351 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2352 }
2353 }
2354 #[doc = "Drive Strength Field"]
2355 pub mod DSE {
2356 pub const offset: u32 = 3;
2357 pub const mask: u32 = 0x07 << offset;
2358 pub mod R {}
2359 pub mod W {}
2360 pub mod RW {
2361 #[doc = "output driver disabled;"]
2362 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2363 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2364 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
2365 #[doc = "R0/2"]
2366 pub const DSE_2_R0_2: u32 = 0x02;
2367 #[doc = "R0/3"]
2368 pub const DSE_3_R0_3: u32 = 0x03;
2369 #[doc = "R0/4"]
2370 pub const DSE_4_R0_4: u32 = 0x04;
2371 #[doc = "R0/5"]
2372 pub const DSE_5_R0_5: u32 = 0x05;
2373 #[doc = "R0/6"]
2374 pub const DSE_6_R0_6: u32 = 0x06;
2375 #[doc = "R0/7"]
2376 pub const DSE_7_R0_7: u32 = 0x07;
2377 }
2378 }
2379 #[doc = "Speed Field"]
2380 pub mod SPEED {
2381 pub const offset: u32 = 6;
2382 pub const mask: u32 = 0x03 << offset;
2383 pub mod R {}
2384 pub mod W {}
2385 pub mod RW {
2386 #[doc = "low(50MHz)"]
2387 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2388 #[doc = "medium(100MHz)"]
2389 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2390 #[doc = "fast(150MHz)"]
2391 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2392 #[doc = "max(200MHz)"]
2393 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2394 }
2395 }
2396 #[doc = "Open Drain Enable Field"]
2397 pub mod ODE {
2398 pub const offset: u32 = 11;
2399 pub const mask: u32 = 0x01 << offset;
2400 pub mod R {}
2401 pub mod W {}
2402 pub mod RW {
2403 #[doc = "Open Drain Disabled"]
2404 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2405 #[doc = "Open Drain Enabled"]
2406 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2407 }
2408 }
2409 #[doc = "Pull / Keep Enable Field"]
2410 pub mod PKE {
2411 pub const offset: u32 = 12;
2412 pub const mask: u32 = 0x01 << offset;
2413 pub mod R {}
2414 pub mod W {}
2415 pub mod RW {
2416 #[doc = "Pull/Keeper Disabled"]
2417 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2418 #[doc = "Pull/Keeper Enabled"]
2419 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2420 }
2421 }
2422 #[doc = "Pull / Keep Select Field"]
2423 pub mod PUE {
2424 pub const offset: u32 = 13;
2425 pub const mask: u32 = 0x01 << offset;
2426 pub mod R {}
2427 pub mod W {}
2428 pub mod RW {
2429 #[doc = "Keeper"]
2430 pub const PUE_0_KEEPER: u32 = 0;
2431 #[doc = "Pull"]
2432 pub const PUE_1_PULL: u32 = 0x01;
2433 }
2434 }
2435 #[doc = "Pull Up / Down Config. Field"]
2436 pub mod PUS {
2437 pub const offset: u32 = 14;
2438 pub const mask: u32 = 0x03 << offset;
2439 pub mod R {}
2440 pub mod W {}
2441 pub mod RW {
2442 #[doc = "100K Ohm Pull Down"]
2443 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2444 #[doc = "47K Ohm Pull Up"]
2445 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2446 #[doc = "100K Ohm Pull Up"]
2447 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2448 #[doc = "22K Ohm Pull Up"]
2449 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2450 }
2451 }
2452 #[doc = "Hyst. Enable Field"]
2453 pub mod HYS {
2454 pub const offset: u32 = 16;
2455 pub const mask: u32 = 0x01 << offset;
2456 pub mod R {}
2457 pub mod W {}
2458 pub mod RW {
2459 #[doc = "Hysteresis Disabled"]
2460 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2461 #[doc = "Hysteresis Enabled"]
2462 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2463 }
2464 }
2465}
2466#[doc = "SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register"]
2467pub mod SW_PAD_CTL_PAD_GPIO_AD_10 {
2468 #[doc = "Slew Rate Field"]
2469 pub mod SRE {
2470 pub const offset: u32 = 0;
2471 pub const mask: u32 = 0x01 << offset;
2472 pub mod R {}
2473 pub mod W {}
2474 pub mod RW {
2475 #[doc = "Slow Slew Rate"]
2476 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2477 #[doc = "Fast Slew Rate"]
2478 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2479 }
2480 }
2481 #[doc = "Drive Strength Field"]
2482 pub mod DSE {
2483 pub const offset: u32 = 3;
2484 pub const mask: u32 = 0x07 << offset;
2485 pub mod R {}
2486 pub mod W {}
2487 pub mod RW {
2488 #[doc = "output driver disabled;"]
2489 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2490 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2491 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
2492 #[doc = "R0/2"]
2493 pub const DSE_2_R0_2: u32 = 0x02;
2494 #[doc = "R0/3"]
2495 pub const DSE_3_R0_3: u32 = 0x03;
2496 #[doc = "R0/4"]
2497 pub const DSE_4_R0_4: u32 = 0x04;
2498 #[doc = "R0/5"]
2499 pub const DSE_5_R0_5: u32 = 0x05;
2500 #[doc = "R0/6"]
2501 pub const DSE_6_R0_6: u32 = 0x06;
2502 #[doc = "R0/7"]
2503 pub const DSE_7_R0_7: u32 = 0x07;
2504 }
2505 }
2506 #[doc = "Speed Field"]
2507 pub mod SPEED {
2508 pub const offset: u32 = 6;
2509 pub const mask: u32 = 0x03 << offset;
2510 pub mod R {}
2511 pub mod W {}
2512 pub mod RW {
2513 #[doc = "low(50MHz)"]
2514 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2515 #[doc = "medium(100MHz)"]
2516 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2517 #[doc = "fast(150MHz)"]
2518 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2519 #[doc = "max(200MHz)"]
2520 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2521 }
2522 }
2523 #[doc = "Open Drain Enable Field"]
2524 pub mod ODE {
2525 pub const offset: u32 = 11;
2526 pub const mask: u32 = 0x01 << offset;
2527 pub mod R {}
2528 pub mod W {}
2529 pub mod RW {
2530 #[doc = "Open Drain Disabled"]
2531 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2532 #[doc = "Open Drain Enabled"]
2533 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2534 }
2535 }
2536 #[doc = "Pull / Keep Enable Field"]
2537 pub mod PKE {
2538 pub const offset: u32 = 12;
2539 pub const mask: u32 = 0x01 << offset;
2540 pub mod R {}
2541 pub mod W {}
2542 pub mod RW {
2543 #[doc = "Pull/Keeper Disabled"]
2544 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2545 #[doc = "Pull/Keeper Enabled"]
2546 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2547 }
2548 }
2549 #[doc = "Pull / Keep Select Field"]
2550 pub mod PUE {
2551 pub const offset: u32 = 13;
2552 pub const mask: u32 = 0x01 << offset;
2553 pub mod R {}
2554 pub mod W {}
2555 pub mod RW {
2556 #[doc = "Keeper"]
2557 pub const PUE_0_KEEPER: u32 = 0;
2558 #[doc = "Pull"]
2559 pub const PUE_1_PULL: u32 = 0x01;
2560 }
2561 }
2562 #[doc = "Pull Up / Down Config. Field"]
2563 pub mod PUS {
2564 pub const offset: u32 = 14;
2565 pub const mask: u32 = 0x03 << offset;
2566 pub mod R {}
2567 pub mod W {}
2568 pub mod RW {
2569 #[doc = "100K Ohm Pull Down"]
2570 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2571 #[doc = "47K Ohm Pull Up"]
2572 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2573 #[doc = "100K Ohm Pull Up"]
2574 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2575 #[doc = "22K Ohm Pull Up"]
2576 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2577 }
2578 }
2579 #[doc = "Hyst. Enable Field"]
2580 pub mod HYS {
2581 pub const offset: u32 = 16;
2582 pub const mask: u32 = 0x01 << offset;
2583 pub mod R {}
2584 pub mod W {}
2585 pub mod RW {
2586 #[doc = "Hysteresis Disabled"]
2587 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2588 #[doc = "Hysteresis Enabled"]
2589 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2590 }
2591 }
2592}
2593#[doc = "SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register"]
2594pub mod SW_PAD_CTL_PAD_GPIO_AD_09 {
2595 #[doc = "Slew Rate Field"]
2596 pub mod SRE {
2597 pub const offset: u32 = 0;
2598 pub const mask: u32 = 0x01 << offset;
2599 pub mod R {}
2600 pub mod W {}
2601 pub mod RW {
2602 #[doc = "Slow Slew Rate"]
2603 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2604 #[doc = "Fast Slew Rate"]
2605 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2606 }
2607 }
2608 #[doc = "Drive Strength Field"]
2609 pub mod DSE {
2610 pub const offset: u32 = 3;
2611 pub const mask: u32 = 0x07 << offset;
2612 pub mod R {}
2613 pub mod W {}
2614 pub mod RW {
2615 #[doc = "output driver disabled;"]
2616 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2617 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2618 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
2619 #[doc = "R0/2"]
2620 pub const DSE_2_R0_2: u32 = 0x02;
2621 #[doc = "R0/3"]
2622 pub const DSE_3_R0_3: u32 = 0x03;
2623 #[doc = "R0/4"]
2624 pub const DSE_4_R0_4: u32 = 0x04;
2625 #[doc = "R0/5"]
2626 pub const DSE_5_R0_5: u32 = 0x05;
2627 #[doc = "R0/6"]
2628 pub const DSE_6_R0_6: u32 = 0x06;
2629 #[doc = "R0/7"]
2630 pub const DSE_7_R0_7: u32 = 0x07;
2631 }
2632 }
2633 #[doc = "Speed Field"]
2634 pub mod SPEED {
2635 pub const offset: u32 = 6;
2636 pub const mask: u32 = 0x03 << offset;
2637 pub mod R {}
2638 pub mod W {}
2639 pub mod RW {
2640 #[doc = "low(50MHz)"]
2641 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2642 #[doc = "medium(100MHz)"]
2643 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2644 #[doc = "fast(150MHz)"]
2645 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2646 #[doc = "max(200MHz)"]
2647 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2648 }
2649 }
2650 #[doc = "Open Drain Enable Field"]
2651 pub mod ODE {
2652 pub const offset: u32 = 11;
2653 pub const mask: u32 = 0x01 << offset;
2654 pub mod R {}
2655 pub mod W {}
2656 pub mod RW {
2657 #[doc = "Open Drain Disabled"]
2658 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2659 #[doc = "Open Drain Enabled"]
2660 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2661 }
2662 }
2663 #[doc = "Pull / Keep Enable Field"]
2664 pub mod PKE {
2665 pub const offset: u32 = 12;
2666 pub const mask: u32 = 0x01 << offset;
2667 pub mod R {}
2668 pub mod W {}
2669 pub mod RW {
2670 #[doc = "Pull/Keeper Disabled"]
2671 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2672 #[doc = "Pull/Keeper Enabled"]
2673 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2674 }
2675 }
2676 #[doc = "Pull / Keep Select Field"]
2677 pub mod PUE {
2678 pub const offset: u32 = 13;
2679 pub const mask: u32 = 0x01 << offset;
2680 pub mod R {}
2681 pub mod W {}
2682 pub mod RW {
2683 #[doc = "Keeper"]
2684 pub const PUE_0_KEEPER: u32 = 0;
2685 #[doc = "Pull"]
2686 pub const PUE_1_PULL: u32 = 0x01;
2687 }
2688 }
2689 #[doc = "Pull Up / Down Config. Field"]
2690 pub mod PUS {
2691 pub const offset: u32 = 14;
2692 pub const mask: u32 = 0x03 << offset;
2693 pub mod R {}
2694 pub mod W {}
2695 pub mod RW {
2696 #[doc = "100K Ohm Pull Down"]
2697 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2698 #[doc = "47K Ohm Pull Up"]
2699 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2700 #[doc = "100K Ohm Pull Up"]
2701 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2702 #[doc = "22K Ohm Pull Up"]
2703 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2704 }
2705 }
2706 #[doc = "Hyst. Enable Field"]
2707 pub mod HYS {
2708 pub const offset: u32 = 16;
2709 pub const mask: u32 = 0x01 << offset;
2710 pub mod R {}
2711 pub mod W {}
2712 pub mod RW {
2713 #[doc = "Hysteresis Disabled"]
2714 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2715 #[doc = "Hysteresis Enabled"]
2716 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2717 }
2718 }
2719}
2720#[doc = "SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register"]
2721pub mod SW_PAD_CTL_PAD_GPIO_AD_08 {
2722 #[doc = "Slew Rate Field"]
2723 pub mod SRE {
2724 pub const offset: u32 = 0;
2725 pub const mask: u32 = 0x01 << offset;
2726 pub mod R {}
2727 pub mod W {}
2728 pub mod RW {
2729 #[doc = "Slow Slew Rate"]
2730 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2731 #[doc = "Fast Slew Rate"]
2732 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2733 }
2734 }
2735 #[doc = "Drive Strength Field"]
2736 pub mod DSE {
2737 pub const offset: u32 = 3;
2738 pub const mask: u32 = 0x07 << offset;
2739 pub mod R {}
2740 pub mod W {}
2741 pub mod RW {
2742 #[doc = "output driver disabled;"]
2743 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2744 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2745 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
2746 #[doc = "R0/2"]
2747 pub const DSE_2_R0_2: u32 = 0x02;
2748 #[doc = "R0/3"]
2749 pub const DSE_3_R0_3: u32 = 0x03;
2750 #[doc = "R0/4"]
2751 pub const DSE_4_R0_4: u32 = 0x04;
2752 #[doc = "R0/5"]
2753 pub const DSE_5_R0_5: u32 = 0x05;
2754 #[doc = "R0/6"]
2755 pub const DSE_6_R0_6: u32 = 0x06;
2756 #[doc = "R0/7"]
2757 pub const DSE_7_R0_7: u32 = 0x07;
2758 }
2759 }
2760 #[doc = "Speed Field"]
2761 pub mod SPEED {
2762 pub const offset: u32 = 6;
2763 pub const mask: u32 = 0x03 << offset;
2764 pub mod R {}
2765 pub mod W {}
2766 pub mod RW {
2767 #[doc = "low(50MHz)"]
2768 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2769 #[doc = "medium(100MHz)"]
2770 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2771 #[doc = "fast(150MHz)"]
2772 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2773 #[doc = "max(200MHz)"]
2774 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2775 }
2776 }
2777 #[doc = "Open Drain Enable Field"]
2778 pub mod ODE {
2779 pub const offset: u32 = 11;
2780 pub const mask: u32 = 0x01 << offset;
2781 pub mod R {}
2782 pub mod W {}
2783 pub mod RW {
2784 #[doc = "Open Drain Disabled"]
2785 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2786 #[doc = "Open Drain Enabled"]
2787 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2788 }
2789 }
2790 #[doc = "Pull / Keep Enable Field"]
2791 pub mod PKE {
2792 pub const offset: u32 = 12;
2793 pub const mask: u32 = 0x01 << offset;
2794 pub mod R {}
2795 pub mod W {}
2796 pub mod RW {
2797 #[doc = "Pull/Keeper Disabled"]
2798 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2799 #[doc = "Pull/Keeper Enabled"]
2800 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2801 }
2802 }
2803 #[doc = "Pull / Keep Select Field"]
2804 pub mod PUE {
2805 pub const offset: u32 = 13;
2806 pub const mask: u32 = 0x01 << offset;
2807 pub mod R {}
2808 pub mod W {}
2809 pub mod RW {
2810 #[doc = "Keeper"]
2811 pub const PUE_0_KEEPER: u32 = 0;
2812 #[doc = "Pull"]
2813 pub const PUE_1_PULL: u32 = 0x01;
2814 }
2815 }
2816 #[doc = "Pull Up / Down Config. Field"]
2817 pub mod PUS {
2818 pub const offset: u32 = 14;
2819 pub const mask: u32 = 0x03 << offset;
2820 pub mod R {}
2821 pub mod W {}
2822 pub mod RW {
2823 #[doc = "100K Ohm Pull Down"]
2824 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2825 #[doc = "47K Ohm Pull Up"]
2826 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2827 #[doc = "100K Ohm Pull Up"]
2828 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2829 #[doc = "22K Ohm Pull Up"]
2830 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2831 }
2832 }
2833 #[doc = "Hyst. Enable Field"]
2834 pub mod HYS {
2835 pub const offset: u32 = 16;
2836 pub const mask: u32 = 0x01 << offset;
2837 pub mod R {}
2838 pub mod W {}
2839 pub mod RW {
2840 #[doc = "Hysteresis Disabled"]
2841 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2842 #[doc = "Hysteresis Enabled"]
2843 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2844 }
2845 }
2846}
2847#[doc = "SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register"]
2848pub mod SW_PAD_CTL_PAD_GPIO_AD_07 {
2849 #[doc = "Slew Rate Field"]
2850 pub mod SRE {
2851 pub const offset: u32 = 0;
2852 pub const mask: u32 = 0x01 << offset;
2853 pub mod R {}
2854 pub mod W {}
2855 pub mod RW {
2856 #[doc = "Slow Slew Rate"]
2857 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2858 #[doc = "Fast Slew Rate"]
2859 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2860 }
2861 }
2862 #[doc = "Drive Strength Field"]
2863 pub mod DSE {
2864 pub const offset: u32 = 3;
2865 pub const mask: u32 = 0x07 << offset;
2866 pub mod R {}
2867 pub mod W {}
2868 pub mod RW {
2869 #[doc = "output driver disabled;"]
2870 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2871 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2872 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
2873 #[doc = "R0/2"]
2874 pub const DSE_2_R0_2: u32 = 0x02;
2875 #[doc = "R0/3"]
2876 pub const DSE_3_R0_3: u32 = 0x03;
2877 #[doc = "R0/4"]
2878 pub const DSE_4_R0_4: u32 = 0x04;
2879 #[doc = "R0/5"]
2880 pub const DSE_5_R0_5: u32 = 0x05;
2881 #[doc = "R0/6"]
2882 pub const DSE_6_R0_6: u32 = 0x06;
2883 #[doc = "R0/7"]
2884 pub const DSE_7_R0_7: u32 = 0x07;
2885 }
2886 }
2887 #[doc = "Speed Field"]
2888 pub mod SPEED {
2889 pub const offset: u32 = 6;
2890 pub const mask: u32 = 0x03 << offset;
2891 pub mod R {}
2892 pub mod W {}
2893 pub mod RW {
2894 #[doc = "low(50MHz)"]
2895 pub const SPEED_0_LOW_50MHZ: u32 = 0;
2896 #[doc = "medium(100MHz)"]
2897 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
2898 #[doc = "fast(150MHz)"]
2899 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
2900 #[doc = "max(200MHz)"]
2901 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
2902 }
2903 }
2904 #[doc = "Open Drain Enable Field"]
2905 pub mod ODE {
2906 pub const offset: u32 = 11;
2907 pub const mask: u32 = 0x01 << offset;
2908 pub mod R {}
2909 pub mod W {}
2910 pub mod RW {
2911 #[doc = "Open Drain Disabled"]
2912 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
2913 #[doc = "Open Drain Enabled"]
2914 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
2915 }
2916 }
2917 #[doc = "Pull / Keep Enable Field"]
2918 pub mod PKE {
2919 pub const offset: u32 = 12;
2920 pub const mask: u32 = 0x01 << offset;
2921 pub mod R {}
2922 pub mod W {}
2923 pub mod RW {
2924 #[doc = "Pull/Keeper Disabled"]
2925 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
2926 #[doc = "Pull/Keeper Enabled"]
2927 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
2928 }
2929 }
2930 #[doc = "Pull / Keep Select Field"]
2931 pub mod PUE {
2932 pub const offset: u32 = 13;
2933 pub const mask: u32 = 0x01 << offset;
2934 pub mod R {}
2935 pub mod W {}
2936 pub mod RW {
2937 #[doc = "Keeper"]
2938 pub const PUE_0_KEEPER: u32 = 0;
2939 #[doc = "Pull"]
2940 pub const PUE_1_PULL: u32 = 0x01;
2941 }
2942 }
2943 #[doc = "Pull Up / Down Config. Field"]
2944 pub mod PUS {
2945 pub const offset: u32 = 14;
2946 pub const mask: u32 = 0x03 << offset;
2947 pub mod R {}
2948 pub mod W {}
2949 pub mod RW {
2950 #[doc = "100K Ohm Pull Down"]
2951 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
2952 #[doc = "47K Ohm Pull Up"]
2953 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
2954 #[doc = "100K Ohm Pull Up"]
2955 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
2956 #[doc = "22K Ohm Pull Up"]
2957 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
2958 }
2959 }
2960 #[doc = "Hyst. Enable Field"]
2961 pub mod HYS {
2962 pub const offset: u32 = 16;
2963 pub const mask: u32 = 0x01 << offset;
2964 pub mod R {}
2965 pub mod W {}
2966 pub mod RW {
2967 #[doc = "Hysteresis Disabled"]
2968 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
2969 #[doc = "Hysteresis Enabled"]
2970 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
2971 }
2972 }
2973}
2974#[doc = "SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register"]
2975pub mod SW_PAD_CTL_PAD_GPIO_AD_06 {
2976 #[doc = "Slew Rate Field"]
2977 pub mod SRE {
2978 pub const offset: u32 = 0;
2979 pub const mask: u32 = 0x01 << offset;
2980 pub mod R {}
2981 pub mod W {}
2982 pub mod RW {
2983 #[doc = "Slow Slew Rate"]
2984 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
2985 #[doc = "Fast Slew Rate"]
2986 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
2987 }
2988 }
2989 #[doc = "Drive Strength Field"]
2990 pub mod DSE {
2991 pub const offset: u32 = 3;
2992 pub const mask: u32 = 0x07 << offset;
2993 pub mod R {}
2994 pub mod W {}
2995 pub mod RW {
2996 #[doc = "output driver disabled;"]
2997 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
2998 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
2999 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3000 #[doc = "R0/2"]
3001 pub const DSE_2_R0_2: u32 = 0x02;
3002 #[doc = "R0/3"]
3003 pub const DSE_3_R0_3: u32 = 0x03;
3004 #[doc = "R0/4"]
3005 pub const DSE_4_R0_4: u32 = 0x04;
3006 #[doc = "R0/5"]
3007 pub const DSE_5_R0_5: u32 = 0x05;
3008 #[doc = "R0/6"]
3009 pub const DSE_6_R0_6: u32 = 0x06;
3010 #[doc = "R0/7"]
3011 pub const DSE_7_R0_7: u32 = 0x07;
3012 }
3013 }
3014 #[doc = "Speed Field"]
3015 pub mod SPEED {
3016 pub const offset: u32 = 6;
3017 pub const mask: u32 = 0x03 << offset;
3018 pub mod R {}
3019 pub mod W {}
3020 pub mod RW {
3021 #[doc = "low(50MHz)"]
3022 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3023 #[doc = "medium(100MHz)"]
3024 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3025 #[doc = "fast(150MHz)"]
3026 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3027 #[doc = "max(200MHz)"]
3028 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3029 }
3030 }
3031 #[doc = "Open Drain Enable Field"]
3032 pub mod ODE {
3033 pub const offset: u32 = 11;
3034 pub const mask: u32 = 0x01 << offset;
3035 pub mod R {}
3036 pub mod W {}
3037 pub mod RW {
3038 #[doc = "Open Drain Disabled"]
3039 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3040 #[doc = "Open Drain Enabled"]
3041 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3042 }
3043 }
3044 #[doc = "Pull / Keep Enable Field"]
3045 pub mod PKE {
3046 pub const offset: u32 = 12;
3047 pub const mask: u32 = 0x01 << offset;
3048 pub mod R {}
3049 pub mod W {}
3050 pub mod RW {
3051 #[doc = "Pull/Keeper Disabled"]
3052 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3053 #[doc = "Pull/Keeper Enabled"]
3054 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3055 }
3056 }
3057 #[doc = "Pull / Keep Select Field"]
3058 pub mod PUE {
3059 pub const offset: u32 = 13;
3060 pub const mask: u32 = 0x01 << offset;
3061 pub mod R {}
3062 pub mod W {}
3063 pub mod RW {
3064 #[doc = "Keeper"]
3065 pub const PUE_0_KEEPER: u32 = 0;
3066 #[doc = "Pull"]
3067 pub const PUE_1_PULL: u32 = 0x01;
3068 }
3069 }
3070 #[doc = "Pull Up / Down Config. Field"]
3071 pub mod PUS {
3072 pub const offset: u32 = 14;
3073 pub const mask: u32 = 0x03 << offset;
3074 pub mod R {}
3075 pub mod W {}
3076 pub mod RW {
3077 #[doc = "100K Ohm Pull Down"]
3078 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3079 #[doc = "47K Ohm Pull Up"]
3080 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3081 #[doc = "100K Ohm Pull Up"]
3082 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3083 #[doc = "22K Ohm Pull Up"]
3084 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3085 }
3086 }
3087 #[doc = "Hyst. Enable Field"]
3088 pub mod HYS {
3089 pub const offset: u32 = 16;
3090 pub const mask: u32 = 0x01 << offset;
3091 pub mod R {}
3092 pub mod W {}
3093 pub mod RW {
3094 #[doc = "Hysteresis Disabled"]
3095 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3096 #[doc = "Hysteresis Enabled"]
3097 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3098 }
3099 }
3100}
3101#[doc = "SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register"]
3102pub mod SW_PAD_CTL_PAD_GPIO_AD_05 {
3103 #[doc = "Slew Rate Field"]
3104 pub mod SRE {
3105 pub const offset: u32 = 0;
3106 pub const mask: u32 = 0x01 << offset;
3107 pub mod R {}
3108 pub mod W {}
3109 pub mod RW {
3110 #[doc = "Slow Slew Rate"]
3111 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
3112 #[doc = "Fast Slew Rate"]
3113 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
3114 }
3115 }
3116 #[doc = "Drive Strength Field"]
3117 pub mod DSE {
3118 pub const offset: u32 = 3;
3119 pub const mask: u32 = 0x07 << offset;
3120 pub mod R {}
3121 pub mod W {}
3122 pub mod RW {
3123 #[doc = "output driver disabled;"]
3124 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
3125 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
3126 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3127 #[doc = "R0/2"]
3128 pub const DSE_2_R0_2: u32 = 0x02;
3129 #[doc = "R0/3"]
3130 pub const DSE_3_R0_3: u32 = 0x03;
3131 #[doc = "R0/4"]
3132 pub const DSE_4_R0_4: u32 = 0x04;
3133 #[doc = "R0/5"]
3134 pub const DSE_5_R0_5: u32 = 0x05;
3135 #[doc = "R0/6"]
3136 pub const DSE_6_R0_6: u32 = 0x06;
3137 #[doc = "R0/7"]
3138 pub const DSE_7_R0_7: u32 = 0x07;
3139 }
3140 }
3141 #[doc = "Speed Field"]
3142 pub mod SPEED {
3143 pub const offset: u32 = 6;
3144 pub const mask: u32 = 0x03 << offset;
3145 pub mod R {}
3146 pub mod W {}
3147 pub mod RW {
3148 #[doc = "low(50MHz)"]
3149 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3150 #[doc = "medium(100MHz)"]
3151 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3152 #[doc = "fast(150MHz)"]
3153 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3154 #[doc = "max(200MHz)"]
3155 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3156 }
3157 }
3158 #[doc = "Open Drain Enable Field"]
3159 pub mod ODE {
3160 pub const offset: u32 = 11;
3161 pub const mask: u32 = 0x01 << offset;
3162 pub mod R {}
3163 pub mod W {}
3164 pub mod RW {
3165 #[doc = "Open Drain Disabled"]
3166 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3167 #[doc = "Open Drain Enabled"]
3168 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3169 }
3170 }
3171 #[doc = "Pull / Keep Enable Field"]
3172 pub mod PKE {
3173 pub const offset: u32 = 12;
3174 pub const mask: u32 = 0x01 << offset;
3175 pub mod R {}
3176 pub mod W {}
3177 pub mod RW {
3178 #[doc = "Pull/Keeper Disabled"]
3179 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3180 #[doc = "Pull/Keeper Enabled"]
3181 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3182 }
3183 }
3184 #[doc = "Pull / Keep Select Field"]
3185 pub mod PUE {
3186 pub const offset: u32 = 13;
3187 pub const mask: u32 = 0x01 << offset;
3188 pub mod R {}
3189 pub mod W {}
3190 pub mod RW {
3191 #[doc = "Keeper"]
3192 pub const PUE_0_KEEPER: u32 = 0;
3193 #[doc = "Pull"]
3194 pub const PUE_1_PULL: u32 = 0x01;
3195 }
3196 }
3197 #[doc = "Pull Up / Down Config. Field"]
3198 pub mod PUS {
3199 pub const offset: u32 = 14;
3200 pub const mask: u32 = 0x03 << offset;
3201 pub mod R {}
3202 pub mod W {}
3203 pub mod RW {
3204 #[doc = "100K Ohm Pull Down"]
3205 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3206 #[doc = "47K Ohm Pull Up"]
3207 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3208 #[doc = "100K Ohm Pull Up"]
3209 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3210 #[doc = "22K Ohm Pull Up"]
3211 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3212 }
3213 }
3214 #[doc = "Hyst. Enable Field"]
3215 pub mod HYS {
3216 pub const offset: u32 = 16;
3217 pub const mask: u32 = 0x01 << offset;
3218 pub mod R {}
3219 pub mod W {}
3220 pub mod RW {
3221 #[doc = "Hysteresis Disabled"]
3222 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3223 #[doc = "Hysteresis Enabled"]
3224 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3225 }
3226 }
3227}
3228#[doc = "SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register"]
3229pub mod SW_PAD_CTL_PAD_GPIO_AD_04 {
3230 #[doc = "Slew Rate Field"]
3231 pub mod SRE {
3232 pub const offset: u32 = 0;
3233 pub const mask: u32 = 0x01 << offset;
3234 pub mod R {}
3235 pub mod W {}
3236 pub mod RW {
3237 #[doc = "Slow Slew Rate"]
3238 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
3239 #[doc = "Fast Slew Rate"]
3240 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
3241 }
3242 }
3243 #[doc = "Drive Strength Field"]
3244 pub mod DSE {
3245 pub const offset: u32 = 3;
3246 pub const mask: u32 = 0x07 << offset;
3247 pub mod R {}
3248 pub mod W {}
3249 pub mod RW {
3250 #[doc = "output driver disabled;"]
3251 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
3252 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
3253 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3254 #[doc = "R0/2"]
3255 pub const DSE_2_R0_2: u32 = 0x02;
3256 #[doc = "R0/3"]
3257 pub const DSE_3_R0_3: u32 = 0x03;
3258 #[doc = "R0/4"]
3259 pub const DSE_4_R0_4: u32 = 0x04;
3260 #[doc = "R0/5"]
3261 pub const DSE_5_R0_5: u32 = 0x05;
3262 #[doc = "R0/6"]
3263 pub const DSE_6_R0_6: u32 = 0x06;
3264 #[doc = "R0/7"]
3265 pub const DSE_7_R0_7: u32 = 0x07;
3266 }
3267 }
3268 #[doc = "Speed Field"]
3269 pub mod SPEED {
3270 pub const offset: u32 = 6;
3271 pub const mask: u32 = 0x03 << offset;
3272 pub mod R {}
3273 pub mod W {}
3274 pub mod RW {
3275 #[doc = "low(50MHz)"]
3276 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3277 #[doc = "medium(100MHz)"]
3278 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3279 #[doc = "fast(150MHz)"]
3280 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3281 #[doc = "max(200MHz)"]
3282 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3283 }
3284 }
3285 #[doc = "Open Drain Enable Field"]
3286 pub mod ODE {
3287 pub const offset: u32 = 11;
3288 pub const mask: u32 = 0x01 << offset;
3289 pub mod R {}
3290 pub mod W {}
3291 pub mod RW {
3292 #[doc = "Open Drain Disabled"]
3293 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3294 #[doc = "Open Drain Enabled"]
3295 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3296 }
3297 }
3298 #[doc = "Pull / Keep Enable Field"]
3299 pub mod PKE {
3300 pub const offset: u32 = 12;
3301 pub const mask: u32 = 0x01 << offset;
3302 pub mod R {}
3303 pub mod W {}
3304 pub mod RW {
3305 #[doc = "Pull/Keeper Disabled"]
3306 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3307 #[doc = "Pull/Keeper Enabled"]
3308 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3309 }
3310 }
3311 #[doc = "Pull / Keep Select Field"]
3312 pub mod PUE {
3313 pub const offset: u32 = 13;
3314 pub const mask: u32 = 0x01 << offset;
3315 pub mod R {}
3316 pub mod W {}
3317 pub mod RW {
3318 #[doc = "Keeper"]
3319 pub const PUE_0_KEEPER: u32 = 0;
3320 #[doc = "Pull"]
3321 pub const PUE_1_PULL: u32 = 0x01;
3322 }
3323 }
3324 #[doc = "Pull Up / Down Config. Field"]
3325 pub mod PUS {
3326 pub const offset: u32 = 14;
3327 pub const mask: u32 = 0x03 << offset;
3328 pub mod R {}
3329 pub mod W {}
3330 pub mod RW {
3331 #[doc = "100K Ohm Pull Down"]
3332 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3333 #[doc = "47K Ohm Pull Up"]
3334 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3335 #[doc = "100K Ohm Pull Up"]
3336 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3337 #[doc = "22K Ohm Pull Up"]
3338 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3339 }
3340 }
3341 #[doc = "Hyst. Enable Field"]
3342 pub mod HYS {
3343 pub const offset: u32 = 16;
3344 pub const mask: u32 = 0x01 << offset;
3345 pub mod R {}
3346 pub mod W {}
3347 pub mod RW {
3348 #[doc = "Hysteresis Disabled"]
3349 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3350 #[doc = "Hysteresis Enabled"]
3351 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3352 }
3353 }
3354}
3355#[doc = "SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register"]
3356pub mod SW_PAD_CTL_PAD_GPIO_AD_03 {
3357 #[doc = "Slew Rate Field"]
3358 pub mod SRE {
3359 pub const offset: u32 = 0;
3360 pub const mask: u32 = 0x01 << offset;
3361 pub mod R {}
3362 pub mod W {}
3363 pub mod RW {
3364 #[doc = "Slow Slew Rate"]
3365 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
3366 #[doc = "Fast Slew Rate"]
3367 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
3368 }
3369 }
3370 #[doc = "Drive Strength Field"]
3371 pub mod DSE {
3372 pub const offset: u32 = 3;
3373 pub const mask: u32 = 0x07 << offset;
3374 pub mod R {}
3375 pub mod W {}
3376 pub mod RW {
3377 #[doc = "output driver disabled;"]
3378 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
3379 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
3380 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3381 #[doc = "R0/2"]
3382 pub const DSE_2_R0_2: u32 = 0x02;
3383 #[doc = "R0/3"]
3384 pub const DSE_3_R0_3: u32 = 0x03;
3385 #[doc = "R0/4"]
3386 pub const DSE_4_R0_4: u32 = 0x04;
3387 #[doc = "R0/5"]
3388 pub const DSE_5_R0_5: u32 = 0x05;
3389 #[doc = "R0/6"]
3390 pub const DSE_6_R0_6: u32 = 0x06;
3391 #[doc = "R0/7"]
3392 pub const DSE_7_R0_7: u32 = 0x07;
3393 }
3394 }
3395 #[doc = "Speed Field"]
3396 pub mod SPEED {
3397 pub const offset: u32 = 6;
3398 pub const mask: u32 = 0x03 << offset;
3399 pub mod R {}
3400 pub mod W {}
3401 pub mod RW {
3402 #[doc = "low(50MHz)"]
3403 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3404 #[doc = "medium(100MHz)"]
3405 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3406 #[doc = "fast(150MHz)"]
3407 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3408 #[doc = "max(200MHz)"]
3409 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3410 }
3411 }
3412 #[doc = "Open Drain Enable Field"]
3413 pub mod ODE {
3414 pub const offset: u32 = 11;
3415 pub const mask: u32 = 0x01 << offset;
3416 pub mod R {}
3417 pub mod W {}
3418 pub mod RW {
3419 #[doc = "Open Drain Disabled"]
3420 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3421 #[doc = "Open Drain Enabled"]
3422 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3423 }
3424 }
3425 #[doc = "Pull / Keep Enable Field"]
3426 pub mod PKE {
3427 pub const offset: u32 = 12;
3428 pub const mask: u32 = 0x01 << offset;
3429 pub mod R {}
3430 pub mod W {}
3431 pub mod RW {
3432 #[doc = "Pull/Keeper Disabled"]
3433 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3434 #[doc = "Pull/Keeper Enabled"]
3435 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3436 }
3437 }
3438 #[doc = "Pull / Keep Select Field"]
3439 pub mod PUE {
3440 pub const offset: u32 = 13;
3441 pub const mask: u32 = 0x01 << offset;
3442 pub mod R {}
3443 pub mod W {}
3444 pub mod RW {
3445 #[doc = "Keeper"]
3446 pub const PUE_0_KEEPER: u32 = 0;
3447 #[doc = "Pull"]
3448 pub const PUE_1_PULL: u32 = 0x01;
3449 }
3450 }
3451 #[doc = "Pull Up / Down Config. Field"]
3452 pub mod PUS {
3453 pub const offset: u32 = 14;
3454 pub const mask: u32 = 0x03 << offset;
3455 pub mod R {}
3456 pub mod W {}
3457 pub mod RW {
3458 #[doc = "100K Ohm Pull Down"]
3459 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3460 #[doc = "47K Ohm Pull Up"]
3461 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3462 #[doc = "100K Ohm Pull Up"]
3463 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3464 #[doc = "22K Ohm Pull Up"]
3465 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3466 }
3467 }
3468 #[doc = "Hyst. Enable Field"]
3469 pub mod HYS {
3470 pub const offset: u32 = 16;
3471 pub const mask: u32 = 0x01 << offset;
3472 pub mod R {}
3473 pub mod W {}
3474 pub mod RW {
3475 #[doc = "Hysteresis Disabled"]
3476 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3477 #[doc = "Hysteresis Enabled"]
3478 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3479 }
3480 }
3481}
3482#[doc = "SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register"]
3483pub mod SW_PAD_CTL_PAD_GPIO_AD_02 {
3484 #[doc = "Slew Rate Field"]
3485 pub mod SRE {
3486 pub const offset: u32 = 0;
3487 pub const mask: u32 = 0x01 << offset;
3488 pub mod R {}
3489 pub mod W {}
3490 pub mod RW {
3491 #[doc = "Slow Slew Rate"]
3492 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
3493 #[doc = "Fast Slew Rate"]
3494 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
3495 }
3496 }
3497 #[doc = "Drive Strength Field"]
3498 pub mod DSE {
3499 pub const offset: u32 = 3;
3500 pub const mask: u32 = 0x07 << offset;
3501 pub mod R {}
3502 pub mod W {}
3503 pub mod RW {
3504 #[doc = "output driver disabled;"]
3505 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
3506 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
3507 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3508 #[doc = "R0/2"]
3509 pub const DSE_2_R0_2: u32 = 0x02;
3510 #[doc = "R0/3"]
3511 pub const DSE_3_R0_3: u32 = 0x03;
3512 #[doc = "R0/4"]
3513 pub const DSE_4_R0_4: u32 = 0x04;
3514 #[doc = "R0/5"]
3515 pub const DSE_5_R0_5: u32 = 0x05;
3516 #[doc = "R0/6"]
3517 pub const DSE_6_R0_6: u32 = 0x06;
3518 #[doc = "R0/7"]
3519 pub const DSE_7_R0_7: u32 = 0x07;
3520 }
3521 }
3522 #[doc = "Speed Field"]
3523 pub mod SPEED {
3524 pub const offset: u32 = 6;
3525 pub const mask: u32 = 0x03 << offset;
3526 pub mod R {}
3527 pub mod W {}
3528 pub mod RW {
3529 #[doc = "low(50MHz)"]
3530 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3531 #[doc = "medium(100MHz)"]
3532 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3533 #[doc = "fast(150MHz)"]
3534 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3535 #[doc = "max(200MHz)"]
3536 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3537 }
3538 }
3539 #[doc = "Open Drain Enable Field"]
3540 pub mod ODE {
3541 pub const offset: u32 = 11;
3542 pub const mask: u32 = 0x01 << offset;
3543 pub mod R {}
3544 pub mod W {}
3545 pub mod RW {
3546 #[doc = "Open Drain Disabled"]
3547 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3548 #[doc = "Open Drain Enabled"]
3549 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3550 }
3551 }
3552 #[doc = "Pull / Keep Enable Field"]
3553 pub mod PKE {
3554 pub const offset: u32 = 12;
3555 pub const mask: u32 = 0x01 << offset;
3556 pub mod R {}
3557 pub mod W {}
3558 pub mod RW {
3559 #[doc = "Pull/Keeper Disabled"]
3560 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3561 #[doc = "Pull/Keeper Enabled"]
3562 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3563 }
3564 }
3565 #[doc = "Pull / Keep Select Field"]
3566 pub mod PUE {
3567 pub const offset: u32 = 13;
3568 pub const mask: u32 = 0x01 << offset;
3569 pub mod R {}
3570 pub mod W {}
3571 pub mod RW {
3572 #[doc = "Keeper"]
3573 pub const PUE_0_KEEPER: u32 = 0;
3574 #[doc = "Pull"]
3575 pub const PUE_1_PULL: u32 = 0x01;
3576 }
3577 }
3578 #[doc = "Pull Up / Down Config. Field"]
3579 pub mod PUS {
3580 pub const offset: u32 = 14;
3581 pub const mask: u32 = 0x03 << offset;
3582 pub mod R {}
3583 pub mod W {}
3584 pub mod RW {
3585 #[doc = "100K Ohm Pull Down"]
3586 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3587 #[doc = "47K Ohm Pull Up"]
3588 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3589 #[doc = "100K Ohm Pull Up"]
3590 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3591 #[doc = "22K Ohm Pull Up"]
3592 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3593 }
3594 }
3595 #[doc = "Hyst. Enable Field"]
3596 pub mod HYS {
3597 pub const offset: u32 = 16;
3598 pub const mask: u32 = 0x01 << offset;
3599 pub mod R {}
3600 pub mod W {}
3601 pub mod RW {
3602 #[doc = "Hysteresis Disabled"]
3603 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3604 #[doc = "Hysteresis Enabled"]
3605 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3606 }
3607 }
3608}
3609#[doc = "SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register"]
3610pub mod SW_PAD_CTL_PAD_GPIO_AD_01 {
3611 #[doc = "Slew Rate Field"]
3612 pub mod SRE {
3613 pub const offset: u32 = 0;
3614 pub const mask: u32 = 0x01 << offset;
3615 pub mod R {}
3616 pub mod W {}
3617 pub mod RW {
3618 #[doc = "Slow Slew Rate"]
3619 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
3620 #[doc = "Fast Slew Rate"]
3621 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
3622 }
3623 }
3624 #[doc = "Drive Strength Field"]
3625 pub mod DSE {
3626 pub const offset: u32 = 3;
3627 pub const mask: u32 = 0x07 << offset;
3628 pub mod R {}
3629 pub mod W {}
3630 pub mod RW {
3631 #[doc = "output driver disabled;"]
3632 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
3633 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
3634 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3635 #[doc = "R0/2"]
3636 pub const DSE_2_R0_2: u32 = 0x02;
3637 #[doc = "R0/3"]
3638 pub const DSE_3_R0_3: u32 = 0x03;
3639 #[doc = "R0/4"]
3640 pub const DSE_4_R0_4: u32 = 0x04;
3641 #[doc = "R0/5"]
3642 pub const DSE_5_R0_5: u32 = 0x05;
3643 #[doc = "R0/6"]
3644 pub const DSE_6_R0_6: u32 = 0x06;
3645 #[doc = "R0/7"]
3646 pub const DSE_7_R0_7: u32 = 0x07;
3647 }
3648 }
3649 #[doc = "Speed Field"]
3650 pub mod SPEED {
3651 pub const offset: u32 = 6;
3652 pub const mask: u32 = 0x03 << offset;
3653 pub mod R {}
3654 pub mod W {}
3655 pub mod RW {
3656 #[doc = "low(50MHz)"]
3657 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3658 #[doc = "medium(100MHz)"]
3659 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3660 #[doc = "fast(150MHz)"]
3661 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3662 #[doc = "max(200MHz)"]
3663 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3664 }
3665 }
3666 #[doc = "Open Drain Enable Field"]
3667 pub mod ODE {
3668 pub const offset: u32 = 11;
3669 pub const mask: u32 = 0x01 << offset;
3670 pub mod R {}
3671 pub mod W {}
3672 pub mod RW {
3673 #[doc = "Open Drain Disabled"]
3674 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3675 #[doc = "Open Drain Enabled"]
3676 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3677 }
3678 }
3679 #[doc = "Pull / Keep Enable Field"]
3680 pub mod PKE {
3681 pub const offset: u32 = 12;
3682 pub const mask: u32 = 0x01 << offset;
3683 pub mod R {}
3684 pub mod W {}
3685 pub mod RW {
3686 #[doc = "Pull/Keeper Disabled"]
3687 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3688 #[doc = "Pull/Keeper Enabled"]
3689 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3690 }
3691 }
3692 #[doc = "Pull / Keep Select Field"]
3693 pub mod PUE {
3694 pub const offset: u32 = 13;
3695 pub const mask: u32 = 0x01 << offset;
3696 pub mod R {}
3697 pub mod W {}
3698 pub mod RW {
3699 #[doc = "Keeper"]
3700 pub const PUE_0_KEEPER: u32 = 0;
3701 #[doc = "Pull"]
3702 pub const PUE_1_PULL: u32 = 0x01;
3703 }
3704 }
3705 #[doc = "Pull Up / Down Config. Field"]
3706 pub mod PUS {
3707 pub const offset: u32 = 14;
3708 pub const mask: u32 = 0x03 << offset;
3709 pub mod R {}
3710 pub mod W {}
3711 pub mod RW {
3712 #[doc = "100K Ohm Pull Down"]
3713 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3714 #[doc = "47K Ohm Pull Up"]
3715 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3716 #[doc = "100K Ohm Pull Up"]
3717 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3718 #[doc = "22K Ohm Pull Up"]
3719 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3720 }
3721 }
3722 #[doc = "Hyst. Enable Field"]
3723 pub mod HYS {
3724 pub const offset: u32 = 16;
3725 pub const mask: u32 = 0x01 << offset;
3726 pub mod R {}
3727 pub mod W {}
3728 pub mod RW {
3729 #[doc = "Hysteresis Disabled"]
3730 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3731 #[doc = "Hysteresis Enabled"]
3732 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3733 }
3734 }
3735}
3736#[doc = "SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register"]
3737pub mod SW_PAD_CTL_PAD_GPIO_AD_00 {
3738 #[doc = "Slew Rate Field"]
3739 pub mod SRE {
3740 pub const offset: u32 = 0;
3741 pub const mask: u32 = 0x01 << offset;
3742 pub mod R {}
3743 pub mod W {}
3744 pub mod RW {
3745 #[doc = "Slow Slew Rate"]
3746 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
3747 #[doc = "Fast Slew Rate"]
3748 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
3749 }
3750 }
3751 #[doc = "Drive Strength Field"]
3752 pub mod DSE {
3753 pub const offset: u32 = 3;
3754 pub const mask: u32 = 0x07 << offset;
3755 pub mod R {}
3756 pub mod W {}
3757 pub mod RW {
3758 #[doc = "output driver disabled;"]
3759 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
3760 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
3761 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3762 #[doc = "R0/2"]
3763 pub const DSE_2_R0_2: u32 = 0x02;
3764 #[doc = "R0/3"]
3765 pub const DSE_3_R0_3: u32 = 0x03;
3766 #[doc = "R0/4"]
3767 pub const DSE_4_R0_4: u32 = 0x04;
3768 #[doc = "R0/5"]
3769 pub const DSE_5_R0_5: u32 = 0x05;
3770 #[doc = "R0/6"]
3771 pub const DSE_6_R0_6: u32 = 0x06;
3772 #[doc = "R0/7"]
3773 pub const DSE_7_R0_7: u32 = 0x07;
3774 }
3775 }
3776 #[doc = "Speed Field"]
3777 pub mod SPEED {
3778 pub const offset: u32 = 6;
3779 pub const mask: u32 = 0x03 << offset;
3780 pub mod R {}
3781 pub mod W {}
3782 pub mod RW {
3783 #[doc = "low(50MHz)"]
3784 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3785 #[doc = "medium(100MHz)"]
3786 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3787 #[doc = "fast(150MHz)"]
3788 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3789 #[doc = "max(200MHz)"]
3790 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3791 }
3792 }
3793 #[doc = "Open Drain Enable Field"]
3794 pub mod ODE {
3795 pub const offset: u32 = 11;
3796 pub const mask: u32 = 0x01 << offset;
3797 pub mod R {}
3798 pub mod W {}
3799 pub mod RW {
3800 #[doc = "Open Drain Disabled"]
3801 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3802 #[doc = "Open Drain Enabled"]
3803 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3804 }
3805 }
3806 #[doc = "Pull / Keep Enable Field"]
3807 pub mod PKE {
3808 pub const offset: u32 = 12;
3809 pub const mask: u32 = 0x01 << offset;
3810 pub mod R {}
3811 pub mod W {}
3812 pub mod RW {
3813 #[doc = "Pull/Keeper Disabled"]
3814 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3815 #[doc = "Pull/Keeper Enabled"]
3816 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3817 }
3818 }
3819 #[doc = "Pull / Keep Select Field"]
3820 pub mod PUE {
3821 pub const offset: u32 = 13;
3822 pub const mask: u32 = 0x01 << offset;
3823 pub mod R {}
3824 pub mod W {}
3825 pub mod RW {
3826 #[doc = "Keeper"]
3827 pub const PUE_0_KEEPER: u32 = 0;
3828 #[doc = "Pull"]
3829 pub const PUE_1_PULL: u32 = 0x01;
3830 }
3831 }
3832 #[doc = "Pull Up / Down Config. Field"]
3833 pub mod PUS {
3834 pub const offset: u32 = 14;
3835 pub const mask: u32 = 0x03 << offset;
3836 pub mod R {}
3837 pub mod W {}
3838 pub mod RW {
3839 #[doc = "100K Ohm Pull Down"]
3840 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3841 #[doc = "47K Ohm Pull Up"]
3842 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3843 #[doc = "100K Ohm Pull Up"]
3844 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3845 #[doc = "22K Ohm Pull Up"]
3846 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3847 }
3848 }
3849 #[doc = "Hyst. Enable Field"]
3850 pub mod HYS {
3851 pub const offset: u32 = 16;
3852 pub const mask: u32 = 0x01 << offset;
3853 pub mod R {}
3854 pub mod W {}
3855 pub mod RW {
3856 #[doc = "Hysteresis Disabled"]
3857 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3858 #[doc = "Hysteresis Enabled"]
3859 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3860 }
3861 }
3862}
3863#[doc = "SW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register"]
3864pub mod SW_PAD_CTL_PAD_GPIO_SD_14 {
3865 #[doc = "Slew Rate Field"]
3866 pub mod SRE {
3867 pub const offset: u32 = 0;
3868 pub const mask: u32 = 0x01 << offset;
3869 pub mod R {}
3870 pub mod W {}
3871 pub mod RW {
3872 #[doc = "Slow Slew Rate"]
3873 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
3874 #[doc = "Fast Slew Rate"]
3875 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
3876 }
3877 }
3878 #[doc = "Drive Strength Field"]
3879 pub mod DSE {
3880 pub const offset: u32 = 3;
3881 pub const mask: u32 = 0x07 << offset;
3882 pub mod R {}
3883 pub mod W {}
3884 pub mod RW {
3885 #[doc = "output driver disabled;"]
3886 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
3887 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
3888 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
3889 #[doc = "R0/2"]
3890 pub const DSE_2_R0_2: u32 = 0x02;
3891 #[doc = "R0/3"]
3892 pub const DSE_3_R0_3: u32 = 0x03;
3893 #[doc = "R0/4"]
3894 pub const DSE_4_R0_4: u32 = 0x04;
3895 #[doc = "R0/5"]
3896 pub const DSE_5_R0_5: u32 = 0x05;
3897 #[doc = "R0/6"]
3898 pub const DSE_6_R0_6: u32 = 0x06;
3899 #[doc = "R0/7"]
3900 pub const DSE_7_R0_7: u32 = 0x07;
3901 }
3902 }
3903 #[doc = "Speed Field"]
3904 pub mod SPEED {
3905 pub const offset: u32 = 6;
3906 pub const mask: u32 = 0x03 << offset;
3907 pub mod R {}
3908 pub mod W {}
3909 pub mod RW {
3910 #[doc = "low(50MHz)"]
3911 pub const SPEED_0_LOW_50MHZ: u32 = 0;
3912 #[doc = "medium(100MHz)"]
3913 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
3914 #[doc = "fast(150MHz)"]
3915 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
3916 #[doc = "max(200MHz)"]
3917 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
3918 }
3919 }
3920 #[doc = "Open Drain Enable Field"]
3921 pub mod ODE {
3922 pub const offset: u32 = 11;
3923 pub const mask: u32 = 0x01 << offset;
3924 pub mod R {}
3925 pub mod W {}
3926 pub mod RW {
3927 #[doc = "Open Drain Disabled"]
3928 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
3929 #[doc = "Open Drain Enabled"]
3930 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
3931 }
3932 }
3933 #[doc = "Pull / Keep Enable Field"]
3934 pub mod PKE {
3935 pub const offset: u32 = 12;
3936 pub const mask: u32 = 0x01 << offset;
3937 pub mod R {}
3938 pub mod W {}
3939 pub mod RW {
3940 #[doc = "Pull/Keeper Disabled"]
3941 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
3942 #[doc = "Pull/Keeper Enabled"]
3943 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
3944 }
3945 }
3946 #[doc = "Pull / Keep Select Field"]
3947 pub mod PUE {
3948 pub const offset: u32 = 13;
3949 pub const mask: u32 = 0x01 << offset;
3950 pub mod R {}
3951 pub mod W {}
3952 pub mod RW {
3953 #[doc = "Keeper"]
3954 pub const PUE_0_KEEPER: u32 = 0;
3955 #[doc = "Pull"]
3956 pub const PUE_1_PULL: u32 = 0x01;
3957 }
3958 }
3959 #[doc = "Pull Up / Down Config. Field"]
3960 pub mod PUS {
3961 pub const offset: u32 = 14;
3962 pub const mask: u32 = 0x03 << offset;
3963 pub mod R {}
3964 pub mod W {}
3965 pub mod RW {
3966 #[doc = "100K Ohm Pull Down"]
3967 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
3968 #[doc = "47K Ohm Pull Up"]
3969 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
3970 #[doc = "100K Ohm Pull Up"]
3971 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
3972 #[doc = "22K Ohm Pull Up"]
3973 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
3974 }
3975 }
3976 #[doc = "Hyst. Enable Field"]
3977 pub mod HYS {
3978 pub const offset: u32 = 16;
3979 pub const mask: u32 = 0x01 << offset;
3980 pub mod R {}
3981 pub mod W {}
3982 pub mod RW {
3983 #[doc = "Hysteresis Disabled"]
3984 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
3985 #[doc = "Hysteresis Enabled"]
3986 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
3987 }
3988 }
3989}
3990#[doc = "SW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register"]
3991pub mod SW_PAD_CTL_PAD_GPIO_SD_13 {
3992 #[doc = "Slew Rate Field"]
3993 pub mod SRE {
3994 pub const offset: u32 = 0;
3995 pub const mask: u32 = 0x01 << offset;
3996 pub mod R {}
3997 pub mod W {}
3998 pub mod RW {
3999 #[doc = "Slow Slew Rate"]
4000 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4001 #[doc = "Fast Slew Rate"]
4002 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4003 }
4004 }
4005 #[doc = "Drive Strength Field"]
4006 pub mod DSE {
4007 pub const offset: u32 = 3;
4008 pub const mask: u32 = 0x07 << offset;
4009 pub mod R {}
4010 pub mod W {}
4011 pub mod RW {
4012 #[doc = "output driver disabled;"]
4013 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4014 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4015 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4016 #[doc = "R0/2"]
4017 pub const DSE_2_R0_2: u32 = 0x02;
4018 #[doc = "R0/3"]
4019 pub const DSE_3_R0_3: u32 = 0x03;
4020 #[doc = "R0/4"]
4021 pub const DSE_4_R0_4: u32 = 0x04;
4022 #[doc = "R0/5"]
4023 pub const DSE_5_R0_5: u32 = 0x05;
4024 #[doc = "R0/6"]
4025 pub const DSE_6_R0_6: u32 = 0x06;
4026 #[doc = "R0/7"]
4027 pub const DSE_7_R0_7: u32 = 0x07;
4028 }
4029 }
4030 #[doc = "Speed Field"]
4031 pub mod SPEED {
4032 pub const offset: u32 = 6;
4033 pub const mask: u32 = 0x03 << offset;
4034 pub mod R {}
4035 pub mod W {}
4036 pub mod RW {
4037 #[doc = "low(50MHz)"]
4038 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4039 #[doc = "medium(100MHz)"]
4040 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4041 #[doc = "fast(150MHz)"]
4042 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4043 #[doc = "max(200MHz)"]
4044 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4045 }
4046 }
4047 #[doc = "Open Drain Enable Field"]
4048 pub mod ODE {
4049 pub const offset: u32 = 11;
4050 pub const mask: u32 = 0x01 << offset;
4051 pub mod R {}
4052 pub mod W {}
4053 pub mod RW {
4054 #[doc = "Open Drain Disabled"]
4055 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4056 #[doc = "Open Drain Enabled"]
4057 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4058 }
4059 }
4060 #[doc = "Pull / Keep Enable Field"]
4061 pub mod PKE {
4062 pub const offset: u32 = 12;
4063 pub const mask: u32 = 0x01 << offset;
4064 pub mod R {}
4065 pub mod W {}
4066 pub mod RW {
4067 #[doc = "Pull/Keeper Disabled"]
4068 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4069 #[doc = "Pull/Keeper Enabled"]
4070 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4071 }
4072 }
4073 #[doc = "Pull / Keep Select Field"]
4074 pub mod PUE {
4075 pub const offset: u32 = 13;
4076 pub const mask: u32 = 0x01 << offset;
4077 pub mod R {}
4078 pub mod W {}
4079 pub mod RW {
4080 #[doc = "Keeper"]
4081 pub const PUE_0_KEEPER: u32 = 0;
4082 #[doc = "Pull"]
4083 pub const PUE_1_PULL: u32 = 0x01;
4084 }
4085 }
4086 #[doc = "Pull Up / Down Config. Field"]
4087 pub mod PUS {
4088 pub const offset: u32 = 14;
4089 pub const mask: u32 = 0x03 << offset;
4090 pub mod R {}
4091 pub mod W {}
4092 pub mod RW {
4093 #[doc = "100K Ohm Pull Down"]
4094 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4095 #[doc = "47K Ohm Pull Up"]
4096 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4097 #[doc = "100K Ohm Pull Up"]
4098 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4099 #[doc = "22K Ohm Pull Up"]
4100 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4101 }
4102 }
4103 #[doc = "Hyst. Enable Field"]
4104 pub mod HYS {
4105 pub const offset: u32 = 16;
4106 pub const mask: u32 = 0x01 << offset;
4107 pub mod R {}
4108 pub mod W {}
4109 pub mod RW {
4110 #[doc = "Hysteresis Disabled"]
4111 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
4112 #[doc = "Hysteresis Enabled"]
4113 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
4114 }
4115 }
4116}
4117#[doc = "SW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register"]
4118pub mod SW_PAD_CTL_PAD_GPIO_SD_12 {
4119 #[doc = "Slew Rate Field"]
4120 pub mod SRE {
4121 pub const offset: u32 = 0;
4122 pub const mask: u32 = 0x01 << offset;
4123 pub mod R {}
4124 pub mod W {}
4125 pub mod RW {
4126 #[doc = "Slow Slew Rate"]
4127 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4128 #[doc = "Fast Slew Rate"]
4129 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4130 }
4131 }
4132 #[doc = "Drive Strength Field"]
4133 pub mod DSE {
4134 pub const offset: u32 = 3;
4135 pub const mask: u32 = 0x07 << offset;
4136 pub mod R {}
4137 pub mod W {}
4138 pub mod RW {
4139 #[doc = "output driver disabled;"]
4140 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4141 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4142 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4143 #[doc = "R0/2"]
4144 pub const DSE_2_R0_2: u32 = 0x02;
4145 #[doc = "R0/3"]
4146 pub const DSE_3_R0_3: u32 = 0x03;
4147 #[doc = "R0/4"]
4148 pub const DSE_4_R0_4: u32 = 0x04;
4149 #[doc = "R0/5"]
4150 pub const DSE_5_R0_5: u32 = 0x05;
4151 #[doc = "R0/6"]
4152 pub const DSE_6_R0_6: u32 = 0x06;
4153 #[doc = "R0/7"]
4154 pub const DSE_7_R0_7: u32 = 0x07;
4155 }
4156 }
4157 #[doc = "Speed Field"]
4158 pub mod SPEED {
4159 pub const offset: u32 = 6;
4160 pub const mask: u32 = 0x03 << offset;
4161 pub mod R {}
4162 pub mod W {}
4163 pub mod RW {
4164 #[doc = "low(50MHz)"]
4165 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4166 #[doc = "medium(100MHz)"]
4167 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4168 #[doc = "fast(150MHz)"]
4169 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4170 #[doc = "max(200MHz)"]
4171 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4172 }
4173 }
4174 #[doc = "Open Drain Enable Field"]
4175 pub mod ODE {
4176 pub const offset: u32 = 11;
4177 pub const mask: u32 = 0x01 << offset;
4178 pub mod R {}
4179 pub mod W {}
4180 pub mod RW {
4181 #[doc = "Open Drain Disabled"]
4182 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4183 #[doc = "Open Drain Enabled"]
4184 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4185 }
4186 }
4187 #[doc = "Pull / Keep Enable Field"]
4188 pub mod PKE {
4189 pub const offset: u32 = 12;
4190 pub const mask: u32 = 0x01 << offset;
4191 pub mod R {}
4192 pub mod W {}
4193 pub mod RW {
4194 #[doc = "Pull/Keeper Disabled"]
4195 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4196 #[doc = "Pull/Keeper Enabled"]
4197 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4198 }
4199 }
4200 #[doc = "Pull / Keep Select Field"]
4201 pub mod PUE {
4202 pub const offset: u32 = 13;
4203 pub const mask: u32 = 0x01 << offset;
4204 pub mod R {}
4205 pub mod W {}
4206 pub mod RW {
4207 #[doc = "Keeper"]
4208 pub const PUE_0_KEEPER: u32 = 0;
4209 #[doc = "Pull"]
4210 pub const PUE_1_PULL: u32 = 0x01;
4211 }
4212 }
4213 #[doc = "Pull Up / Down Config. Field"]
4214 pub mod PUS {
4215 pub const offset: u32 = 14;
4216 pub const mask: u32 = 0x03 << offset;
4217 pub mod R {}
4218 pub mod W {}
4219 pub mod RW {
4220 #[doc = "100K Ohm Pull Down"]
4221 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4222 #[doc = "47K Ohm Pull Up"]
4223 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4224 #[doc = "100K Ohm Pull Up"]
4225 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4226 #[doc = "22K Ohm Pull Up"]
4227 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4228 }
4229 }
4230 #[doc = "Hyst. Enable Field"]
4231 pub mod HYS {
4232 pub const offset: u32 = 16;
4233 pub const mask: u32 = 0x01 << offset;
4234 pub mod R {}
4235 pub mod W {}
4236 pub mod RW {
4237 #[doc = "Hysteresis Disabled"]
4238 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
4239 #[doc = "Hysteresis Enabled"]
4240 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
4241 }
4242 }
4243}
4244#[doc = "SW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register"]
4245pub mod SW_PAD_CTL_PAD_GPIO_SD_11 {
4246 #[doc = "Slew Rate Field"]
4247 pub mod SRE {
4248 pub const offset: u32 = 0;
4249 pub const mask: u32 = 0x01 << offset;
4250 pub mod R {}
4251 pub mod W {}
4252 pub mod RW {
4253 #[doc = "Slow Slew Rate"]
4254 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4255 #[doc = "Fast Slew Rate"]
4256 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4257 }
4258 }
4259 #[doc = "Drive Strength Field"]
4260 pub mod DSE {
4261 pub const offset: u32 = 3;
4262 pub const mask: u32 = 0x07 << offset;
4263 pub mod R {}
4264 pub mod W {}
4265 pub mod RW {
4266 #[doc = "output driver disabled;"]
4267 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4268 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4269 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4270 #[doc = "R0/2"]
4271 pub const DSE_2_R0_2: u32 = 0x02;
4272 #[doc = "R0/3"]
4273 pub const DSE_3_R0_3: u32 = 0x03;
4274 #[doc = "R0/4"]
4275 pub const DSE_4_R0_4: u32 = 0x04;
4276 #[doc = "R0/5"]
4277 pub const DSE_5_R0_5: u32 = 0x05;
4278 #[doc = "R0/6"]
4279 pub const DSE_6_R0_6: u32 = 0x06;
4280 #[doc = "R0/7"]
4281 pub const DSE_7_R0_7: u32 = 0x07;
4282 }
4283 }
4284 #[doc = "Speed Field"]
4285 pub mod SPEED {
4286 pub const offset: u32 = 6;
4287 pub const mask: u32 = 0x03 << offset;
4288 pub mod R {}
4289 pub mod W {}
4290 pub mod RW {
4291 #[doc = "low(50MHz)"]
4292 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4293 #[doc = "medium(100MHz)"]
4294 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4295 #[doc = "fast(150MHz)"]
4296 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4297 #[doc = "max(200MHz)"]
4298 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4299 }
4300 }
4301 #[doc = "Open Drain Enable Field"]
4302 pub mod ODE {
4303 pub const offset: u32 = 11;
4304 pub const mask: u32 = 0x01 << offset;
4305 pub mod R {}
4306 pub mod W {}
4307 pub mod RW {
4308 #[doc = "Open Drain Disabled"]
4309 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4310 #[doc = "Open Drain Enabled"]
4311 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4312 }
4313 }
4314 #[doc = "Pull / Keep Enable Field"]
4315 pub mod PKE {
4316 pub const offset: u32 = 12;
4317 pub const mask: u32 = 0x01 << offset;
4318 pub mod R {}
4319 pub mod W {}
4320 pub mod RW {
4321 #[doc = "Pull/Keeper Disabled"]
4322 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4323 #[doc = "Pull/Keeper Enabled"]
4324 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4325 }
4326 }
4327 #[doc = "Pull / Keep Select Field"]
4328 pub mod PUE {
4329 pub const offset: u32 = 13;
4330 pub const mask: u32 = 0x01 << offset;
4331 pub mod R {}
4332 pub mod W {}
4333 pub mod RW {
4334 #[doc = "Keeper"]
4335 pub const PUE_0_KEEPER: u32 = 0;
4336 #[doc = "Pull"]
4337 pub const PUE_1_PULL: u32 = 0x01;
4338 }
4339 }
4340 #[doc = "Pull Up / Down Config. Field"]
4341 pub mod PUS {
4342 pub const offset: u32 = 14;
4343 pub const mask: u32 = 0x03 << offset;
4344 pub mod R {}
4345 pub mod W {}
4346 pub mod RW {
4347 #[doc = "100K Ohm Pull Down"]
4348 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4349 #[doc = "47K Ohm Pull Up"]
4350 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4351 #[doc = "100K Ohm Pull Up"]
4352 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4353 #[doc = "22K Ohm Pull Up"]
4354 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4355 }
4356 }
4357 #[doc = "Hyst. Enable Field"]
4358 pub mod HYS {
4359 pub const offset: u32 = 16;
4360 pub const mask: u32 = 0x01 << offset;
4361 pub mod R {}
4362 pub mod W {}
4363 pub mod RW {
4364 #[doc = "Hysteresis Disabled"]
4365 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
4366 #[doc = "Hysteresis Enabled"]
4367 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
4368 }
4369 }
4370}
4371#[doc = "SW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register"]
4372pub mod SW_PAD_CTL_PAD_GPIO_SD_10 {
4373 #[doc = "Slew Rate Field"]
4374 pub mod SRE {
4375 pub const offset: u32 = 0;
4376 pub const mask: u32 = 0x01 << offset;
4377 pub mod R {}
4378 pub mod W {}
4379 pub mod RW {
4380 #[doc = "Slow Slew Rate"]
4381 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4382 #[doc = "Fast Slew Rate"]
4383 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4384 }
4385 }
4386 #[doc = "Drive Strength Field"]
4387 pub mod DSE {
4388 pub const offset: u32 = 3;
4389 pub const mask: u32 = 0x07 << offset;
4390 pub mod R {}
4391 pub mod W {}
4392 pub mod RW {
4393 #[doc = "output driver disabled;"]
4394 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4395 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4396 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4397 #[doc = "R0/2"]
4398 pub const DSE_2_R0_2: u32 = 0x02;
4399 #[doc = "R0/3"]
4400 pub const DSE_3_R0_3: u32 = 0x03;
4401 #[doc = "R0/4"]
4402 pub const DSE_4_R0_4: u32 = 0x04;
4403 #[doc = "R0/5"]
4404 pub const DSE_5_R0_5: u32 = 0x05;
4405 #[doc = "R0/6"]
4406 pub const DSE_6_R0_6: u32 = 0x06;
4407 #[doc = "R0/7"]
4408 pub const DSE_7_R0_7: u32 = 0x07;
4409 }
4410 }
4411 #[doc = "Speed Field"]
4412 pub mod SPEED {
4413 pub const offset: u32 = 6;
4414 pub const mask: u32 = 0x03 << offset;
4415 pub mod R {}
4416 pub mod W {}
4417 pub mod RW {
4418 #[doc = "low(50MHz)"]
4419 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4420 #[doc = "medium(100MHz)"]
4421 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4422 #[doc = "fast(150MHz)"]
4423 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4424 #[doc = "max(200MHz)"]
4425 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4426 }
4427 }
4428 #[doc = "Open Drain Enable Field"]
4429 pub mod ODE {
4430 pub const offset: u32 = 11;
4431 pub const mask: u32 = 0x01 << offset;
4432 pub mod R {}
4433 pub mod W {}
4434 pub mod RW {
4435 #[doc = "Open Drain Disabled"]
4436 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4437 #[doc = "Open Drain Enabled"]
4438 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4439 }
4440 }
4441 #[doc = "Pull / Keep Enable Field"]
4442 pub mod PKE {
4443 pub const offset: u32 = 12;
4444 pub const mask: u32 = 0x01 << offset;
4445 pub mod R {}
4446 pub mod W {}
4447 pub mod RW {
4448 #[doc = "Pull/Keeper Disabled"]
4449 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4450 #[doc = "Pull/Keeper Enabled"]
4451 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4452 }
4453 }
4454 #[doc = "Pull / Keep Select Field"]
4455 pub mod PUE {
4456 pub const offset: u32 = 13;
4457 pub const mask: u32 = 0x01 << offset;
4458 pub mod R {}
4459 pub mod W {}
4460 pub mod RW {
4461 #[doc = "Keeper"]
4462 pub const PUE_0_KEEPER: u32 = 0;
4463 #[doc = "Pull"]
4464 pub const PUE_1_PULL: u32 = 0x01;
4465 }
4466 }
4467 #[doc = "Pull Up / Down Config. Field"]
4468 pub mod PUS {
4469 pub const offset: u32 = 14;
4470 pub const mask: u32 = 0x03 << offset;
4471 pub mod R {}
4472 pub mod W {}
4473 pub mod RW {
4474 #[doc = "100K Ohm Pull Down"]
4475 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4476 #[doc = "47K Ohm Pull Up"]
4477 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4478 #[doc = "100K Ohm Pull Up"]
4479 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4480 #[doc = "22K Ohm Pull Up"]
4481 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4482 }
4483 }
4484 #[doc = "Hyst. Enable Field"]
4485 pub mod HYS {
4486 pub const offset: u32 = 16;
4487 pub const mask: u32 = 0x01 << offset;
4488 pub mod R {}
4489 pub mod W {}
4490 pub mod RW {
4491 #[doc = "Hysteresis Disabled"]
4492 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
4493 #[doc = "Hysteresis Enabled"]
4494 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
4495 }
4496 }
4497}
4498#[doc = "SW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register"]
4499pub mod SW_PAD_CTL_PAD_GPIO_SD_09 {
4500 #[doc = "Slew Rate Field"]
4501 pub mod SRE {
4502 pub const offset: u32 = 0;
4503 pub const mask: u32 = 0x01 << offset;
4504 pub mod R {}
4505 pub mod W {}
4506 pub mod RW {
4507 #[doc = "Slow Slew Rate"]
4508 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4509 #[doc = "Fast Slew Rate"]
4510 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4511 }
4512 }
4513 #[doc = "Drive Strength Field"]
4514 pub mod DSE {
4515 pub const offset: u32 = 3;
4516 pub const mask: u32 = 0x07 << offset;
4517 pub mod R {}
4518 pub mod W {}
4519 pub mod RW {
4520 #[doc = "output driver disabled;"]
4521 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4522 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4523 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4524 #[doc = "R0/2"]
4525 pub const DSE_2_R0_2: u32 = 0x02;
4526 #[doc = "R0/3"]
4527 pub const DSE_3_R0_3: u32 = 0x03;
4528 #[doc = "R0/4"]
4529 pub const DSE_4_R0_4: u32 = 0x04;
4530 #[doc = "R0/5"]
4531 pub const DSE_5_R0_5: u32 = 0x05;
4532 #[doc = "R0/6"]
4533 pub const DSE_6_R0_6: u32 = 0x06;
4534 #[doc = "R0/7"]
4535 pub const DSE_7_R0_7: u32 = 0x07;
4536 }
4537 }
4538 #[doc = "Speed Field"]
4539 pub mod SPEED {
4540 pub const offset: u32 = 6;
4541 pub const mask: u32 = 0x03 << offset;
4542 pub mod R {}
4543 pub mod W {}
4544 pub mod RW {
4545 #[doc = "low(50MHz)"]
4546 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4547 #[doc = "medium(100MHz)"]
4548 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4549 #[doc = "fast(150MHz)"]
4550 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4551 #[doc = "max(200MHz)"]
4552 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4553 }
4554 }
4555 #[doc = "Open Drain Enable Field"]
4556 pub mod ODE {
4557 pub const offset: u32 = 11;
4558 pub const mask: u32 = 0x01 << offset;
4559 pub mod R {}
4560 pub mod W {}
4561 pub mod RW {
4562 #[doc = "Open Drain Disabled"]
4563 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4564 #[doc = "Open Drain Enabled"]
4565 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4566 }
4567 }
4568 #[doc = "Pull / Keep Enable Field"]
4569 pub mod PKE {
4570 pub const offset: u32 = 12;
4571 pub const mask: u32 = 0x01 << offset;
4572 pub mod R {}
4573 pub mod W {}
4574 pub mod RW {
4575 #[doc = "Pull/Keeper Disabled"]
4576 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4577 #[doc = "Pull/Keeper Enabled"]
4578 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4579 }
4580 }
4581 #[doc = "Pull / Keep Select Field"]
4582 pub mod PUE {
4583 pub const offset: u32 = 13;
4584 pub const mask: u32 = 0x01 << offset;
4585 pub mod R {}
4586 pub mod W {}
4587 pub mod RW {
4588 #[doc = "Keeper"]
4589 pub const PUE_0_KEEPER: u32 = 0;
4590 #[doc = "Pull"]
4591 pub const PUE_1_PULL: u32 = 0x01;
4592 }
4593 }
4594 #[doc = "Pull Up / Down Config. Field"]
4595 pub mod PUS {
4596 pub const offset: u32 = 14;
4597 pub const mask: u32 = 0x03 << offset;
4598 pub mod R {}
4599 pub mod W {}
4600 pub mod RW {
4601 #[doc = "100K Ohm Pull Down"]
4602 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4603 #[doc = "47K Ohm Pull Up"]
4604 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4605 #[doc = "100K Ohm Pull Up"]
4606 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4607 #[doc = "22K Ohm Pull Up"]
4608 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4609 }
4610 }
4611 #[doc = "Hyst. Enable Field"]
4612 pub mod HYS {
4613 pub const offset: u32 = 16;
4614 pub const mask: u32 = 0x01 << offset;
4615 pub mod R {}
4616 pub mod W {}
4617 pub mod RW {
4618 #[doc = "Hysteresis Disabled"]
4619 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
4620 #[doc = "Hysteresis Enabled"]
4621 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
4622 }
4623 }
4624}
4625#[doc = "SW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register"]
4626pub mod SW_PAD_CTL_PAD_GPIO_SD_08 {
4627 #[doc = "Slew Rate Field"]
4628 pub mod SRE {
4629 pub const offset: u32 = 0;
4630 pub const mask: u32 = 0x01 << offset;
4631 pub mod R {}
4632 pub mod W {}
4633 pub mod RW {
4634 #[doc = "Slow Slew Rate"]
4635 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4636 #[doc = "Fast Slew Rate"]
4637 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4638 }
4639 }
4640 #[doc = "Drive Strength Field"]
4641 pub mod DSE {
4642 pub const offset: u32 = 3;
4643 pub const mask: u32 = 0x07 << offset;
4644 pub mod R {}
4645 pub mod W {}
4646 pub mod RW {
4647 #[doc = "output driver disabled;"]
4648 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4649 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4650 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4651 #[doc = "R0/2"]
4652 pub const DSE_2_R0_2: u32 = 0x02;
4653 #[doc = "R0/3"]
4654 pub const DSE_3_R0_3: u32 = 0x03;
4655 #[doc = "R0/4"]
4656 pub const DSE_4_R0_4: u32 = 0x04;
4657 #[doc = "R0/5"]
4658 pub const DSE_5_R0_5: u32 = 0x05;
4659 #[doc = "R0/6"]
4660 pub const DSE_6_R0_6: u32 = 0x06;
4661 #[doc = "R0/7"]
4662 pub const DSE_7_R0_7: u32 = 0x07;
4663 }
4664 }
4665 #[doc = "Speed Field"]
4666 pub mod SPEED {
4667 pub const offset: u32 = 6;
4668 pub const mask: u32 = 0x03 << offset;
4669 pub mod R {}
4670 pub mod W {}
4671 pub mod RW {
4672 #[doc = "low(50MHz)"]
4673 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4674 #[doc = "medium(100MHz)"]
4675 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4676 #[doc = "fast(150MHz)"]
4677 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4678 #[doc = "max(200MHz)"]
4679 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4680 }
4681 }
4682 #[doc = "Open Drain Enable Field"]
4683 pub mod ODE {
4684 pub const offset: u32 = 11;
4685 pub const mask: u32 = 0x01 << offset;
4686 pub mod R {}
4687 pub mod W {}
4688 pub mod RW {
4689 #[doc = "Open Drain Disabled"]
4690 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4691 #[doc = "Open Drain Enabled"]
4692 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4693 }
4694 }
4695 #[doc = "Pull / Keep Enable Field"]
4696 pub mod PKE {
4697 pub const offset: u32 = 12;
4698 pub const mask: u32 = 0x01 << offset;
4699 pub mod R {}
4700 pub mod W {}
4701 pub mod RW {
4702 #[doc = "Pull/Keeper Disabled"]
4703 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4704 #[doc = "Pull/Keeper Enabled"]
4705 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4706 }
4707 }
4708 #[doc = "Pull / Keep Select Field"]
4709 pub mod PUE {
4710 pub const offset: u32 = 13;
4711 pub const mask: u32 = 0x01 << offset;
4712 pub mod R {}
4713 pub mod W {}
4714 pub mod RW {
4715 #[doc = "Keeper"]
4716 pub const PUE_0_KEEPER: u32 = 0;
4717 #[doc = "Pull"]
4718 pub const PUE_1_PULL: u32 = 0x01;
4719 }
4720 }
4721 #[doc = "Pull Up / Down Config. Field"]
4722 pub mod PUS {
4723 pub const offset: u32 = 14;
4724 pub const mask: u32 = 0x03 << offset;
4725 pub mod R {}
4726 pub mod W {}
4727 pub mod RW {
4728 #[doc = "100K Ohm Pull Down"]
4729 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4730 #[doc = "47K Ohm Pull Up"]
4731 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4732 #[doc = "100K Ohm Pull Up"]
4733 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4734 #[doc = "22K Ohm Pull Up"]
4735 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4736 }
4737 }
4738 #[doc = "Hyst. Enable Field"]
4739 pub mod HYS {
4740 pub const offset: u32 = 16;
4741 pub const mask: u32 = 0x01 << offset;
4742 pub mod R {}
4743 pub mod W {}
4744 pub mod RW {
4745 #[doc = "Hysteresis Disabled"]
4746 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
4747 #[doc = "Hysteresis Enabled"]
4748 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
4749 }
4750 }
4751}
4752#[doc = "SW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register"]
4753pub mod SW_PAD_CTL_PAD_GPIO_SD_07 {
4754 #[doc = "Slew Rate Field"]
4755 pub mod SRE {
4756 pub const offset: u32 = 0;
4757 pub const mask: u32 = 0x01 << offset;
4758 pub mod R {}
4759 pub mod W {}
4760 pub mod RW {
4761 #[doc = "Slow Slew Rate"]
4762 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4763 #[doc = "Fast Slew Rate"]
4764 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4765 }
4766 }
4767 #[doc = "Drive Strength Field"]
4768 pub mod DSE {
4769 pub const offset: u32 = 3;
4770 pub const mask: u32 = 0x07 << offset;
4771 pub mod R {}
4772 pub mod W {}
4773 pub mod RW {
4774 #[doc = "output driver disabled;"]
4775 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4776 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4777 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4778 #[doc = "R0/2"]
4779 pub const DSE_2_R0_2: u32 = 0x02;
4780 #[doc = "R0/3"]
4781 pub const DSE_3_R0_3: u32 = 0x03;
4782 #[doc = "R0/4"]
4783 pub const DSE_4_R0_4: u32 = 0x04;
4784 #[doc = "R0/5"]
4785 pub const DSE_5_R0_5: u32 = 0x05;
4786 #[doc = "R0/6"]
4787 pub const DSE_6_R0_6: u32 = 0x06;
4788 #[doc = "R0/7"]
4789 pub const DSE_7_R0_7: u32 = 0x07;
4790 }
4791 }
4792 #[doc = "Speed Field"]
4793 pub mod SPEED {
4794 pub const offset: u32 = 6;
4795 pub const mask: u32 = 0x03 << offset;
4796 pub mod R {}
4797 pub mod W {}
4798 pub mod RW {
4799 #[doc = "low(50MHz)"]
4800 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4801 #[doc = "medium(100MHz)"]
4802 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4803 #[doc = "fast(150MHz)"]
4804 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4805 #[doc = "max(200MHz)"]
4806 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4807 }
4808 }
4809 #[doc = "Open Drain Enable Field"]
4810 pub mod ODE {
4811 pub const offset: u32 = 11;
4812 pub const mask: u32 = 0x01 << offset;
4813 pub mod R {}
4814 pub mod W {}
4815 pub mod RW {
4816 #[doc = "Open Drain Disabled"]
4817 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4818 #[doc = "Open Drain Enabled"]
4819 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4820 }
4821 }
4822 #[doc = "Pull / Keep Enable Field"]
4823 pub mod PKE {
4824 pub const offset: u32 = 12;
4825 pub const mask: u32 = 0x01 << offset;
4826 pub mod R {}
4827 pub mod W {}
4828 pub mod RW {
4829 #[doc = "Pull/Keeper Disabled"]
4830 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4831 #[doc = "Pull/Keeper Enabled"]
4832 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4833 }
4834 }
4835 #[doc = "Pull / Keep Select Field"]
4836 pub mod PUE {
4837 pub const offset: u32 = 13;
4838 pub const mask: u32 = 0x01 << offset;
4839 pub mod R {}
4840 pub mod W {}
4841 pub mod RW {
4842 #[doc = "Keeper"]
4843 pub const PUE_0_KEEPER: u32 = 0;
4844 #[doc = "Pull"]
4845 pub const PUE_1_PULL: u32 = 0x01;
4846 }
4847 }
4848 #[doc = "Pull Up / Down Config. Field"]
4849 pub mod PUS {
4850 pub const offset: u32 = 14;
4851 pub const mask: u32 = 0x03 << offset;
4852 pub mod R {}
4853 pub mod W {}
4854 pub mod RW {
4855 #[doc = "100K Ohm Pull Down"]
4856 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4857 #[doc = "47K Ohm Pull Up"]
4858 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4859 #[doc = "100K Ohm Pull Up"]
4860 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4861 #[doc = "22K Ohm Pull Up"]
4862 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4863 }
4864 }
4865 #[doc = "Hyst. Enable Field"]
4866 pub mod HYS {
4867 pub const offset: u32 = 16;
4868 pub const mask: u32 = 0x01 << offset;
4869 pub mod R {}
4870 pub mod W {}
4871 pub mod RW {
4872 #[doc = "Hysteresis Disabled"]
4873 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
4874 #[doc = "Hysteresis Enabled"]
4875 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
4876 }
4877 }
4878}
4879#[doc = "SW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register"]
4880pub mod SW_PAD_CTL_PAD_GPIO_SD_06 {
4881 #[doc = "Slew Rate Field"]
4882 pub mod SRE {
4883 pub const offset: u32 = 0;
4884 pub const mask: u32 = 0x01 << offset;
4885 pub mod R {}
4886 pub mod W {}
4887 pub mod RW {
4888 #[doc = "Slow Slew Rate"]
4889 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
4890 #[doc = "Fast Slew Rate"]
4891 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
4892 }
4893 }
4894 #[doc = "Drive Strength Field"]
4895 pub mod DSE {
4896 pub const offset: u32 = 3;
4897 pub const mask: u32 = 0x07 << offset;
4898 pub mod R {}
4899 pub mod W {}
4900 pub mod RW {
4901 #[doc = "output driver disabled;"]
4902 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
4903 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
4904 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
4905 #[doc = "R0/2"]
4906 pub const DSE_2_R0_2: u32 = 0x02;
4907 #[doc = "R0/3"]
4908 pub const DSE_3_R0_3: u32 = 0x03;
4909 #[doc = "R0/4"]
4910 pub const DSE_4_R0_4: u32 = 0x04;
4911 #[doc = "R0/5"]
4912 pub const DSE_5_R0_5: u32 = 0x05;
4913 #[doc = "R0/6"]
4914 pub const DSE_6_R0_6: u32 = 0x06;
4915 #[doc = "R0/7"]
4916 pub const DSE_7_R0_7: u32 = 0x07;
4917 }
4918 }
4919 #[doc = "Speed Field"]
4920 pub mod SPEED {
4921 pub const offset: u32 = 6;
4922 pub const mask: u32 = 0x03 << offset;
4923 pub mod R {}
4924 pub mod W {}
4925 pub mod RW {
4926 #[doc = "low(50MHz)"]
4927 pub const SPEED_0_LOW_50MHZ: u32 = 0;
4928 #[doc = "medium(100MHz)"]
4929 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
4930 #[doc = "fast(150MHz)"]
4931 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
4932 #[doc = "max(200MHz)"]
4933 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
4934 }
4935 }
4936 #[doc = "Open Drain Enable Field"]
4937 pub mod ODE {
4938 pub const offset: u32 = 11;
4939 pub const mask: u32 = 0x01 << offset;
4940 pub mod R {}
4941 pub mod W {}
4942 pub mod RW {
4943 #[doc = "Open Drain Disabled"]
4944 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
4945 #[doc = "Open Drain Enabled"]
4946 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
4947 }
4948 }
4949 #[doc = "Pull / Keep Enable Field"]
4950 pub mod PKE {
4951 pub const offset: u32 = 12;
4952 pub const mask: u32 = 0x01 << offset;
4953 pub mod R {}
4954 pub mod W {}
4955 pub mod RW {
4956 #[doc = "Pull/Keeper Disabled"]
4957 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
4958 #[doc = "Pull/Keeper Enabled"]
4959 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
4960 }
4961 }
4962 #[doc = "Pull / Keep Select Field"]
4963 pub mod PUE {
4964 pub const offset: u32 = 13;
4965 pub const mask: u32 = 0x01 << offset;
4966 pub mod R {}
4967 pub mod W {}
4968 pub mod RW {
4969 #[doc = "Keeper"]
4970 pub const PUE_0_KEEPER: u32 = 0;
4971 #[doc = "Pull"]
4972 pub const PUE_1_PULL: u32 = 0x01;
4973 }
4974 }
4975 #[doc = "Pull Up / Down Config. Field"]
4976 pub mod PUS {
4977 pub const offset: u32 = 14;
4978 pub const mask: u32 = 0x03 << offset;
4979 pub mod R {}
4980 pub mod W {}
4981 pub mod RW {
4982 #[doc = "100K Ohm Pull Down"]
4983 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
4984 #[doc = "47K Ohm Pull Up"]
4985 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
4986 #[doc = "100K Ohm Pull Up"]
4987 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
4988 #[doc = "22K Ohm Pull Up"]
4989 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
4990 }
4991 }
4992 #[doc = "Hyst. Enable Field"]
4993 pub mod HYS {
4994 pub const offset: u32 = 16;
4995 pub const mask: u32 = 0x01 << offset;
4996 pub mod R {}
4997 pub mod W {}
4998 pub mod RW {
4999 #[doc = "Hysteresis Disabled"]
5000 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5001 #[doc = "Hysteresis Enabled"]
5002 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5003 }
5004 }
5005}
5006#[doc = "SW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register"]
5007pub mod SW_PAD_CTL_PAD_GPIO_SD_05 {
5008 #[doc = "Slew Rate Field"]
5009 pub mod SRE {
5010 pub const offset: u32 = 0;
5011 pub const mask: u32 = 0x01 << offset;
5012 pub mod R {}
5013 pub mod W {}
5014 pub mod RW {
5015 #[doc = "Slow Slew Rate"]
5016 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5017 #[doc = "Fast Slew Rate"]
5018 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5019 }
5020 }
5021 #[doc = "Drive Strength Field"]
5022 pub mod DSE {
5023 pub const offset: u32 = 3;
5024 pub const mask: u32 = 0x07 << offset;
5025 pub mod R {}
5026 pub mod W {}
5027 pub mod RW {
5028 #[doc = "output driver disabled;"]
5029 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5030 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5031 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5032 #[doc = "R0/2"]
5033 pub const DSE_2_R0_2: u32 = 0x02;
5034 #[doc = "R0/3"]
5035 pub const DSE_3_R0_3: u32 = 0x03;
5036 #[doc = "R0/4"]
5037 pub const DSE_4_R0_4: u32 = 0x04;
5038 #[doc = "R0/5"]
5039 pub const DSE_5_R0_5: u32 = 0x05;
5040 #[doc = "R0/6"]
5041 pub const DSE_6_R0_6: u32 = 0x06;
5042 #[doc = "R0/7"]
5043 pub const DSE_7_R0_7: u32 = 0x07;
5044 }
5045 }
5046 #[doc = "Speed Field"]
5047 pub mod SPEED {
5048 pub const offset: u32 = 6;
5049 pub const mask: u32 = 0x03 << offset;
5050 pub mod R {}
5051 pub mod W {}
5052 pub mod RW {
5053 #[doc = "low(50MHz)"]
5054 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5055 #[doc = "medium(100MHz)"]
5056 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5057 #[doc = "fast(150MHz)"]
5058 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5059 #[doc = "max(200MHz)"]
5060 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5061 }
5062 }
5063 #[doc = "Open Drain Enable Field"]
5064 pub mod ODE {
5065 pub const offset: u32 = 11;
5066 pub const mask: u32 = 0x01 << offset;
5067 pub mod R {}
5068 pub mod W {}
5069 pub mod RW {
5070 #[doc = "Open Drain Disabled"]
5071 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5072 #[doc = "Open Drain Enabled"]
5073 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5074 }
5075 }
5076 #[doc = "Pull / Keep Enable Field"]
5077 pub mod PKE {
5078 pub const offset: u32 = 12;
5079 pub const mask: u32 = 0x01 << offset;
5080 pub mod R {}
5081 pub mod W {}
5082 pub mod RW {
5083 #[doc = "Pull/Keeper Disabled"]
5084 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5085 #[doc = "Pull/Keeper Enabled"]
5086 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5087 }
5088 }
5089 #[doc = "Pull / Keep Select Field"]
5090 pub mod PUE {
5091 pub const offset: u32 = 13;
5092 pub const mask: u32 = 0x01 << offset;
5093 pub mod R {}
5094 pub mod W {}
5095 pub mod RW {
5096 #[doc = "Keeper"]
5097 pub const PUE_0_KEEPER: u32 = 0;
5098 #[doc = "Pull"]
5099 pub const PUE_1_PULL: u32 = 0x01;
5100 }
5101 }
5102 #[doc = "Pull Up / Down Config. Field"]
5103 pub mod PUS {
5104 pub const offset: u32 = 14;
5105 pub const mask: u32 = 0x03 << offset;
5106 pub mod R {}
5107 pub mod W {}
5108 pub mod RW {
5109 #[doc = "100K Ohm Pull Down"]
5110 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
5111 #[doc = "47K Ohm Pull Up"]
5112 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
5113 #[doc = "100K Ohm Pull Up"]
5114 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
5115 #[doc = "22K Ohm Pull Up"]
5116 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
5117 }
5118 }
5119 #[doc = "Hyst. Enable Field"]
5120 pub mod HYS {
5121 pub const offset: u32 = 16;
5122 pub const mask: u32 = 0x01 << offset;
5123 pub mod R {}
5124 pub mod W {}
5125 pub mod RW {
5126 #[doc = "Hysteresis Disabled"]
5127 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5128 #[doc = "Hysteresis Enabled"]
5129 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5130 }
5131 }
5132}
5133#[doc = "SW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register"]
5134pub mod SW_PAD_CTL_PAD_GPIO_SD_04 {
5135 #[doc = "Slew Rate Field"]
5136 pub mod SRE {
5137 pub const offset: u32 = 0;
5138 pub const mask: u32 = 0x01 << offset;
5139 pub mod R {}
5140 pub mod W {}
5141 pub mod RW {
5142 #[doc = "Slow Slew Rate"]
5143 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5144 #[doc = "Fast Slew Rate"]
5145 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5146 }
5147 }
5148 #[doc = "Drive Strength Field"]
5149 pub mod DSE {
5150 pub const offset: u32 = 3;
5151 pub const mask: u32 = 0x07 << offset;
5152 pub mod R {}
5153 pub mod W {}
5154 pub mod RW {
5155 #[doc = "output driver disabled;"]
5156 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5157 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5158 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5159 #[doc = "R0/2"]
5160 pub const DSE_2_R0_2: u32 = 0x02;
5161 #[doc = "R0/3"]
5162 pub const DSE_3_R0_3: u32 = 0x03;
5163 #[doc = "R0/4"]
5164 pub const DSE_4_R0_4: u32 = 0x04;
5165 #[doc = "R0/5"]
5166 pub const DSE_5_R0_5: u32 = 0x05;
5167 #[doc = "R0/6"]
5168 pub const DSE_6_R0_6: u32 = 0x06;
5169 #[doc = "R0/7"]
5170 pub const DSE_7_R0_7: u32 = 0x07;
5171 }
5172 }
5173 #[doc = "Speed Field"]
5174 pub mod SPEED {
5175 pub const offset: u32 = 6;
5176 pub const mask: u32 = 0x03 << offset;
5177 pub mod R {}
5178 pub mod W {}
5179 pub mod RW {
5180 #[doc = "low(50MHz)"]
5181 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5182 #[doc = "medium(100MHz)"]
5183 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5184 #[doc = "fast(150MHz)"]
5185 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5186 #[doc = "max(200MHz)"]
5187 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5188 }
5189 }
5190 #[doc = "Open Drain Enable Field"]
5191 pub mod ODE {
5192 pub const offset: u32 = 11;
5193 pub const mask: u32 = 0x01 << offset;
5194 pub mod R {}
5195 pub mod W {}
5196 pub mod RW {
5197 #[doc = "Open Drain Disabled"]
5198 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5199 #[doc = "Open Drain Enabled"]
5200 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5201 }
5202 }
5203 #[doc = "Pull / Keep Enable Field"]
5204 pub mod PKE {
5205 pub const offset: u32 = 12;
5206 pub const mask: u32 = 0x01 << offset;
5207 pub mod R {}
5208 pub mod W {}
5209 pub mod RW {
5210 #[doc = "Pull/Keeper Disabled"]
5211 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5212 #[doc = "Pull/Keeper Enabled"]
5213 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5214 }
5215 }
5216 #[doc = "Pull / Keep Select Field"]
5217 pub mod PUE {
5218 pub const offset: u32 = 13;
5219 pub const mask: u32 = 0x01 << offset;
5220 pub mod R {}
5221 pub mod W {}
5222 pub mod RW {
5223 #[doc = "Keeper"]
5224 pub const PUE_0_KEEPER: u32 = 0;
5225 #[doc = "Pull"]
5226 pub const PUE_1_PULL: u32 = 0x01;
5227 }
5228 }
5229 #[doc = "Pull Up / Down Config. Field"]
5230 pub mod PUS {
5231 pub const offset: u32 = 14;
5232 pub const mask: u32 = 0x03 << offset;
5233 pub mod R {}
5234 pub mod W {}
5235 pub mod RW {
5236 #[doc = "100K Ohm Pull Down"]
5237 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
5238 #[doc = "47K Ohm Pull Up"]
5239 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
5240 #[doc = "100K Ohm Pull Up"]
5241 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
5242 #[doc = "22K Ohm Pull Up"]
5243 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
5244 }
5245 }
5246 #[doc = "Hyst. Enable Field"]
5247 pub mod HYS {
5248 pub const offset: u32 = 16;
5249 pub const mask: u32 = 0x01 << offset;
5250 pub mod R {}
5251 pub mod W {}
5252 pub mod RW {
5253 #[doc = "Hysteresis Disabled"]
5254 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5255 #[doc = "Hysteresis Enabled"]
5256 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5257 }
5258 }
5259}
5260#[doc = "SW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register"]
5261pub mod SW_PAD_CTL_PAD_GPIO_SD_03 {
5262 #[doc = "Slew Rate Field"]
5263 pub mod SRE {
5264 pub const offset: u32 = 0;
5265 pub const mask: u32 = 0x01 << offset;
5266 pub mod R {}
5267 pub mod W {}
5268 pub mod RW {
5269 #[doc = "Slow Slew Rate"]
5270 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5271 #[doc = "Fast Slew Rate"]
5272 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5273 }
5274 }
5275 #[doc = "Drive Strength Field"]
5276 pub mod DSE {
5277 pub const offset: u32 = 3;
5278 pub const mask: u32 = 0x07 << offset;
5279 pub mod R {}
5280 pub mod W {}
5281 pub mod RW {
5282 #[doc = "output driver disabled;"]
5283 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5284 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5285 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5286 #[doc = "R0/2"]
5287 pub const DSE_2_R0_2: u32 = 0x02;
5288 #[doc = "R0/3"]
5289 pub const DSE_3_R0_3: u32 = 0x03;
5290 #[doc = "R0/4"]
5291 pub const DSE_4_R0_4: u32 = 0x04;
5292 #[doc = "R0/5"]
5293 pub const DSE_5_R0_5: u32 = 0x05;
5294 #[doc = "R0/6"]
5295 pub const DSE_6_R0_6: u32 = 0x06;
5296 #[doc = "R0/7"]
5297 pub const DSE_7_R0_7: u32 = 0x07;
5298 }
5299 }
5300 #[doc = "Speed Field"]
5301 pub mod SPEED {
5302 pub const offset: u32 = 6;
5303 pub const mask: u32 = 0x03 << offset;
5304 pub mod R {}
5305 pub mod W {}
5306 pub mod RW {
5307 #[doc = "low(50MHz)"]
5308 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5309 #[doc = "medium(100MHz)"]
5310 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5311 #[doc = "fast(150MHz)"]
5312 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5313 #[doc = "max(200MHz)"]
5314 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5315 }
5316 }
5317 #[doc = "Open Drain Enable Field"]
5318 pub mod ODE {
5319 pub const offset: u32 = 11;
5320 pub const mask: u32 = 0x01 << offset;
5321 pub mod R {}
5322 pub mod W {}
5323 pub mod RW {
5324 #[doc = "Open Drain Disabled"]
5325 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5326 #[doc = "Open Drain Enabled"]
5327 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5328 }
5329 }
5330 #[doc = "Pull / Keep Enable Field"]
5331 pub mod PKE {
5332 pub const offset: u32 = 12;
5333 pub const mask: u32 = 0x01 << offset;
5334 pub mod R {}
5335 pub mod W {}
5336 pub mod RW {
5337 #[doc = "Pull/Keeper Disabled"]
5338 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5339 #[doc = "Pull/Keeper Enabled"]
5340 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5341 }
5342 }
5343 #[doc = "Pull / Keep Select Field"]
5344 pub mod PUE {
5345 pub const offset: u32 = 13;
5346 pub const mask: u32 = 0x01 << offset;
5347 pub mod R {}
5348 pub mod W {}
5349 pub mod RW {
5350 #[doc = "Keeper"]
5351 pub const PUE_0_KEEPER: u32 = 0;
5352 #[doc = "Pull"]
5353 pub const PUE_1_PULL: u32 = 0x01;
5354 }
5355 }
5356 #[doc = "Pull Up / Down Config. Field"]
5357 pub mod PUS {
5358 pub const offset: u32 = 14;
5359 pub const mask: u32 = 0x03 << offset;
5360 pub mod R {}
5361 pub mod W {}
5362 pub mod RW {
5363 #[doc = "100K Ohm Pull Down"]
5364 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
5365 #[doc = "47K Ohm Pull Up"]
5366 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
5367 #[doc = "100K Ohm Pull Up"]
5368 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
5369 #[doc = "22K Ohm Pull Up"]
5370 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
5371 }
5372 }
5373 #[doc = "Hyst. Enable Field"]
5374 pub mod HYS {
5375 pub const offset: u32 = 16;
5376 pub const mask: u32 = 0x01 << offset;
5377 pub mod R {}
5378 pub mod W {}
5379 pub mod RW {
5380 #[doc = "Hysteresis Disabled"]
5381 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5382 #[doc = "Hysteresis Enabled"]
5383 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5384 }
5385 }
5386}
5387#[doc = "SW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register"]
5388pub mod SW_PAD_CTL_PAD_GPIO_SD_02 {
5389 #[doc = "Slew Rate Field"]
5390 pub mod SRE {
5391 pub const offset: u32 = 0;
5392 pub const mask: u32 = 0x01 << offset;
5393 pub mod R {}
5394 pub mod W {}
5395 pub mod RW {
5396 #[doc = "Slow Slew Rate"]
5397 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5398 #[doc = "Fast Slew Rate"]
5399 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5400 }
5401 }
5402 #[doc = "Drive Strength Field"]
5403 pub mod DSE {
5404 pub const offset: u32 = 3;
5405 pub const mask: u32 = 0x07 << offset;
5406 pub mod R {}
5407 pub mod W {}
5408 pub mod RW {
5409 #[doc = "output driver disabled;"]
5410 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5411 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5412 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5413 #[doc = "R0/2"]
5414 pub const DSE_2_R0_2: u32 = 0x02;
5415 #[doc = "R0/3"]
5416 pub const DSE_3_R0_3: u32 = 0x03;
5417 #[doc = "R0/4"]
5418 pub const DSE_4_R0_4: u32 = 0x04;
5419 #[doc = "R0/5"]
5420 pub const DSE_5_R0_5: u32 = 0x05;
5421 #[doc = "R0/6"]
5422 pub const DSE_6_R0_6: u32 = 0x06;
5423 #[doc = "R0/7"]
5424 pub const DSE_7_R0_7: u32 = 0x07;
5425 }
5426 }
5427 #[doc = "Speed Field"]
5428 pub mod SPEED {
5429 pub const offset: u32 = 6;
5430 pub const mask: u32 = 0x03 << offset;
5431 pub mod R {}
5432 pub mod W {}
5433 pub mod RW {
5434 #[doc = "low(50MHz)"]
5435 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5436 #[doc = "medium(100MHz)"]
5437 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5438 #[doc = "fast(150MHz)"]
5439 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5440 #[doc = "max(200MHz)"]
5441 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5442 }
5443 }
5444 #[doc = "Open Drain Enable Field"]
5445 pub mod ODE {
5446 pub const offset: u32 = 11;
5447 pub const mask: u32 = 0x01 << offset;
5448 pub mod R {}
5449 pub mod W {}
5450 pub mod RW {
5451 #[doc = "Open Drain Disabled"]
5452 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5453 #[doc = "Open Drain Enabled"]
5454 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5455 }
5456 }
5457 #[doc = "Pull / Keep Enable Field"]
5458 pub mod PKE {
5459 pub const offset: u32 = 12;
5460 pub const mask: u32 = 0x01 << offset;
5461 pub mod R {}
5462 pub mod W {}
5463 pub mod RW {
5464 #[doc = "Pull/Keeper Disabled"]
5465 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5466 #[doc = "Pull/Keeper Enabled"]
5467 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5468 }
5469 }
5470 #[doc = "Pull / Keep Select Field"]
5471 pub mod PUE {
5472 pub const offset: u32 = 13;
5473 pub const mask: u32 = 0x01 << offset;
5474 pub mod R {}
5475 pub mod W {}
5476 pub mod RW {
5477 #[doc = "Keeper"]
5478 pub const PUE_0_KEEPER: u32 = 0;
5479 #[doc = "Pull"]
5480 pub const PUE_1_PULL: u32 = 0x01;
5481 }
5482 }
5483 #[doc = "Pull Up / Down Config. Field"]
5484 pub mod PUS {
5485 pub const offset: u32 = 14;
5486 pub const mask: u32 = 0x03 << offset;
5487 pub mod R {}
5488 pub mod W {}
5489 pub mod RW {
5490 #[doc = "100K Ohm Pull Down"]
5491 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
5492 #[doc = "47K Ohm Pull Up"]
5493 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
5494 #[doc = "100K Ohm Pull Up"]
5495 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
5496 #[doc = "22K Ohm Pull Up"]
5497 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
5498 }
5499 }
5500 #[doc = "Hyst. Enable Field"]
5501 pub mod HYS {
5502 pub const offset: u32 = 16;
5503 pub const mask: u32 = 0x01 << offset;
5504 pub mod R {}
5505 pub mod W {}
5506 pub mod RW {
5507 #[doc = "Hysteresis Disabled"]
5508 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5509 #[doc = "Hysteresis Enabled"]
5510 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5511 }
5512 }
5513}
5514#[doc = "SW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register"]
5515pub mod SW_PAD_CTL_PAD_GPIO_SD_01 {
5516 #[doc = "Slew Rate Field"]
5517 pub mod SRE {
5518 pub const offset: u32 = 0;
5519 pub const mask: u32 = 0x01 << offset;
5520 pub mod R {}
5521 pub mod W {}
5522 pub mod RW {
5523 #[doc = "Slow Slew Rate"]
5524 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5525 #[doc = "Fast Slew Rate"]
5526 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5527 }
5528 }
5529 #[doc = "Drive Strength Field"]
5530 pub mod DSE {
5531 pub const offset: u32 = 3;
5532 pub const mask: u32 = 0x07 << offset;
5533 pub mod R {}
5534 pub mod W {}
5535 pub mod RW {
5536 #[doc = "output driver disabled;"]
5537 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5538 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5539 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5540 #[doc = "R0/2"]
5541 pub const DSE_2_R0_2: u32 = 0x02;
5542 #[doc = "R0/3"]
5543 pub const DSE_3_R0_3: u32 = 0x03;
5544 #[doc = "R0/4"]
5545 pub const DSE_4_R0_4: u32 = 0x04;
5546 #[doc = "R0/5"]
5547 pub const DSE_5_R0_5: u32 = 0x05;
5548 #[doc = "R0/6"]
5549 pub const DSE_6_R0_6: u32 = 0x06;
5550 #[doc = "R0/7"]
5551 pub const DSE_7_R0_7: u32 = 0x07;
5552 }
5553 }
5554 #[doc = "Speed Field"]
5555 pub mod SPEED {
5556 pub const offset: u32 = 6;
5557 pub const mask: u32 = 0x03 << offset;
5558 pub mod R {}
5559 pub mod W {}
5560 pub mod RW {
5561 #[doc = "low(50MHz)"]
5562 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5563 #[doc = "medium(100MHz)"]
5564 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5565 #[doc = "fast(150MHz)"]
5566 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5567 #[doc = "max(200MHz)"]
5568 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5569 }
5570 }
5571 #[doc = "Open Drain Enable Field"]
5572 pub mod ODE {
5573 pub const offset: u32 = 11;
5574 pub const mask: u32 = 0x01 << offset;
5575 pub mod R {}
5576 pub mod W {}
5577 pub mod RW {
5578 #[doc = "Open Drain Disabled"]
5579 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5580 #[doc = "Open Drain Enabled"]
5581 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5582 }
5583 }
5584 #[doc = "Pull / Keep Enable Field"]
5585 pub mod PKE {
5586 pub const offset: u32 = 12;
5587 pub const mask: u32 = 0x01 << offset;
5588 pub mod R {}
5589 pub mod W {}
5590 pub mod RW {
5591 #[doc = "Pull/Keeper Disabled"]
5592 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5593 #[doc = "Pull/Keeper Enabled"]
5594 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5595 }
5596 }
5597 #[doc = "Pull / Keep Select Field"]
5598 pub mod PUE {
5599 pub const offset: u32 = 13;
5600 pub const mask: u32 = 0x01 << offset;
5601 pub mod R {}
5602 pub mod W {}
5603 pub mod RW {
5604 #[doc = "Keeper"]
5605 pub const PUE_0_KEEPER: u32 = 0;
5606 #[doc = "Pull"]
5607 pub const PUE_1_PULL: u32 = 0x01;
5608 }
5609 }
5610 #[doc = "Pull Up / Down Config. Field"]
5611 pub mod PUS {
5612 pub const offset: u32 = 14;
5613 pub const mask: u32 = 0x03 << offset;
5614 pub mod R {}
5615 pub mod W {}
5616 pub mod RW {
5617 #[doc = "100K Ohm Pull Down"]
5618 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
5619 #[doc = "47K Ohm Pull Up"]
5620 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
5621 #[doc = "100K Ohm Pull Up"]
5622 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
5623 #[doc = "22K Ohm Pull Up"]
5624 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
5625 }
5626 }
5627 #[doc = "Hyst. Enable Field"]
5628 pub mod HYS {
5629 pub const offset: u32 = 16;
5630 pub const mask: u32 = 0x01 << offset;
5631 pub mod R {}
5632 pub mod W {}
5633 pub mod RW {
5634 #[doc = "Hysteresis Disabled"]
5635 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5636 #[doc = "Hysteresis Enabled"]
5637 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5638 }
5639 }
5640}
5641#[doc = "SW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register"]
5642pub mod SW_PAD_CTL_PAD_GPIO_SD_00 {
5643 #[doc = "Slew Rate Field"]
5644 pub mod SRE {
5645 pub const offset: u32 = 0;
5646 pub const mask: u32 = 0x01 << offset;
5647 pub mod R {}
5648 pub mod W {}
5649 pub mod RW {
5650 #[doc = "Slow Slew Rate"]
5651 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5652 #[doc = "Fast Slew Rate"]
5653 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5654 }
5655 }
5656 #[doc = "Drive Strength Field"]
5657 pub mod DSE {
5658 pub const offset: u32 = 3;
5659 pub const mask: u32 = 0x07 << offset;
5660 pub mod R {}
5661 pub mod W {}
5662 pub mod RW {
5663 #[doc = "output driver disabled;"]
5664 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5665 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5666 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5667 #[doc = "R0/2"]
5668 pub const DSE_2_R0_2: u32 = 0x02;
5669 #[doc = "R0/3"]
5670 pub const DSE_3_R0_3: u32 = 0x03;
5671 #[doc = "R0/4"]
5672 pub const DSE_4_R0_4: u32 = 0x04;
5673 #[doc = "R0/5"]
5674 pub const DSE_5_R0_5: u32 = 0x05;
5675 #[doc = "R0/6"]
5676 pub const DSE_6_R0_6: u32 = 0x06;
5677 #[doc = "R0/7"]
5678 pub const DSE_7_R0_7: u32 = 0x07;
5679 }
5680 }
5681 #[doc = "Speed Field"]
5682 pub mod SPEED {
5683 pub const offset: u32 = 6;
5684 pub const mask: u32 = 0x03 << offset;
5685 pub mod R {}
5686 pub mod W {}
5687 pub mod RW {
5688 #[doc = "low(50MHz)"]
5689 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5690 #[doc = "medium(100MHz)"]
5691 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5692 #[doc = "fast(150MHz)"]
5693 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5694 #[doc = "max(200MHz)"]
5695 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5696 }
5697 }
5698 #[doc = "Open Drain Enable Field"]
5699 pub mod ODE {
5700 pub const offset: u32 = 11;
5701 pub const mask: u32 = 0x01 << offset;
5702 pub mod R {}
5703 pub mod W {}
5704 pub mod RW {
5705 #[doc = "Open Drain Disabled"]
5706 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5707 #[doc = "Open Drain Enabled"]
5708 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5709 }
5710 }
5711 #[doc = "Pull / Keep Enable Field"]
5712 pub mod PKE {
5713 pub const offset: u32 = 12;
5714 pub const mask: u32 = 0x01 << offset;
5715 pub mod R {}
5716 pub mod W {}
5717 pub mod RW {
5718 #[doc = "Pull/Keeper Disabled"]
5719 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5720 #[doc = "Pull/Keeper Enabled"]
5721 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5722 }
5723 }
5724 #[doc = "Pull / Keep Select Field"]
5725 pub mod PUE {
5726 pub const offset: u32 = 13;
5727 pub const mask: u32 = 0x01 << offset;
5728 pub mod R {}
5729 pub mod W {}
5730 pub mod RW {
5731 #[doc = "Keeper"]
5732 pub const PUE_0_KEEPER: u32 = 0;
5733 #[doc = "Pull"]
5734 pub const PUE_1_PULL: u32 = 0x01;
5735 }
5736 }
5737 #[doc = "Pull Up / Down Config. Field"]
5738 pub mod PUS {
5739 pub const offset: u32 = 14;
5740 pub const mask: u32 = 0x03 << offset;
5741 pub mod R {}
5742 pub mod W {}
5743 pub mod RW {
5744 #[doc = "100K Ohm Pull Down"]
5745 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
5746 #[doc = "47K Ohm Pull Up"]
5747 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
5748 #[doc = "100K Ohm Pull Up"]
5749 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
5750 #[doc = "22K Ohm Pull Up"]
5751 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
5752 }
5753 }
5754 #[doc = "Hyst. Enable Field"]
5755 pub mod HYS {
5756 pub const offset: u32 = 16;
5757 pub const mask: u32 = 0x01 << offset;
5758 pub mod R {}
5759 pub mod W {}
5760 pub mod RW {
5761 #[doc = "Hysteresis Disabled"]
5762 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5763 #[doc = "Hysteresis Enabled"]
5764 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5765 }
5766 }
5767}
5768#[doc = "SW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register"]
5769pub mod SW_PAD_CTL_PAD_GPIO_13 {
5770 #[doc = "Slew Rate Field"]
5771 pub mod SRE {
5772 pub const offset: u32 = 0;
5773 pub const mask: u32 = 0x01 << offset;
5774 pub mod R {}
5775 pub mod W {}
5776 pub mod RW {
5777 #[doc = "Slow Slew Rate"]
5778 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5779 #[doc = "Fast Slew Rate"]
5780 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5781 }
5782 }
5783 #[doc = "Drive Strength Field"]
5784 pub mod DSE {
5785 pub const offset: u32 = 3;
5786 pub const mask: u32 = 0x07 << offset;
5787 pub mod R {}
5788 pub mod W {}
5789 pub mod RW {
5790 #[doc = "output driver disabled;"]
5791 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5792 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5793 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5794 #[doc = "R0/2"]
5795 pub const DSE_2_R0_2: u32 = 0x02;
5796 #[doc = "R0/3"]
5797 pub const DSE_3_R0_3: u32 = 0x03;
5798 #[doc = "R0/4"]
5799 pub const DSE_4_R0_4: u32 = 0x04;
5800 #[doc = "R0/5"]
5801 pub const DSE_5_R0_5: u32 = 0x05;
5802 #[doc = "R0/6"]
5803 pub const DSE_6_R0_6: u32 = 0x06;
5804 #[doc = "R0/7"]
5805 pub const DSE_7_R0_7: u32 = 0x07;
5806 }
5807 }
5808 #[doc = "Speed Field"]
5809 pub mod SPEED {
5810 pub const offset: u32 = 6;
5811 pub const mask: u32 = 0x03 << offset;
5812 pub mod R {}
5813 pub mod W {}
5814 pub mod RW {
5815 #[doc = "low(50MHz)"]
5816 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5817 #[doc = "medium(100MHz)"]
5818 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5819 #[doc = "fast(150MHz)"]
5820 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5821 #[doc = "max(200MHz)"]
5822 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5823 }
5824 }
5825 #[doc = "Open Drain Enable Field"]
5826 pub mod ODE {
5827 pub const offset: u32 = 11;
5828 pub const mask: u32 = 0x01 << offset;
5829 pub mod R {}
5830 pub mod W {}
5831 pub mod RW {
5832 #[doc = "Open Drain Disabled"]
5833 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5834 #[doc = "Open Drain Enabled"]
5835 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5836 }
5837 }
5838 #[doc = "Pull / Keep Enable Field"]
5839 pub mod PKE {
5840 pub const offset: u32 = 12;
5841 pub const mask: u32 = 0x01 << offset;
5842 pub mod R {}
5843 pub mod W {}
5844 pub mod RW {
5845 #[doc = "Pull/Keeper Disabled"]
5846 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5847 #[doc = "Pull/Keeper Enabled"]
5848 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5849 }
5850 }
5851 #[doc = "Pull / Keep Select Field"]
5852 pub mod PUE {
5853 pub const offset: u32 = 13;
5854 pub const mask: u32 = 0x01 << offset;
5855 pub mod R {}
5856 pub mod W {}
5857 pub mod RW {
5858 #[doc = "Keeper"]
5859 pub const PUE_0_KEEPER: u32 = 0;
5860 #[doc = "Pull"]
5861 pub const PUE_1_PULL: u32 = 0x01;
5862 }
5863 }
5864 #[doc = "Pull Up / Down Config. Field"]
5865 pub mod PUS {
5866 pub const offset: u32 = 14;
5867 pub const mask: u32 = 0x03 << offset;
5868 pub mod R {}
5869 pub mod W {}
5870 pub mod RW {
5871 #[doc = "100K Ohm Pull Down"]
5872 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
5873 #[doc = "47K Ohm Pull Up"]
5874 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
5875 #[doc = "100K Ohm Pull Up"]
5876 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
5877 #[doc = "22K Ohm Pull Up"]
5878 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
5879 }
5880 }
5881 #[doc = "Hyst. Enable Field"]
5882 pub mod HYS {
5883 pub const offset: u32 = 16;
5884 pub const mask: u32 = 0x01 << offset;
5885 pub mod R {}
5886 pub mod W {}
5887 pub mod RW {
5888 #[doc = "Hysteresis Disabled"]
5889 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
5890 #[doc = "Hysteresis Enabled"]
5891 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
5892 }
5893 }
5894}
5895#[doc = "SW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register"]
5896pub mod SW_PAD_CTL_PAD_GPIO_12 {
5897 #[doc = "Slew Rate Field"]
5898 pub mod SRE {
5899 pub const offset: u32 = 0;
5900 pub const mask: u32 = 0x01 << offset;
5901 pub mod R {}
5902 pub mod W {}
5903 pub mod RW {
5904 #[doc = "Slow Slew Rate"]
5905 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
5906 #[doc = "Fast Slew Rate"]
5907 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
5908 }
5909 }
5910 #[doc = "Drive Strength Field"]
5911 pub mod DSE {
5912 pub const offset: u32 = 3;
5913 pub const mask: u32 = 0x07 << offset;
5914 pub mod R {}
5915 pub mod W {}
5916 pub mod RW {
5917 #[doc = "output driver disabled;"]
5918 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
5919 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
5920 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
5921 #[doc = "R0/2"]
5922 pub const DSE_2_R0_2: u32 = 0x02;
5923 #[doc = "R0/3"]
5924 pub const DSE_3_R0_3: u32 = 0x03;
5925 #[doc = "R0/4"]
5926 pub const DSE_4_R0_4: u32 = 0x04;
5927 #[doc = "R0/5"]
5928 pub const DSE_5_R0_5: u32 = 0x05;
5929 #[doc = "R0/6"]
5930 pub const DSE_6_R0_6: u32 = 0x06;
5931 #[doc = "R0/7"]
5932 pub const DSE_7_R0_7: u32 = 0x07;
5933 }
5934 }
5935 #[doc = "Speed Field"]
5936 pub mod SPEED {
5937 pub const offset: u32 = 6;
5938 pub const mask: u32 = 0x03 << offset;
5939 pub mod R {}
5940 pub mod W {}
5941 pub mod RW {
5942 #[doc = "low(50MHz)"]
5943 pub const SPEED_0_LOW_50MHZ: u32 = 0;
5944 #[doc = "medium(100MHz)"]
5945 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
5946 #[doc = "fast(150MHz)"]
5947 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
5948 #[doc = "max(200MHz)"]
5949 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
5950 }
5951 }
5952 #[doc = "Open Drain Enable Field"]
5953 pub mod ODE {
5954 pub const offset: u32 = 11;
5955 pub const mask: u32 = 0x01 << offset;
5956 pub mod R {}
5957 pub mod W {}
5958 pub mod RW {
5959 #[doc = "Open Drain Disabled"]
5960 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
5961 #[doc = "Open Drain Enabled"]
5962 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
5963 }
5964 }
5965 #[doc = "Pull / Keep Enable Field"]
5966 pub mod PKE {
5967 pub const offset: u32 = 12;
5968 pub const mask: u32 = 0x01 << offset;
5969 pub mod R {}
5970 pub mod W {}
5971 pub mod RW {
5972 #[doc = "Pull/Keeper Disabled"]
5973 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
5974 #[doc = "Pull/Keeper Enabled"]
5975 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
5976 }
5977 }
5978 #[doc = "Pull / Keep Select Field"]
5979 pub mod PUE {
5980 pub const offset: u32 = 13;
5981 pub const mask: u32 = 0x01 << offset;
5982 pub mod R {}
5983 pub mod W {}
5984 pub mod RW {
5985 #[doc = "Keeper"]
5986 pub const PUE_0_KEEPER: u32 = 0;
5987 #[doc = "Pull"]
5988 pub const PUE_1_PULL: u32 = 0x01;
5989 }
5990 }
5991 #[doc = "Pull Up / Down Config. Field"]
5992 pub mod PUS {
5993 pub const offset: u32 = 14;
5994 pub const mask: u32 = 0x03 << offset;
5995 pub mod R {}
5996 pub mod W {}
5997 pub mod RW {
5998 #[doc = "100K Ohm Pull Down"]
5999 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6000 #[doc = "47K Ohm Pull Up"]
6001 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6002 #[doc = "100K Ohm Pull Up"]
6003 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6004 #[doc = "22K Ohm Pull Up"]
6005 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6006 }
6007 }
6008 #[doc = "Hyst. Enable Field"]
6009 pub mod HYS {
6010 pub const offset: u32 = 16;
6011 pub const mask: u32 = 0x01 << offset;
6012 pub mod R {}
6013 pub mod W {}
6014 pub mod RW {
6015 #[doc = "Hysteresis Disabled"]
6016 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6017 #[doc = "Hysteresis Enabled"]
6018 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6019 }
6020 }
6021}
6022#[doc = "SW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register"]
6023pub mod SW_PAD_CTL_PAD_GPIO_11 {
6024 #[doc = "Slew Rate Field"]
6025 pub mod SRE {
6026 pub const offset: u32 = 0;
6027 pub const mask: u32 = 0x01 << offset;
6028 pub mod R {}
6029 pub mod W {}
6030 pub mod RW {
6031 #[doc = "Slow Slew Rate"]
6032 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6033 #[doc = "Fast Slew Rate"]
6034 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6035 }
6036 }
6037 #[doc = "Drive Strength Field"]
6038 pub mod DSE {
6039 pub const offset: u32 = 3;
6040 pub const mask: u32 = 0x07 << offset;
6041 pub mod R {}
6042 pub mod W {}
6043 pub mod RW {
6044 #[doc = "output driver disabled;"]
6045 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6046 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6047 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6048 #[doc = "R0/2"]
6049 pub const DSE_2_R0_2: u32 = 0x02;
6050 #[doc = "R0/3"]
6051 pub const DSE_3_R0_3: u32 = 0x03;
6052 #[doc = "R0/4"]
6053 pub const DSE_4_R0_4: u32 = 0x04;
6054 #[doc = "R0/5"]
6055 pub const DSE_5_R0_5: u32 = 0x05;
6056 #[doc = "R0/6"]
6057 pub const DSE_6_R0_6: u32 = 0x06;
6058 #[doc = "R0/7"]
6059 pub const DSE_7_R0_7: u32 = 0x07;
6060 }
6061 }
6062 #[doc = "Speed Field"]
6063 pub mod SPEED {
6064 pub const offset: u32 = 6;
6065 pub const mask: u32 = 0x03 << offset;
6066 pub mod R {}
6067 pub mod W {}
6068 pub mod RW {
6069 #[doc = "low(50MHz)"]
6070 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6071 #[doc = "medium(100MHz)"]
6072 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6073 #[doc = "fast(150MHz)"]
6074 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6075 #[doc = "max(200MHz)"]
6076 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6077 }
6078 }
6079 #[doc = "Open Drain Enable Field"]
6080 pub mod ODE {
6081 pub const offset: u32 = 11;
6082 pub const mask: u32 = 0x01 << offset;
6083 pub mod R {}
6084 pub mod W {}
6085 pub mod RW {
6086 #[doc = "Open Drain Disabled"]
6087 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6088 #[doc = "Open Drain Enabled"]
6089 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6090 }
6091 }
6092 #[doc = "Pull / Keep Enable Field"]
6093 pub mod PKE {
6094 pub const offset: u32 = 12;
6095 pub const mask: u32 = 0x01 << offset;
6096 pub mod R {}
6097 pub mod W {}
6098 pub mod RW {
6099 #[doc = "Pull/Keeper Disabled"]
6100 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6101 #[doc = "Pull/Keeper Enabled"]
6102 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6103 }
6104 }
6105 #[doc = "Pull / Keep Select Field"]
6106 pub mod PUE {
6107 pub const offset: u32 = 13;
6108 pub const mask: u32 = 0x01 << offset;
6109 pub mod R {}
6110 pub mod W {}
6111 pub mod RW {
6112 #[doc = "Keeper"]
6113 pub const PUE_0_KEEPER: u32 = 0;
6114 #[doc = "Pull"]
6115 pub const PUE_1_PULL: u32 = 0x01;
6116 }
6117 }
6118 #[doc = "Pull Up / Down Config. Field"]
6119 pub mod PUS {
6120 pub const offset: u32 = 14;
6121 pub const mask: u32 = 0x03 << offset;
6122 pub mod R {}
6123 pub mod W {}
6124 pub mod RW {
6125 #[doc = "100K Ohm Pull Down"]
6126 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6127 #[doc = "47K Ohm Pull Up"]
6128 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6129 #[doc = "100K Ohm Pull Up"]
6130 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6131 #[doc = "22K Ohm Pull Up"]
6132 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6133 }
6134 }
6135 #[doc = "Hyst. Enable Field"]
6136 pub mod HYS {
6137 pub const offset: u32 = 16;
6138 pub const mask: u32 = 0x01 << offset;
6139 pub mod R {}
6140 pub mod W {}
6141 pub mod RW {
6142 #[doc = "Hysteresis Disabled"]
6143 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6144 #[doc = "Hysteresis Enabled"]
6145 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6146 }
6147 }
6148}
6149#[doc = "SW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register"]
6150pub mod SW_PAD_CTL_PAD_GPIO_10 {
6151 #[doc = "Slew Rate Field"]
6152 pub mod SRE {
6153 pub const offset: u32 = 0;
6154 pub const mask: u32 = 0x01 << offset;
6155 pub mod R {}
6156 pub mod W {}
6157 pub mod RW {
6158 #[doc = "Slow Slew Rate"]
6159 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6160 #[doc = "Fast Slew Rate"]
6161 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6162 }
6163 }
6164 #[doc = "Drive Strength Field"]
6165 pub mod DSE {
6166 pub const offset: u32 = 3;
6167 pub const mask: u32 = 0x07 << offset;
6168 pub mod R {}
6169 pub mod W {}
6170 pub mod RW {
6171 #[doc = "output driver disabled;"]
6172 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6173 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6174 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6175 #[doc = "R0/2"]
6176 pub const DSE_2_R0_2: u32 = 0x02;
6177 #[doc = "R0/3"]
6178 pub const DSE_3_R0_3: u32 = 0x03;
6179 #[doc = "R0/4"]
6180 pub const DSE_4_R0_4: u32 = 0x04;
6181 #[doc = "R0/5"]
6182 pub const DSE_5_R0_5: u32 = 0x05;
6183 #[doc = "R0/6"]
6184 pub const DSE_6_R0_6: u32 = 0x06;
6185 #[doc = "R0/7"]
6186 pub const DSE_7_R0_7: u32 = 0x07;
6187 }
6188 }
6189 #[doc = "Speed Field"]
6190 pub mod SPEED {
6191 pub const offset: u32 = 6;
6192 pub const mask: u32 = 0x03 << offset;
6193 pub mod R {}
6194 pub mod W {}
6195 pub mod RW {
6196 #[doc = "low(50MHz)"]
6197 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6198 #[doc = "medium(100MHz)"]
6199 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6200 #[doc = "fast(150MHz)"]
6201 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6202 #[doc = "max(200MHz)"]
6203 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6204 }
6205 }
6206 #[doc = "Open Drain Enable Field"]
6207 pub mod ODE {
6208 pub const offset: u32 = 11;
6209 pub const mask: u32 = 0x01 << offset;
6210 pub mod R {}
6211 pub mod W {}
6212 pub mod RW {
6213 #[doc = "Open Drain Disabled"]
6214 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6215 #[doc = "Open Drain Enabled"]
6216 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6217 }
6218 }
6219 #[doc = "Pull / Keep Enable Field"]
6220 pub mod PKE {
6221 pub const offset: u32 = 12;
6222 pub const mask: u32 = 0x01 << offset;
6223 pub mod R {}
6224 pub mod W {}
6225 pub mod RW {
6226 #[doc = "Pull/Keeper Disabled"]
6227 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6228 #[doc = "Pull/Keeper Enabled"]
6229 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6230 }
6231 }
6232 #[doc = "Pull / Keep Select Field"]
6233 pub mod PUE {
6234 pub const offset: u32 = 13;
6235 pub const mask: u32 = 0x01 << offset;
6236 pub mod R {}
6237 pub mod W {}
6238 pub mod RW {
6239 #[doc = "Keeper"]
6240 pub const PUE_0_KEEPER: u32 = 0;
6241 #[doc = "Pull"]
6242 pub const PUE_1_PULL: u32 = 0x01;
6243 }
6244 }
6245 #[doc = "Pull Up / Down Config. Field"]
6246 pub mod PUS {
6247 pub const offset: u32 = 14;
6248 pub const mask: u32 = 0x03 << offset;
6249 pub mod R {}
6250 pub mod W {}
6251 pub mod RW {
6252 #[doc = "100K Ohm Pull Down"]
6253 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6254 #[doc = "47K Ohm Pull Up"]
6255 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6256 #[doc = "100K Ohm Pull Up"]
6257 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6258 #[doc = "22K Ohm Pull Up"]
6259 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6260 }
6261 }
6262 #[doc = "Hyst. Enable Field"]
6263 pub mod HYS {
6264 pub const offset: u32 = 16;
6265 pub const mask: u32 = 0x01 << offset;
6266 pub mod R {}
6267 pub mod W {}
6268 pub mod RW {
6269 #[doc = "Hysteresis Disabled"]
6270 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6271 #[doc = "Hysteresis Enabled"]
6272 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6273 }
6274 }
6275}
6276#[doc = "SW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register"]
6277pub mod SW_PAD_CTL_PAD_GPIO_09 {
6278 #[doc = "Slew Rate Field"]
6279 pub mod SRE {
6280 pub const offset: u32 = 0;
6281 pub const mask: u32 = 0x01 << offset;
6282 pub mod R {}
6283 pub mod W {}
6284 pub mod RW {
6285 #[doc = "Slow Slew Rate"]
6286 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6287 #[doc = "Fast Slew Rate"]
6288 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6289 }
6290 }
6291 #[doc = "Drive Strength Field"]
6292 pub mod DSE {
6293 pub const offset: u32 = 3;
6294 pub const mask: u32 = 0x07 << offset;
6295 pub mod R {}
6296 pub mod W {}
6297 pub mod RW {
6298 #[doc = "output driver disabled;"]
6299 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6300 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6301 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6302 #[doc = "R0/2"]
6303 pub const DSE_2_R0_2: u32 = 0x02;
6304 #[doc = "R0/3"]
6305 pub const DSE_3_R0_3: u32 = 0x03;
6306 #[doc = "R0/4"]
6307 pub const DSE_4_R0_4: u32 = 0x04;
6308 #[doc = "R0/5"]
6309 pub const DSE_5_R0_5: u32 = 0x05;
6310 #[doc = "R0/6"]
6311 pub const DSE_6_R0_6: u32 = 0x06;
6312 #[doc = "R0/7"]
6313 pub const DSE_7_R0_7: u32 = 0x07;
6314 }
6315 }
6316 #[doc = "Speed Field"]
6317 pub mod SPEED {
6318 pub const offset: u32 = 6;
6319 pub const mask: u32 = 0x03 << offset;
6320 pub mod R {}
6321 pub mod W {}
6322 pub mod RW {
6323 #[doc = "low(50MHz)"]
6324 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6325 #[doc = "medium(100MHz)"]
6326 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6327 #[doc = "fast(150MHz)"]
6328 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6329 #[doc = "max(200MHz)"]
6330 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6331 }
6332 }
6333 #[doc = "Open Drain Enable Field"]
6334 pub mod ODE {
6335 pub const offset: u32 = 11;
6336 pub const mask: u32 = 0x01 << offset;
6337 pub mod R {}
6338 pub mod W {}
6339 pub mod RW {
6340 #[doc = "Open Drain Disabled"]
6341 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6342 #[doc = "Open Drain Enabled"]
6343 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6344 }
6345 }
6346 #[doc = "Pull / Keep Enable Field"]
6347 pub mod PKE {
6348 pub const offset: u32 = 12;
6349 pub const mask: u32 = 0x01 << offset;
6350 pub mod R {}
6351 pub mod W {}
6352 pub mod RW {
6353 #[doc = "Pull/Keeper Disabled"]
6354 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6355 #[doc = "Pull/Keeper Enabled"]
6356 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6357 }
6358 }
6359 #[doc = "Pull / Keep Select Field"]
6360 pub mod PUE {
6361 pub const offset: u32 = 13;
6362 pub const mask: u32 = 0x01 << offset;
6363 pub mod R {}
6364 pub mod W {}
6365 pub mod RW {
6366 #[doc = "Keeper"]
6367 pub const PUE_0_KEEPER: u32 = 0;
6368 #[doc = "Pull"]
6369 pub const PUE_1_PULL: u32 = 0x01;
6370 }
6371 }
6372 #[doc = "Pull Up / Down Config. Field"]
6373 pub mod PUS {
6374 pub const offset: u32 = 14;
6375 pub const mask: u32 = 0x03 << offset;
6376 pub mod R {}
6377 pub mod W {}
6378 pub mod RW {
6379 #[doc = "100K Ohm Pull Down"]
6380 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6381 #[doc = "47K Ohm Pull Up"]
6382 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6383 #[doc = "100K Ohm Pull Up"]
6384 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6385 #[doc = "22K Ohm Pull Up"]
6386 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6387 }
6388 }
6389 #[doc = "Hyst. Enable Field"]
6390 pub mod HYS {
6391 pub const offset: u32 = 16;
6392 pub const mask: u32 = 0x01 << offset;
6393 pub mod R {}
6394 pub mod W {}
6395 pub mod RW {
6396 #[doc = "Hysteresis Disabled"]
6397 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6398 #[doc = "Hysteresis Enabled"]
6399 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6400 }
6401 }
6402}
6403#[doc = "SW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register"]
6404pub mod SW_PAD_CTL_PAD_GPIO_08 {
6405 #[doc = "Slew Rate Field"]
6406 pub mod SRE {
6407 pub const offset: u32 = 0;
6408 pub const mask: u32 = 0x01 << offset;
6409 pub mod R {}
6410 pub mod W {}
6411 pub mod RW {
6412 #[doc = "Slow Slew Rate"]
6413 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6414 #[doc = "Fast Slew Rate"]
6415 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6416 }
6417 }
6418 #[doc = "Drive Strength Field"]
6419 pub mod DSE {
6420 pub const offset: u32 = 3;
6421 pub const mask: u32 = 0x07 << offset;
6422 pub mod R {}
6423 pub mod W {}
6424 pub mod RW {
6425 #[doc = "output driver disabled;"]
6426 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6427 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6428 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6429 #[doc = "R0/2"]
6430 pub const DSE_2_R0_2: u32 = 0x02;
6431 #[doc = "R0/3"]
6432 pub const DSE_3_R0_3: u32 = 0x03;
6433 #[doc = "R0/4"]
6434 pub const DSE_4_R0_4: u32 = 0x04;
6435 #[doc = "R0/5"]
6436 pub const DSE_5_R0_5: u32 = 0x05;
6437 #[doc = "R0/6"]
6438 pub const DSE_6_R0_6: u32 = 0x06;
6439 #[doc = "R0/7"]
6440 pub const DSE_7_R0_7: u32 = 0x07;
6441 }
6442 }
6443 #[doc = "Speed Field"]
6444 pub mod SPEED {
6445 pub const offset: u32 = 6;
6446 pub const mask: u32 = 0x03 << offset;
6447 pub mod R {}
6448 pub mod W {}
6449 pub mod RW {
6450 #[doc = "low(50MHz)"]
6451 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6452 #[doc = "medium(100MHz)"]
6453 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6454 #[doc = "fast(150MHz)"]
6455 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6456 #[doc = "max(200MHz)"]
6457 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6458 }
6459 }
6460 #[doc = "Open Drain Enable Field"]
6461 pub mod ODE {
6462 pub const offset: u32 = 11;
6463 pub const mask: u32 = 0x01 << offset;
6464 pub mod R {}
6465 pub mod W {}
6466 pub mod RW {
6467 #[doc = "Open Drain Disabled"]
6468 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6469 #[doc = "Open Drain Enabled"]
6470 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6471 }
6472 }
6473 #[doc = "Pull / Keep Enable Field"]
6474 pub mod PKE {
6475 pub const offset: u32 = 12;
6476 pub const mask: u32 = 0x01 << offset;
6477 pub mod R {}
6478 pub mod W {}
6479 pub mod RW {
6480 #[doc = "Pull/Keeper Disabled"]
6481 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6482 #[doc = "Pull/Keeper Enabled"]
6483 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6484 }
6485 }
6486 #[doc = "Pull / Keep Select Field"]
6487 pub mod PUE {
6488 pub const offset: u32 = 13;
6489 pub const mask: u32 = 0x01 << offset;
6490 pub mod R {}
6491 pub mod W {}
6492 pub mod RW {
6493 #[doc = "Keeper"]
6494 pub const PUE_0_KEEPER: u32 = 0;
6495 #[doc = "Pull"]
6496 pub const PUE_1_PULL: u32 = 0x01;
6497 }
6498 }
6499 #[doc = "Pull Up / Down Config. Field"]
6500 pub mod PUS {
6501 pub const offset: u32 = 14;
6502 pub const mask: u32 = 0x03 << offset;
6503 pub mod R {}
6504 pub mod W {}
6505 pub mod RW {
6506 #[doc = "100K Ohm Pull Down"]
6507 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6508 #[doc = "47K Ohm Pull Up"]
6509 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6510 #[doc = "100K Ohm Pull Up"]
6511 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6512 #[doc = "22K Ohm Pull Up"]
6513 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6514 }
6515 }
6516 #[doc = "Hyst. Enable Field"]
6517 pub mod HYS {
6518 pub const offset: u32 = 16;
6519 pub const mask: u32 = 0x01 << offset;
6520 pub mod R {}
6521 pub mod W {}
6522 pub mod RW {
6523 #[doc = "Hysteresis Disabled"]
6524 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6525 #[doc = "Hysteresis Enabled"]
6526 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6527 }
6528 }
6529}
6530#[doc = "SW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register"]
6531pub mod SW_PAD_CTL_PAD_GPIO_07 {
6532 #[doc = "Slew Rate Field"]
6533 pub mod SRE {
6534 pub const offset: u32 = 0;
6535 pub const mask: u32 = 0x01 << offset;
6536 pub mod R {}
6537 pub mod W {}
6538 pub mod RW {
6539 #[doc = "Slow Slew Rate"]
6540 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6541 #[doc = "Fast Slew Rate"]
6542 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6543 }
6544 }
6545 #[doc = "Drive Strength Field"]
6546 pub mod DSE {
6547 pub const offset: u32 = 3;
6548 pub const mask: u32 = 0x07 << offset;
6549 pub mod R {}
6550 pub mod W {}
6551 pub mod RW {
6552 #[doc = "output driver disabled;"]
6553 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6554 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6555 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6556 #[doc = "R0/2"]
6557 pub const DSE_2_R0_2: u32 = 0x02;
6558 #[doc = "R0/3"]
6559 pub const DSE_3_R0_3: u32 = 0x03;
6560 #[doc = "R0/4"]
6561 pub const DSE_4_R0_4: u32 = 0x04;
6562 #[doc = "R0/5"]
6563 pub const DSE_5_R0_5: u32 = 0x05;
6564 #[doc = "R0/6"]
6565 pub const DSE_6_R0_6: u32 = 0x06;
6566 #[doc = "R0/7"]
6567 pub const DSE_7_R0_7: u32 = 0x07;
6568 }
6569 }
6570 #[doc = "Speed Field"]
6571 pub mod SPEED {
6572 pub const offset: u32 = 6;
6573 pub const mask: u32 = 0x03 << offset;
6574 pub mod R {}
6575 pub mod W {}
6576 pub mod RW {
6577 #[doc = "low(50MHz)"]
6578 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6579 #[doc = "medium(100MHz)"]
6580 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6581 #[doc = "fast(150MHz)"]
6582 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6583 #[doc = "max(200MHz)"]
6584 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6585 }
6586 }
6587 #[doc = "Open Drain Enable Field"]
6588 pub mod ODE {
6589 pub const offset: u32 = 11;
6590 pub const mask: u32 = 0x01 << offset;
6591 pub mod R {}
6592 pub mod W {}
6593 pub mod RW {
6594 #[doc = "Open Drain Disabled"]
6595 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6596 #[doc = "Open Drain Enabled"]
6597 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6598 }
6599 }
6600 #[doc = "Pull / Keep Enable Field"]
6601 pub mod PKE {
6602 pub const offset: u32 = 12;
6603 pub const mask: u32 = 0x01 << offset;
6604 pub mod R {}
6605 pub mod W {}
6606 pub mod RW {
6607 #[doc = "Pull/Keeper Disabled"]
6608 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6609 #[doc = "Pull/Keeper Enabled"]
6610 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6611 }
6612 }
6613 #[doc = "Pull / Keep Select Field"]
6614 pub mod PUE {
6615 pub const offset: u32 = 13;
6616 pub const mask: u32 = 0x01 << offset;
6617 pub mod R {}
6618 pub mod W {}
6619 pub mod RW {
6620 #[doc = "Keeper"]
6621 pub const PUE_0_KEEPER: u32 = 0;
6622 #[doc = "Pull"]
6623 pub const PUE_1_PULL: u32 = 0x01;
6624 }
6625 }
6626 #[doc = "Pull Up / Down Config. Field"]
6627 pub mod PUS {
6628 pub const offset: u32 = 14;
6629 pub const mask: u32 = 0x03 << offset;
6630 pub mod R {}
6631 pub mod W {}
6632 pub mod RW {
6633 #[doc = "100K Ohm Pull Down"]
6634 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6635 #[doc = "47K Ohm Pull Up"]
6636 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6637 #[doc = "100K Ohm Pull Up"]
6638 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6639 #[doc = "22K Ohm Pull Up"]
6640 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6641 }
6642 }
6643 #[doc = "Hyst. Enable Field"]
6644 pub mod HYS {
6645 pub const offset: u32 = 16;
6646 pub const mask: u32 = 0x01 << offset;
6647 pub mod R {}
6648 pub mod W {}
6649 pub mod RW {
6650 #[doc = "Hysteresis Disabled"]
6651 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6652 #[doc = "Hysteresis Enabled"]
6653 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6654 }
6655 }
6656}
6657#[doc = "SW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register"]
6658pub mod SW_PAD_CTL_PAD_GPIO_06 {
6659 #[doc = "Slew Rate Field"]
6660 pub mod SRE {
6661 pub const offset: u32 = 0;
6662 pub const mask: u32 = 0x01 << offset;
6663 pub mod R {}
6664 pub mod W {}
6665 pub mod RW {
6666 #[doc = "Slow Slew Rate"]
6667 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6668 #[doc = "Fast Slew Rate"]
6669 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6670 }
6671 }
6672 #[doc = "Drive Strength Field"]
6673 pub mod DSE {
6674 pub const offset: u32 = 3;
6675 pub const mask: u32 = 0x07 << offset;
6676 pub mod R {}
6677 pub mod W {}
6678 pub mod RW {
6679 #[doc = "output driver disabled;"]
6680 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6681 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6682 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6683 #[doc = "R0/2"]
6684 pub const DSE_2_R0_2: u32 = 0x02;
6685 #[doc = "R0/3"]
6686 pub const DSE_3_R0_3: u32 = 0x03;
6687 #[doc = "R0/4"]
6688 pub const DSE_4_R0_4: u32 = 0x04;
6689 #[doc = "R0/5"]
6690 pub const DSE_5_R0_5: u32 = 0x05;
6691 #[doc = "R0/6"]
6692 pub const DSE_6_R0_6: u32 = 0x06;
6693 #[doc = "R0/7"]
6694 pub const DSE_7_R0_7: u32 = 0x07;
6695 }
6696 }
6697 #[doc = "Speed Field"]
6698 pub mod SPEED {
6699 pub const offset: u32 = 6;
6700 pub const mask: u32 = 0x03 << offset;
6701 pub mod R {}
6702 pub mod W {}
6703 pub mod RW {
6704 #[doc = "low(50MHz)"]
6705 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6706 #[doc = "medium(100MHz)"]
6707 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6708 #[doc = "fast(150MHz)"]
6709 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6710 #[doc = "max(200MHz)"]
6711 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6712 }
6713 }
6714 #[doc = "Open Drain Enable Field"]
6715 pub mod ODE {
6716 pub const offset: u32 = 11;
6717 pub const mask: u32 = 0x01 << offset;
6718 pub mod R {}
6719 pub mod W {}
6720 pub mod RW {
6721 #[doc = "Open Drain Disabled"]
6722 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6723 #[doc = "Open Drain Enabled"]
6724 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6725 }
6726 }
6727 #[doc = "Pull / Keep Enable Field"]
6728 pub mod PKE {
6729 pub const offset: u32 = 12;
6730 pub const mask: u32 = 0x01 << offset;
6731 pub mod R {}
6732 pub mod W {}
6733 pub mod RW {
6734 #[doc = "Pull/Keeper Disabled"]
6735 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6736 #[doc = "Pull/Keeper Enabled"]
6737 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6738 }
6739 }
6740 #[doc = "Pull / Keep Select Field"]
6741 pub mod PUE {
6742 pub const offset: u32 = 13;
6743 pub const mask: u32 = 0x01 << offset;
6744 pub mod R {}
6745 pub mod W {}
6746 pub mod RW {
6747 #[doc = "Keeper"]
6748 pub const PUE_0_KEEPER: u32 = 0;
6749 #[doc = "Pull"]
6750 pub const PUE_1_PULL: u32 = 0x01;
6751 }
6752 }
6753 #[doc = "Pull Up / Down Config. Field"]
6754 pub mod PUS {
6755 pub const offset: u32 = 14;
6756 pub const mask: u32 = 0x03 << offset;
6757 pub mod R {}
6758 pub mod W {}
6759 pub mod RW {
6760 #[doc = "100K Ohm Pull Down"]
6761 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6762 #[doc = "47K Ohm Pull Up"]
6763 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6764 #[doc = "100K Ohm Pull Up"]
6765 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6766 #[doc = "22K Ohm Pull Up"]
6767 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6768 }
6769 }
6770 #[doc = "Hyst. Enable Field"]
6771 pub mod HYS {
6772 pub const offset: u32 = 16;
6773 pub const mask: u32 = 0x01 << offset;
6774 pub mod R {}
6775 pub mod W {}
6776 pub mod RW {
6777 #[doc = "Hysteresis Disabled"]
6778 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6779 #[doc = "Hysteresis Enabled"]
6780 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6781 }
6782 }
6783}
6784#[doc = "SW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register"]
6785pub mod SW_PAD_CTL_PAD_GPIO_05 {
6786 #[doc = "Slew Rate Field"]
6787 pub mod SRE {
6788 pub const offset: u32 = 0;
6789 pub const mask: u32 = 0x01 << offset;
6790 pub mod R {}
6791 pub mod W {}
6792 pub mod RW {
6793 #[doc = "Slow Slew Rate"]
6794 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6795 #[doc = "Fast Slew Rate"]
6796 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6797 }
6798 }
6799 #[doc = "Drive Strength Field"]
6800 pub mod DSE {
6801 pub const offset: u32 = 3;
6802 pub const mask: u32 = 0x07 << offset;
6803 pub mod R {}
6804 pub mod W {}
6805 pub mod RW {
6806 #[doc = "output driver disabled;"]
6807 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6808 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6809 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6810 #[doc = "R0/2"]
6811 pub const DSE_2_R0_2: u32 = 0x02;
6812 #[doc = "R0/3"]
6813 pub const DSE_3_R0_3: u32 = 0x03;
6814 #[doc = "R0/4"]
6815 pub const DSE_4_R0_4: u32 = 0x04;
6816 #[doc = "R0/5"]
6817 pub const DSE_5_R0_5: u32 = 0x05;
6818 #[doc = "R0/6"]
6819 pub const DSE_6_R0_6: u32 = 0x06;
6820 #[doc = "R0/7"]
6821 pub const DSE_7_R0_7: u32 = 0x07;
6822 }
6823 }
6824 #[doc = "Speed Field"]
6825 pub mod SPEED {
6826 pub const offset: u32 = 6;
6827 pub const mask: u32 = 0x03 << offset;
6828 pub mod R {}
6829 pub mod W {}
6830 pub mod RW {
6831 #[doc = "low(50MHz)"]
6832 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6833 #[doc = "medium(100MHz)"]
6834 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6835 #[doc = "fast(150MHz)"]
6836 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6837 #[doc = "max(200MHz)"]
6838 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6839 }
6840 }
6841 #[doc = "Open Drain Enable Field"]
6842 pub mod ODE {
6843 pub const offset: u32 = 11;
6844 pub const mask: u32 = 0x01 << offset;
6845 pub mod R {}
6846 pub mod W {}
6847 pub mod RW {
6848 #[doc = "Open Drain Disabled"]
6849 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6850 #[doc = "Open Drain Enabled"]
6851 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6852 }
6853 }
6854 #[doc = "Pull / Keep Enable Field"]
6855 pub mod PKE {
6856 pub const offset: u32 = 12;
6857 pub const mask: u32 = 0x01 << offset;
6858 pub mod R {}
6859 pub mod W {}
6860 pub mod RW {
6861 #[doc = "Pull/Keeper Disabled"]
6862 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6863 #[doc = "Pull/Keeper Enabled"]
6864 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6865 }
6866 }
6867 #[doc = "Pull / Keep Select Field"]
6868 pub mod PUE {
6869 pub const offset: u32 = 13;
6870 pub const mask: u32 = 0x01 << offset;
6871 pub mod R {}
6872 pub mod W {}
6873 pub mod RW {
6874 #[doc = "Keeper"]
6875 pub const PUE_0_KEEPER: u32 = 0;
6876 #[doc = "Pull"]
6877 pub const PUE_1_PULL: u32 = 0x01;
6878 }
6879 }
6880 #[doc = "Pull Up / Down Config. Field"]
6881 pub mod PUS {
6882 pub const offset: u32 = 14;
6883 pub const mask: u32 = 0x03 << offset;
6884 pub mod R {}
6885 pub mod W {}
6886 pub mod RW {
6887 #[doc = "100K Ohm Pull Down"]
6888 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6889 #[doc = "47K Ohm Pull Up"]
6890 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6891 #[doc = "100K Ohm Pull Up"]
6892 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6893 #[doc = "22K Ohm Pull Up"]
6894 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6895 }
6896 }
6897 #[doc = "Hyst. Enable Field"]
6898 pub mod HYS {
6899 pub const offset: u32 = 16;
6900 pub const mask: u32 = 0x01 << offset;
6901 pub mod R {}
6902 pub mod W {}
6903 pub mod RW {
6904 #[doc = "Hysteresis Disabled"]
6905 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6906 #[doc = "Hysteresis Enabled"]
6907 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6908 }
6909 }
6910}
6911#[doc = "SW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register"]
6912pub mod SW_PAD_CTL_PAD_GPIO_04 {
6913 #[doc = "Slew Rate Field"]
6914 pub mod SRE {
6915 pub const offset: u32 = 0;
6916 pub const mask: u32 = 0x01 << offset;
6917 pub mod R {}
6918 pub mod W {}
6919 pub mod RW {
6920 #[doc = "Slow Slew Rate"]
6921 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6922 #[doc = "Fast Slew Rate"]
6923 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6924 }
6925 }
6926 #[doc = "Drive Strength Field"]
6927 pub mod DSE {
6928 pub const offset: u32 = 3;
6929 pub const mask: u32 = 0x07 << offset;
6930 pub mod R {}
6931 pub mod W {}
6932 pub mod RW {
6933 #[doc = "output driver disabled;"]
6934 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
6935 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
6936 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
6937 #[doc = "R0/2"]
6938 pub const DSE_2_R0_2: u32 = 0x02;
6939 #[doc = "R0/3"]
6940 pub const DSE_3_R0_3: u32 = 0x03;
6941 #[doc = "R0/4"]
6942 pub const DSE_4_R0_4: u32 = 0x04;
6943 #[doc = "R0/5"]
6944 pub const DSE_5_R0_5: u32 = 0x05;
6945 #[doc = "R0/6"]
6946 pub const DSE_6_R0_6: u32 = 0x06;
6947 #[doc = "R0/7"]
6948 pub const DSE_7_R0_7: u32 = 0x07;
6949 }
6950 }
6951 #[doc = "Speed Field"]
6952 pub mod SPEED {
6953 pub const offset: u32 = 6;
6954 pub const mask: u32 = 0x03 << offset;
6955 pub mod R {}
6956 pub mod W {}
6957 pub mod RW {
6958 #[doc = "low(50MHz)"]
6959 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6960 #[doc = "medium(100MHz)"]
6961 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6962 #[doc = "fast(150MHz)"]
6963 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
6964 #[doc = "max(200MHz)"]
6965 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6966 }
6967 }
6968 #[doc = "Open Drain Enable Field"]
6969 pub mod ODE {
6970 pub const offset: u32 = 11;
6971 pub const mask: u32 = 0x01 << offset;
6972 pub mod R {}
6973 pub mod W {}
6974 pub mod RW {
6975 #[doc = "Open Drain Disabled"]
6976 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6977 #[doc = "Open Drain Enabled"]
6978 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6979 }
6980 }
6981 #[doc = "Pull / Keep Enable Field"]
6982 pub mod PKE {
6983 pub const offset: u32 = 12;
6984 pub const mask: u32 = 0x01 << offset;
6985 pub mod R {}
6986 pub mod W {}
6987 pub mod RW {
6988 #[doc = "Pull/Keeper Disabled"]
6989 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6990 #[doc = "Pull/Keeper Enabled"]
6991 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6992 }
6993 }
6994 #[doc = "Pull / Keep Select Field"]
6995 pub mod PUE {
6996 pub const offset: u32 = 13;
6997 pub const mask: u32 = 0x01 << offset;
6998 pub mod R {}
6999 pub mod W {}
7000 pub mod RW {
7001 #[doc = "Keeper"]
7002 pub const PUE_0_KEEPER: u32 = 0;
7003 #[doc = "Pull"]
7004 pub const PUE_1_PULL: u32 = 0x01;
7005 }
7006 }
7007 #[doc = "Pull Up / Down Config. Field"]
7008 pub mod PUS {
7009 pub const offset: u32 = 14;
7010 pub const mask: u32 = 0x03 << offset;
7011 pub mod R {}
7012 pub mod W {}
7013 pub mod RW {
7014 #[doc = "100K Ohm Pull Down"]
7015 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7016 #[doc = "47K Ohm Pull Up"]
7017 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7018 #[doc = "100K Ohm Pull Up"]
7019 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7020 #[doc = "22K Ohm Pull Up"]
7021 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7022 }
7023 }
7024 #[doc = "Hyst. Enable Field"]
7025 pub mod HYS {
7026 pub const offset: u32 = 16;
7027 pub const mask: u32 = 0x01 << offset;
7028 pub mod R {}
7029 pub mod W {}
7030 pub mod RW {
7031 #[doc = "Hysteresis Disabled"]
7032 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7033 #[doc = "Hysteresis Enabled"]
7034 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7035 }
7036 }
7037}
7038#[doc = "SW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register"]
7039pub mod SW_PAD_CTL_PAD_GPIO_03 {
7040 #[doc = "Slew Rate Field"]
7041 pub mod SRE {
7042 pub const offset: u32 = 0;
7043 pub const mask: u32 = 0x01 << offset;
7044 pub mod R {}
7045 pub mod W {}
7046 pub mod RW {
7047 #[doc = "Slow Slew Rate"]
7048 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7049 #[doc = "Fast Slew Rate"]
7050 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7051 }
7052 }
7053 #[doc = "Drive Strength Field"]
7054 pub mod DSE {
7055 pub const offset: u32 = 3;
7056 pub const mask: u32 = 0x07 << offset;
7057 pub mod R {}
7058 pub mod W {}
7059 pub mod RW {
7060 #[doc = "output driver disabled;"]
7061 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
7062 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
7063 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
7064 #[doc = "R0/2"]
7065 pub const DSE_2_R0_2: u32 = 0x02;
7066 #[doc = "R0/3"]
7067 pub const DSE_3_R0_3: u32 = 0x03;
7068 #[doc = "R0/4"]
7069 pub const DSE_4_R0_4: u32 = 0x04;
7070 #[doc = "R0/5"]
7071 pub const DSE_5_R0_5: u32 = 0x05;
7072 #[doc = "R0/6"]
7073 pub const DSE_6_R0_6: u32 = 0x06;
7074 #[doc = "R0/7"]
7075 pub const DSE_7_R0_7: u32 = 0x07;
7076 }
7077 }
7078 #[doc = "Speed Field"]
7079 pub mod SPEED {
7080 pub const offset: u32 = 6;
7081 pub const mask: u32 = 0x03 << offset;
7082 pub mod R {}
7083 pub mod W {}
7084 pub mod RW {
7085 #[doc = "low(50MHz)"]
7086 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7087 #[doc = "medium(100MHz)"]
7088 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7089 #[doc = "fast(150MHz)"]
7090 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
7091 #[doc = "max(200MHz)"]
7092 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7093 }
7094 }
7095 #[doc = "Open Drain Enable Field"]
7096 pub mod ODE {
7097 pub const offset: u32 = 11;
7098 pub const mask: u32 = 0x01 << offset;
7099 pub mod R {}
7100 pub mod W {}
7101 pub mod RW {
7102 #[doc = "Open Drain Disabled"]
7103 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7104 #[doc = "Open Drain Enabled"]
7105 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7106 }
7107 }
7108 #[doc = "Pull / Keep Enable Field"]
7109 pub mod PKE {
7110 pub const offset: u32 = 12;
7111 pub const mask: u32 = 0x01 << offset;
7112 pub mod R {}
7113 pub mod W {}
7114 pub mod RW {
7115 #[doc = "Pull/Keeper Disabled"]
7116 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7117 #[doc = "Pull/Keeper Enabled"]
7118 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7119 }
7120 }
7121 #[doc = "Pull / Keep Select Field"]
7122 pub mod PUE {
7123 pub const offset: u32 = 13;
7124 pub const mask: u32 = 0x01 << offset;
7125 pub mod R {}
7126 pub mod W {}
7127 pub mod RW {
7128 #[doc = "Keeper"]
7129 pub const PUE_0_KEEPER: u32 = 0;
7130 #[doc = "Pull"]
7131 pub const PUE_1_PULL: u32 = 0x01;
7132 }
7133 }
7134 #[doc = "Pull Up / Down Config. Field"]
7135 pub mod PUS {
7136 pub const offset: u32 = 14;
7137 pub const mask: u32 = 0x03 << offset;
7138 pub mod R {}
7139 pub mod W {}
7140 pub mod RW {
7141 #[doc = "100K Ohm Pull Down"]
7142 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7143 #[doc = "47K Ohm Pull Up"]
7144 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7145 #[doc = "100K Ohm Pull Up"]
7146 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7147 #[doc = "22K Ohm Pull Up"]
7148 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7149 }
7150 }
7151 #[doc = "Hyst. Enable Field"]
7152 pub mod HYS {
7153 pub const offset: u32 = 16;
7154 pub const mask: u32 = 0x01 << offset;
7155 pub mod R {}
7156 pub mod W {}
7157 pub mod RW {
7158 #[doc = "Hysteresis Disabled"]
7159 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7160 #[doc = "Hysteresis Enabled"]
7161 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7162 }
7163 }
7164}
7165#[doc = "SW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register"]
7166pub mod SW_PAD_CTL_PAD_GPIO_02 {
7167 #[doc = "Slew Rate Field"]
7168 pub mod SRE {
7169 pub const offset: u32 = 0;
7170 pub const mask: u32 = 0x01 << offset;
7171 pub mod R {}
7172 pub mod W {}
7173 pub mod RW {
7174 #[doc = "Slow Slew Rate"]
7175 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7176 #[doc = "Fast Slew Rate"]
7177 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7178 }
7179 }
7180 #[doc = "Drive Strength Field"]
7181 pub mod DSE {
7182 pub const offset: u32 = 3;
7183 pub const mask: u32 = 0x07 << offset;
7184 pub mod R {}
7185 pub mod W {}
7186 pub mod RW {
7187 #[doc = "output driver disabled;"]
7188 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
7189 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
7190 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
7191 #[doc = "R0/2"]
7192 pub const DSE_2_R0_2: u32 = 0x02;
7193 #[doc = "R0/3"]
7194 pub const DSE_3_R0_3: u32 = 0x03;
7195 #[doc = "R0/4"]
7196 pub const DSE_4_R0_4: u32 = 0x04;
7197 #[doc = "R0/5"]
7198 pub const DSE_5_R0_5: u32 = 0x05;
7199 #[doc = "R0/6"]
7200 pub const DSE_6_R0_6: u32 = 0x06;
7201 #[doc = "R0/7"]
7202 pub const DSE_7_R0_7: u32 = 0x07;
7203 }
7204 }
7205 #[doc = "Speed Field"]
7206 pub mod SPEED {
7207 pub const offset: u32 = 6;
7208 pub const mask: u32 = 0x03 << offset;
7209 pub mod R {}
7210 pub mod W {}
7211 pub mod RW {
7212 #[doc = "low(50MHz)"]
7213 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7214 #[doc = "medium(100MHz)"]
7215 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7216 #[doc = "fast(150MHz)"]
7217 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
7218 #[doc = "max(200MHz)"]
7219 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7220 }
7221 }
7222 #[doc = "Open Drain Enable Field"]
7223 pub mod ODE {
7224 pub const offset: u32 = 11;
7225 pub const mask: u32 = 0x01 << offset;
7226 pub mod R {}
7227 pub mod W {}
7228 pub mod RW {
7229 #[doc = "Open Drain Disabled"]
7230 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7231 #[doc = "Open Drain Enabled"]
7232 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7233 }
7234 }
7235 #[doc = "Pull / Keep Enable Field"]
7236 pub mod PKE {
7237 pub const offset: u32 = 12;
7238 pub const mask: u32 = 0x01 << offset;
7239 pub mod R {}
7240 pub mod W {}
7241 pub mod RW {
7242 #[doc = "Pull/Keeper Disabled"]
7243 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7244 #[doc = "Pull/Keeper Enabled"]
7245 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7246 }
7247 }
7248 #[doc = "Pull / Keep Select Field"]
7249 pub mod PUE {
7250 pub const offset: u32 = 13;
7251 pub const mask: u32 = 0x01 << offset;
7252 pub mod R {}
7253 pub mod W {}
7254 pub mod RW {
7255 #[doc = "Keeper"]
7256 pub const PUE_0_KEEPER: u32 = 0;
7257 #[doc = "Pull"]
7258 pub const PUE_1_PULL: u32 = 0x01;
7259 }
7260 }
7261 #[doc = "Pull Up / Down Config. Field"]
7262 pub mod PUS {
7263 pub const offset: u32 = 14;
7264 pub const mask: u32 = 0x03 << offset;
7265 pub mod R {}
7266 pub mod W {}
7267 pub mod RW {
7268 #[doc = "100K Ohm Pull Down"]
7269 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7270 #[doc = "47K Ohm Pull Up"]
7271 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7272 #[doc = "100K Ohm Pull Up"]
7273 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7274 #[doc = "22K Ohm Pull Up"]
7275 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7276 }
7277 }
7278 #[doc = "Hyst. Enable Field"]
7279 pub mod HYS {
7280 pub const offset: u32 = 16;
7281 pub const mask: u32 = 0x01 << offset;
7282 pub mod R {}
7283 pub mod W {}
7284 pub mod RW {
7285 #[doc = "Hysteresis Disabled"]
7286 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7287 #[doc = "Hysteresis Enabled"]
7288 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7289 }
7290 }
7291}
7292#[doc = "SW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register"]
7293pub mod SW_PAD_CTL_PAD_GPIO_01 {
7294 #[doc = "Slew Rate Field"]
7295 pub mod SRE {
7296 pub const offset: u32 = 0;
7297 pub const mask: u32 = 0x01 << offset;
7298 pub mod R {}
7299 pub mod W {}
7300 pub mod RW {
7301 #[doc = "Slow Slew Rate"]
7302 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7303 #[doc = "Fast Slew Rate"]
7304 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7305 }
7306 }
7307 #[doc = "Drive Strength Field"]
7308 pub mod DSE {
7309 pub const offset: u32 = 3;
7310 pub const mask: u32 = 0x07 << offset;
7311 pub mod R {}
7312 pub mod W {}
7313 pub mod RW {
7314 #[doc = "output driver disabled;"]
7315 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
7316 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
7317 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
7318 #[doc = "R0/2"]
7319 pub const DSE_2_R0_2: u32 = 0x02;
7320 #[doc = "R0/3"]
7321 pub const DSE_3_R0_3: u32 = 0x03;
7322 #[doc = "R0/4"]
7323 pub const DSE_4_R0_4: u32 = 0x04;
7324 #[doc = "R0/5"]
7325 pub const DSE_5_R0_5: u32 = 0x05;
7326 #[doc = "R0/6"]
7327 pub const DSE_6_R0_6: u32 = 0x06;
7328 #[doc = "R0/7"]
7329 pub const DSE_7_R0_7: u32 = 0x07;
7330 }
7331 }
7332 #[doc = "Speed Field"]
7333 pub mod SPEED {
7334 pub const offset: u32 = 6;
7335 pub const mask: u32 = 0x03 << offset;
7336 pub mod R {}
7337 pub mod W {}
7338 pub mod RW {
7339 #[doc = "low(50MHz)"]
7340 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7341 #[doc = "medium(100MHz)"]
7342 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7343 #[doc = "fast(150MHz)"]
7344 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
7345 #[doc = "max(200MHz)"]
7346 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7347 }
7348 }
7349 #[doc = "Open Drain Enable Field"]
7350 pub mod ODE {
7351 pub const offset: u32 = 11;
7352 pub const mask: u32 = 0x01 << offset;
7353 pub mod R {}
7354 pub mod W {}
7355 pub mod RW {
7356 #[doc = "Open Drain Disabled"]
7357 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7358 #[doc = "Open Drain Enabled"]
7359 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7360 }
7361 }
7362 #[doc = "Pull / Keep Enable Field"]
7363 pub mod PKE {
7364 pub const offset: u32 = 12;
7365 pub const mask: u32 = 0x01 << offset;
7366 pub mod R {}
7367 pub mod W {}
7368 pub mod RW {
7369 #[doc = "Pull/Keeper Disabled"]
7370 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7371 #[doc = "Pull/Keeper Enabled"]
7372 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7373 }
7374 }
7375 #[doc = "Pull / Keep Select Field"]
7376 pub mod PUE {
7377 pub const offset: u32 = 13;
7378 pub const mask: u32 = 0x01 << offset;
7379 pub mod R {}
7380 pub mod W {}
7381 pub mod RW {
7382 #[doc = "Keeper"]
7383 pub const PUE_0_KEEPER: u32 = 0;
7384 #[doc = "Pull"]
7385 pub const PUE_1_PULL: u32 = 0x01;
7386 }
7387 }
7388 #[doc = "Pull Up / Down Config. Field"]
7389 pub mod PUS {
7390 pub const offset: u32 = 14;
7391 pub const mask: u32 = 0x03 << offset;
7392 pub mod R {}
7393 pub mod W {}
7394 pub mod RW {
7395 #[doc = "100K Ohm Pull Down"]
7396 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7397 #[doc = "47K Ohm Pull Up"]
7398 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7399 #[doc = "100K Ohm Pull Up"]
7400 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7401 #[doc = "22K Ohm Pull Up"]
7402 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7403 }
7404 }
7405 #[doc = "Hyst. Enable Field"]
7406 pub mod HYS {
7407 pub const offset: u32 = 16;
7408 pub const mask: u32 = 0x01 << offset;
7409 pub mod R {}
7410 pub mod W {}
7411 pub mod RW {
7412 #[doc = "Hysteresis Disabled"]
7413 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7414 #[doc = "Hysteresis Enabled"]
7415 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7416 }
7417 }
7418}
7419#[doc = "SW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register"]
7420pub mod SW_PAD_CTL_PAD_GPIO_00 {
7421 #[doc = "Slew Rate Field"]
7422 pub mod SRE {
7423 pub const offset: u32 = 0;
7424 pub const mask: u32 = 0x01 << offset;
7425 pub mod R {}
7426 pub mod W {}
7427 pub mod RW {
7428 #[doc = "Slow Slew Rate"]
7429 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7430 #[doc = "Fast Slew Rate"]
7431 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7432 }
7433 }
7434 #[doc = "Drive Strength Field"]
7435 pub mod DSE {
7436 pub const offset: u32 = 3;
7437 pub const mask: u32 = 0x07 << offset;
7438 pub mod R {}
7439 pub mod W {}
7440 pub mod RW {
7441 #[doc = "output driver disabled;"]
7442 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
7443 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)"]
7444 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
7445 #[doc = "R0/2"]
7446 pub const DSE_2_R0_2: u32 = 0x02;
7447 #[doc = "R0/3"]
7448 pub const DSE_3_R0_3: u32 = 0x03;
7449 #[doc = "R0/4"]
7450 pub const DSE_4_R0_4: u32 = 0x04;
7451 #[doc = "R0/5"]
7452 pub const DSE_5_R0_5: u32 = 0x05;
7453 #[doc = "R0/6"]
7454 pub const DSE_6_R0_6: u32 = 0x06;
7455 #[doc = "R0/7"]
7456 pub const DSE_7_R0_7: u32 = 0x07;
7457 }
7458 }
7459 #[doc = "Speed Field"]
7460 pub mod SPEED {
7461 pub const offset: u32 = 6;
7462 pub const mask: u32 = 0x03 << offset;
7463 pub mod R {}
7464 pub mod W {}
7465 pub mod RW {
7466 #[doc = "low(50MHz)"]
7467 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7468 #[doc = "medium(100MHz)"]
7469 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7470 #[doc = "fast(150MHz)"]
7471 pub const SPEED_2_FAST_150MHZ: u32 = 0x02;
7472 #[doc = "max(200MHz)"]
7473 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7474 }
7475 }
7476 #[doc = "Open Drain Enable Field"]
7477 pub mod ODE {
7478 pub const offset: u32 = 11;
7479 pub const mask: u32 = 0x01 << offset;
7480 pub mod R {}
7481 pub mod W {}
7482 pub mod RW {
7483 #[doc = "Open Drain Disabled"]
7484 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7485 #[doc = "Open Drain Enabled"]
7486 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7487 }
7488 }
7489 #[doc = "Pull / Keep Enable Field"]
7490 pub mod PKE {
7491 pub const offset: u32 = 12;
7492 pub const mask: u32 = 0x01 << offset;
7493 pub mod R {}
7494 pub mod W {}
7495 pub mod RW {
7496 #[doc = "Pull/Keeper Disabled"]
7497 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7498 #[doc = "Pull/Keeper Enabled"]
7499 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7500 }
7501 }
7502 #[doc = "Pull / Keep Select Field"]
7503 pub mod PUE {
7504 pub const offset: u32 = 13;
7505 pub const mask: u32 = 0x01 << offset;
7506 pub mod R {}
7507 pub mod W {}
7508 pub mod RW {
7509 #[doc = "Keeper"]
7510 pub const PUE_0_KEEPER: u32 = 0;
7511 #[doc = "Pull"]
7512 pub const PUE_1_PULL: u32 = 0x01;
7513 }
7514 }
7515 #[doc = "Pull Up / Down Config. Field"]
7516 pub mod PUS {
7517 pub const offset: u32 = 14;
7518 pub const mask: u32 = 0x03 << offset;
7519 pub mod R {}
7520 pub mod W {}
7521 pub mod RW {
7522 #[doc = "100K Ohm Pull Down"]
7523 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7524 #[doc = "47K Ohm Pull Up"]
7525 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7526 #[doc = "100K Ohm Pull Up"]
7527 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7528 #[doc = "22K Ohm Pull Up"]
7529 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7530 }
7531 }
7532 #[doc = "Hyst. Enable Field"]
7533 pub mod HYS {
7534 pub const offset: u32 = 16;
7535 pub const mask: u32 = 0x01 << offset;
7536 pub mod R {}
7537 pub mod W {}
7538 pub mod RW {
7539 #[doc = "Hysteresis Disabled"]
7540 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7541 #[doc = "Hysteresis Enabled"]
7542 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7543 }
7544 }
7545}
7546#[doc = "USB_OTG_ID_SELECT_INPUT DAISY Register"]
7547pub mod USB_OTG_ID_SELECT_INPUT {
7548 #[doc = "Selecting Pads Involved in Daisy Chain."]
7549 pub mod DAISY {
7550 pub const offset: u32 = 0;
7551 pub const mask: u32 = 0x01 << offset;
7552 pub mod R {}
7553 pub mod W {}
7554 pub mod RW {
7555 #[doc = "Selecting Pad: GPIO_AD_10 for Mode: ALT6"]
7556 pub const GPIO_AD_10_ALT6: u32 = 0;
7557 #[doc = "Selecting Pad: GPIO_13 for Mode: ALT3"]
7558 pub const GPIO_13_ALT3: u32 = 0x01;
7559 }
7560 }
7561}
7562#[doc = "FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register"]
7563pub mod FLEXPWM1_PWMA_SELECT_INPUT_0 {
7564 #[doc = "Selecting Pads Involved in Daisy Chain."]
7565 pub mod DAISY {
7566 pub const offset: u32 = 0;
7567 pub const mask: u32 = 0x01 << offset;
7568 pub mod R {}
7569 pub mod W {}
7570 pub mod RW {
7571 #[doc = "Selecting Pad: GPIO_SD_02 for Mode: ALT2"]
7572 pub const GPIO_SD_02_ALT2: u32 = 0;
7573 #[doc = "Selecting Pad: GPIO_02 for Mode: ALT2"]
7574 pub const GPIO_02_ALT2: u32 = 0x01;
7575 }
7576 }
7577}
7578#[doc = "FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register"]
7579pub mod FLEXPWM1_PWMA_SELECT_INPUT_1 {
7580 #[doc = "Selecting Pads Involved in Daisy Chain."]
7581 pub mod DAISY {
7582 pub const offset: u32 = 0;
7583 pub const mask: u32 = 0x01 << offset;
7584 pub mod R {}
7585 pub mod W {}
7586 pub mod RW {
7587 #[doc = "Selecting Pad: GPIO_SD_04 for Mode: ALT2"]
7588 pub const GPIO_SD_04_ALT2: u32 = 0;
7589 #[doc = "Selecting Pad: GPIO_04 for Mode: ALT2"]
7590 pub const GPIO_04_ALT2: u32 = 0x01;
7591 }
7592 }
7593}
7594#[doc = "FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register"]
7595pub mod FLEXPWM1_PWMA_SELECT_INPUT_2 {
7596 #[doc = "Selecting Pads Involved in Daisy Chain."]
7597 pub mod DAISY {
7598 pub const offset: u32 = 0;
7599 pub const mask: u32 = 0x01 << offset;
7600 pub mod R {}
7601 pub mod W {}
7602 pub mod RW {
7603 #[doc = "Selecting Pad: GPIO_AD_04 for Mode: ALT2"]
7604 pub const GPIO_AD_04_ALT2: u32 = 0;
7605 #[doc = "Selecting Pad: GPIO_06 for Mode: ALT2"]
7606 pub const GPIO_06_ALT2: u32 = 0x01;
7607 }
7608 }
7609}
7610#[doc = "FLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register"]
7611pub mod FLEXPWM1_PWMA_SELECT_INPUT_3 {
7612 #[doc = "Selecting Pads Involved in Daisy Chain."]
7613 pub mod DAISY {
7614 pub const offset: u32 = 0;
7615 pub const mask: u32 = 0x01 << offset;
7616 pub mod R {}
7617 pub mod W {}
7618 pub mod RW {
7619 #[doc = "Selecting Pad: GPIO_AD_06 for Mode: ALT2"]
7620 pub const GPIO_AD_06_ALT2: u32 = 0;
7621 #[doc = "Selecting Pad: GPIO_08 for Mode: ALT2"]
7622 pub const GPIO_08_ALT2: u32 = 0x01;
7623 }
7624 }
7625}
7626#[doc = "FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register"]
7627pub mod FLEXPWM1_PWMB_SELECT_INPUT_0 {
7628 #[doc = "Selecting Pads Involved in Daisy Chain."]
7629 pub mod DAISY {
7630 pub const offset: u32 = 0;
7631 pub const mask: u32 = 0x01 << offset;
7632 pub mod R {}
7633 pub mod W {}
7634 pub mod RW {
7635 #[doc = "Selecting Pad: GPIO_SD_01 for Mode: ALT2"]
7636 pub const GPIO_SD_01_ALT2: u32 = 0;
7637 #[doc = "Selecting Pad: GPIO_01 for Mode: ALT2"]
7638 pub const GPIO_01_ALT2: u32 = 0x01;
7639 }
7640 }
7641}
7642#[doc = "FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register"]
7643pub mod FLEXPWM1_PWMB_SELECT_INPUT_1 {
7644 #[doc = "Selecting Pads Involved in Daisy Chain."]
7645 pub mod DAISY {
7646 pub const offset: u32 = 0;
7647 pub const mask: u32 = 0x01 << offset;
7648 pub mod R {}
7649 pub mod W {}
7650 pub mod RW {
7651 #[doc = "Selecting Pad: GPIO_SD_03 for Mode: ALT2"]
7652 pub const GPIO_SD_03_ALT2: u32 = 0;
7653 #[doc = "Selecting Pad: GPIO_03 for Mode: ALT2"]
7654 pub const GPIO_03_ALT2: u32 = 0x01;
7655 }
7656 }
7657}
7658#[doc = "FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register"]
7659pub mod FLEXPWM1_PWMB_SELECT_INPUT_2 {
7660 #[doc = "Selecting Pads Involved in Daisy Chain."]
7661 pub mod DAISY {
7662 pub const offset: u32 = 0;
7663 pub const mask: u32 = 0x01 << offset;
7664 pub mod R {}
7665 pub mod W {}
7666 pub mod RW {
7667 #[doc = "Selecting Pad: GPIO_AD_03 for Mode: ALT2"]
7668 pub const GPIO_AD_03_ALT2: u32 = 0;
7669 #[doc = "Selecting Pad: GPIO_05 for Mode: ALT2"]
7670 pub const GPIO_05_ALT2: u32 = 0x01;
7671 }
7672 }
7673}
7674#[doc = "FLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register"]
7675pub mod FLEXPWM1_PWMB_SELECT_INPUT_3 {
7676 #[doc = "Selecting Pads Involved in Daisy Chain."]
7677 pub mod DAISY {
7678 pub const offset: u32 = 0;
7679 pub const mask: u32 = 0x01 << offset;
7680 pub mod R {}
7681 pub mod W {}
7682 pub mod RW {
7683 #[doc = "Selecting Pad: GPIO_AD_05 for Mode: ALT2"]
7684 pub const GPIO_AD_05_ALT2: u32 = 0;
7685 #[doc = "Selecting Pad: GPIO_07 for Mode: ALT2"]
7686 pub const GPIO_07_ALT2: u32 = 0x01;
7687 }
7688 }
7689}
7690#[doc = "FLEXSPI_DQS_FA_SELECT_INPUT DAISY Register"]
7691pub mod FLEXSPI_DQS_FA_SELECT_INPUT {
7692 #[doc = "Selecting Pads Involved in Daisy Chain."]
7693 pub mod DAISY {
7694 pub const offset: u32 = 0;
7695 pub const mask: u32 = 0x01 << offset;
7696 pub mod R {}
7697 pub mod W {}
7698 pub mod RW {
7699 #[doc = "Selecting Pad: GPIO_SD_14 for Mode: ALT0"]
7700 pub const GPIO_SD_14_ALT0: u32 = 0;
7701 #[doc = "Selecting Pad: GPIO_SD_12 for Mode: ALT0"]
7702 pub const GPIO_SD_12_ALT0: u32 = 0x01;
7703 }
7704 }
7705}
7706#[doc = "FLEXSPI_DQS_FB_SELECT_INPUT DAISY Register"]
7707pub mod FLEXSPI_DQS_FB_SELECT_INPUT {
7708 #[doc = "Selecting Pads Involved in Daisy Chain."]
7709 pub mod DAISY {
7710 pub const offset: u32 = 0;
7711 pub const mask: u32 = 0x01 << offset;
7712 pub mod R {}
7713 pub mod W {}
7714 pub mod RW {
7715 #[doc = "Selecting Pad: GPIO_SD_14 for Mode: ALT1"]
7716 pub const GPIO_SD_14_ALT1: u32 = 0;
7717 #[doc = "Selecting Pad: GPIO_00 for Mode: ALT0"]
7718 pub const GPIO_00_ALT0: u32 = 0x01;
7719 }
7720 }
7721}
7722#[doc = "KPP_COL_SELECT_INPUT_0 DAISY Register"]
7723pub mod KPP_COL_SELECT_INPUT_0 {
7724 #[doc = "Selecting Pads Involved in Daisy Chain."]
7725 pub mod DAISY {
7726 pub const offset: u32 = 0;
7727 pub const mask: u32 = 0x01 << offset;
7728 pub mod R {}
7729 pub mod W {}
7730 pub mod RW {
7731 #[doc = "Selecting Pad: GPIO_AD_14 for Mode: ALT2"]
7732 pub const GPIO_AD_14_ALT2: u32 = 0;
7733 #[doc = "Selecting Pad: GPIO_12 for Mode: ALT2"]
7734 pub const GPIO_12_ALT2: u32 = 0x01;
7735 }
7736 }
7737}
7738#[doc = "KPP_COL_SELECT_INPUT_1 DAISY Register"]
7739pub mod KPP_COL_SELECT_INPUT_1 {
7740 #[doc = "Selecting Pads Involved in Daisy Chain."]
7741 pub mod DAISY {
7742 pub const offset: u32 = 0;
7743 pub const mask: u32 = 0x01 << offset;
7744 pub mod R {}
7745 pub mod W {}
7746 pub mod RW {
7747 #[doc = "Selecting Pad: GPIO_AD_12 for Mode: ALT2"]
7748 pub const GPIO_AD_12_ALT2: u32 = 0;
7749 #[doc = "Selecting Pad: GPIO_AD_06 for Mode: ALT3"]
7750 pub const GPIO_AD_06_ALT3: u32 = 0x01;
7751 }
7752 }
7753}
7754#[doc = "KPP_COL_SELECT_INPUT_2 DAISY Register"]
7755pub mod KPP_COL_SELECT_INPUT_2 {
7756 #[doc = "Selecting Pads Involved in Daisy Chain."]
7757 pub mod DAISY {
7758 pub const offset: u32 = 0;
7759 pub const mask: u32 = 0x01 << offset;
7760 pub mod R {}
7761 pub mod W {}
7762 pub mod RW {
7763 #[doc = "Selecting Pad: GPIO_AD_10 for Mode: ALT2"]
7764 pub const GPIO_AD_10_ALT2: u32 = 0;
7765 #[doc = "Selecting Pad: GPIO_AD_04 for Mode: ALT3"]
7766 pub const GPIO_AD_04_ALT3: u32 = 0x01;
7767 }
7768 }
7769}
7770#[doc = "KPP_COL_SELECT_INPUT_3 DAISY Register"]
7771pub mod KPP_COL_SELECT_INPUT_3 {
7772 #[doc = "Selecting Pads Involved in Daisy Chain."]
7773 pub mod DAISY {
7774 pub const offset: u32 = 0;
7775 pub const mask: u32 = 0x01 << offset;
7776 pub mod R {}
7777 pub mod W {}
7778 pub mod RW {
7779 #[doc = "Selecting Pad: GPIO_AD_00 for Mode: ALT2"]
7780 pub const GPIO_AD_00_ALT2: u32 = 0;
7781 #[doc = "Selecting Pad: GPIO_02 for Mode: ALT4"]
7782 pub const GPIO_02_ALT4: u32 = 0x01;
7783 }
7784 }
7785}
7786#[doc = "KPP_ROW_SELECT_INPUT_0 DAISY Register"]
7787pub mod KPP_ROW_SELECT_INPUT_0 {
7788 #[doc = "Selecting Pads Involved in Daisy Chain."]
7789 pub mod DAISY {
7790 pub const offset: u32 = 0;
7791 pub const mask: u32 = 0x01 << offset;
7792 pub mod R {}
7793 pub mod W {}
7794 pub mod RW {
7795 #[doc = "Selecting Pad: GPIO_AD_13 for Mode: ALT2"]
7796 pub const GPIO_AD_13_ALT2: u32 = 0;
7797 #[doc = "Selecting Pad: GPIO_11 for Mode: ALT2"]
7798 pub const GPIO_11_ALT2: u32 = 0x01;
7799 }
7800 }
7801}
7802#[doc = "KPP_ROW_SELECT_INPUT_1 DAISY Register"]
7803pub mod KPP_ROW_SELECT_INPUT_1 {
7804 #[doc = "Selecting Pads Involved in Daisy Chain."]
7805 pub mod DAISY {
7806 pub const offset: u32 = 0;
7807 pub const mask: u32 = 0x01 << offset;
7808 pub mod R {}
7809 pub mod W {}
7810 pub mod RW {
7811 #[doc = "Selecting Pad: GPIO_AD_11 for Mode: ALT2"]
7812 pub const GPIO_AD_11_ALT2: u32 = 0;
7813 #[doc = "Selecting Pad: GPIO_AD_05 for Mode: ALT3"]
7814 pub const GPIO_AD_05_ALT3: u32 = 0x01;
7815 }
7816 }
7817}
7818#[doc = "KPP_ROW_SELECT_INPUT_2 DAISY Register"]
7819pub mod KPP_ROW_SELECT_INPUT_2 {
7820 #[doc = "Selecting Pads Involved in Daisy Chain."]
7821 pub mod DAISY {
7822 pub const offset: u32 = 0;
7823 pub const mask: u32 = 0x01 << offset;
7824 pub mod R {}
7825 pub mod W {}
7826 pub mod RW {
7827 #[doc = "Selecting Pad: GPIO_AD_09 for Mode: ALT2"]
7828 pub const GPIO_AD_09_ALT2: u32 = 0;
7829 #[doc = "Selecting Pad: GPIO_AD_03 for Mode: ALT3"]
7830 pub const GPIO_AD_03_ALT3: u32 = 0x01;
7831 }
7832 }
7833}
7834#[doc = "KPP_ROW_SELECT_INPUT_3 DAISY Register"]
7835pub mod KPP_ROW_SELECT_INPUT_3 {
7836 #[doc = "Selecting Pads Involved in Daisy Chain."]
7837 pub mod DAISY {
7838 pub const offset: u32 = 0;
7839 pub const mask: u32 = 0x01 << offset;
7840 pub mod R {}
7841 pub mod W {}
7842 pub mod RW {
7843 #[doc = "Selecting Pad: GPIO_13 for Mode: ALT2"]
7844 pub const GPIO_13_ALT2: u32 = 0;
7845 #[doc = "Selecting Pad: GPIO_01 for Mode: ALT4"]
7846 pub const GPIO_01_ALT4: u32 = 0x01;
7847 }
7848 }
7849}
7850#[doc = "LPI2C1_HREQ_SELECT_INPUT DAISY Register"]
7851pub mod LPI2C1_HREQ_SELECT_INPUT {
7852 #[doc = "Selecting Pads Involved in Daisy Chain."]
7853 pub mod DAISY {
7854 pub const offset: u32 = 0;
7855 pub const mask: u32 = 0x01 << offset;
7856 pub mod R {}
7857 pub mod W {}
7858 pub mod RW {
7859 #[doc = "Selecting Pad: GPIO_AD_06 for Mode: ALT6"]
7860 pub const GPIO_AD_06_ALT6: u32 = 0;
7861 #[doc = "Selecting Pad: GPIO_10 for Mode: ALT1"]
7862 pub const GPIO_10_ALT1: u32 = 0x01;
7863 }
7864 }
7865}
7866#[doc = "LPI2C1_SCL_SELECT_INPUT DAISY Register"]
7867pub mod LPI2C1_SCL_SELECT_INPUT {
7868 #[doc = "Selecting Pads Involved in Daisy Chain."]
7869 pub mod DAISY {
7870 pub const offset: u32 = 0;
7871 pub const mask: u32 = 0x03 << offset;
7872 pub mod R {}
7873 pub mod W {}
7874 pub mod RW {
7875 #[doc = "Selecting Pad: GPIO_AD_14 for Mode: ALT0"]
7876 pub const GPIO_AD_14_ALT0: u32 = 0;
7877 #[doc = "Selecting Pad: GPIO_SD_06 for Mode: ALT1"]
7878 pub const GPIO_SD_06_ALT1: u32 = 0x01;
7879 #[doc = "Selecting Pad: GPIO_12 for Mode: ALT1"]
7880 pub const GPIO_12_ALT1: u32 = 0x02;
7881 #[doc = "Selecting Pad: GPIO_02 for Mode: ALT3"]
7882 pub const GPIO_02_ALT3: u32 = 0x03;
7883 }
7884 }
7885}
7886#[doc = "LPI2C1_SDA_SELECT_INPUT DAISY Register"]
7887pub mod LPI2C1_SDA_SELECT_INPUT {
7888 #[doc = "Selecting Pads Involved in Daisy Chain."]
7889 pub mod DAISY {
7890 pub const offset: u32 = 0;
7891 pub const mask: u32 = 0x03 << offset;
7892 pub mod R {}
7893 pub mod W {}
7894 pub mod RW {
7895 #[doc = "Selecting Pad: GPIO_AD_13 for Mode: ALT0"]
7896 pub const GPIO_AD_13_ALT0: u32 = 0;
7897 #[doc = "Selecting Pad: GPIO_SD_05 for Mode: ALT1"]
7898 pub const GPIO_SD_05_ALT1: u32 = 0x01;
7899 #[doc = "Selecting Pad: GPIO_11 for Mode: ALT1"]
7900 pub const GPIO_11_ALT1: u32 = 0x02;
7901 #[doc = "Selecting Pad: GPIO_01 for Mode: ALT3"]
7902 pub const GPIO_01_ALT3: u32 = 0x03;
7903 }
7904 }
7905}
7906#[doc = "LPI2C2_SCL_SELECT_INPUT DAISY Register"]
7907pub mod LPI2C2_SCL_SELECT_INPUT {
7908 #[doc = "Selecting Pads Involved in Daisy Chain."]
7909 pub mod DAISY {
7910 pub const offset: u32 = 0;
7911 pub const mask: u32 = 0x03 << offset;
7912 pub mod R {}
7913 pub mod W {}
7914 pub mod RW {
7915 #[doc = "Selecting Pad: GPIO_AD_08 for Mode: ALT0"]
7916 pub const GPIO_AD_08_ALT0: u32 = 0;
7917 #[doc = "Selecting Pad: GPIO_AD_02 for Mode: ALT3"]
7918 pub const GPIO_AD_02_ALT3: u32 = 0x01;
7919 #[doc = "Selecting Pad: GPIO_SD_08 for Mode: ALT1"]
7920 pub const GPIO_SD_08_ALT1: u32 = 0x02;
7921 #[doc = "Selecting Pad: GPIO_10 for Mode: ALT3"]
7922 pub const GPIO_10_ALT3: u32 = 0x03;
7923 }
7924 }
7925}
7926#[doc = "LPI2C2_SDA_SELECT_INPUT DAISY Register"]
7927pub mod LPI2C2_SDA_SELECT_INPUT {
7928 #[doc = "Selecting Pads Involved in Daisy Chain."]
7929 pub mod DAISY {
7930 pub const offset: u32 = 0;
7931 pub const mask: u32 = 0x03 << offset;
7932 pub mod R {}
7933 pub mod W {}
7934 pub mod RW {
7935 #[doc = "Selecting Pad: GPIO_AD_07 for Mode: ALT0"]
7936 pub const GPIO_AD_07_ALT0: u32 = 0;
7937 #[doc = "Selecting Pad: GPIO_AD_01 for Mode: ALT3"]
7938 pub const GPIO_AD_01_ALT3: u32 = 0x01;
7939 #[doc = "Selecting Pad: GPIO_SD_07 for Mode: ALT1"]
7940 pub const GPIO_SD_07_ALT1: u32 = 0x02;
7941 #[doc = "Selecting Pad: GPIO_09 for Mode: ALT3"]
7942 pub const GPIO_09_ALT3: u32 = 0x03;
7943 }
7944 }
7945}
7946#[doc = "LPSPI1_PCS_SELECT_INPUT_0 DAISY Register"]
7947pub mod LPSPI1_PCS_SELECT_INPUT_0 {
7948 #[doc = "Selecting Pads Involved in Daisy Chain."]
7949 pub mod DAISY {
7950 pub const offset: u32 = 0;
7951 pub const mask: u32 = 0x01 << offset;
7952 pub mod R {}
7953 pub mod W {}
7954 pub mod RW {
7955 #[doc = "Selecting Pad: GPIO_AD_05 for Mode: ALT0"]
7956 pub const GPIO_AD_05_ALT0: u32 = 0;
7957 #[doc = "Selecting Pad: GPIO_SD_07 for Mode: ALT2"]
7958 pub const GPIO_SD_07_ALT2: u32 = 0x01;
7959 }
7960 }
7961}
7962#[doc = "LPSPI1_SCK_SELECT_INPUT DAISY Register"]
7963pub mod LPSPI1_SCK_SELECT_INPUT {
7964 #[doc = "Selecting Pads Involved in Daisy Chain."]
7965 pub mod DAISY {
7966 pub const offset: u32 = 0;
7967 pub const mask: u32 = 0x01 << offset;
7968 pub mod R {}
7969 pub mod W {}
7970 pub mod RW {
7971 #[doc = "Selecting Pad: GPIO_AD_06 for Mode: ALT0"]
7972 pub const GPIO_AD_06_ALT0: u32 = 0;
7973 #[doc = "Selecting Pad: GPIO_SD_08 for Mode: ALT2"]
7974 pub const GPIO_SD_08_ALT2: u32 = 0x01;
7975 }
7976 }
7977}
7978#[doc = "LPSPI1_SDI_SELECT_INPUT DAISY Register"]
7979pub mod LPSPI1_SDI_SELECT_INPUT {
7980 #[doc = "Selecting Pads Involved in Daisy Chain."]
7981 pub mod DAISY {
7982 pub const offset: u32 = 0;
7983 pub const mask: u32 = 0x01 << offset;
7984 pub mod R {}
7985 pub mod W {}
7986 pub mod RW {
7987 #[doc = "Selecting Pad: GPIO_AD_03 for Mode: ALT0"]
7988 pub const GPIO_AD_03_ALT0: u32 = 0;
7989 #[doc = "Selecting Pad: GPIO_SD_05 for Mode: ALT2"]
7990 pub const GPIO_SD_05_ALT2: u32 = 0x01;
7991 }
7992 }
7993}
7994#[doc = "LPSPI1_SDO_SELECT_INPUT DAISY Register"]
7995pub mod LPSPI1_SDO_SELECT_INPUT {
7996 #[doc = "Selecting Pads Involved in Daisy Chain."]
7997 pub mod DAISY {
7998 pub const offset: u32 = 0;
7999 pub const mask: u32 = 0x01 << offset;
8000 pub mod R {}
8001 pub mod W {}
8002 pub mod RW {
8003 #[doc = "Selecting Pad: GPIO_AD_04 for Mode: ALT0"]
8004 pub const GPIO_AD_04_ALT0: u32 = 0;
8005 #[doc = "Selecting Pad: GPIO_SD_06 for Mode: ALT2"]
8006 pub const GPIO_SD_06_ALT2: u32 = 0x01;
8007 }
8008 }
8009}
8010#[doc = "LPSPI2_PCS_SELECT_INPUT_0 DAISY Register"]
8011pub mod LPSPI2_PCS_SELECT_INPUT_0 {
8012 #[doc = "Selecting Pads Involved in Daisy Chain."]
8013 pub mod DAISY {
8014 pub const offset: u32 = 0;
8015 pub const mask: u32 = 0x01 << offset;
8016 pub mod R {}
8017 pub mod W {}
8018 pub mod RW {
8019 #[doc = "Selecting Pad: GPIO_AD_11 for Mode: ALT0"]
8020 pub const GPIO_AD_11_ALT0: u32 = 0;
8021 #[doc = "Selecting Pad: GPIO_SD_12 for Mode: ALT1"]
8022 pub const GPIO_SD_12_ALT1: u32 = 0x01;
8023 }
8024 }
8025}
8026#[doc = "LPSPI2_SCK_SELECT_INPUT DAISY Register"]
8027pub mod LPSPI2_SCK_SELECT_INPUT {
8028 #[doc = "Selecting Pads Involved in Daisy Chain."]
8029 pub mod DAISY {
8030 pub const offset: u32 = 0;
8031 pub const mask: u32 = 0x01 << offset;
8032 pub mod R {}
8033 pub mod W {}
8034 pub mod RW {
8035 #[doc = "Selecting Pad: GPIO_AD_12 for Mode: ALT0"]
8036 pub const GPIO_AD_12_ALT0: u32 = 0;
8037 #[doc = "Selecting Pad: GPIO_SD_11 for Mode: ALT1"]
8038 pub const GPIO_SD_11_ALT1: u32 = 0x01;
8039 }
8040 }
8041}
8042#[doc = "LPSPI2_SDI_SELECT_INPUT DAISY Register"]
8043pub mod LPSPI2_SDI_SELECT_INPUT {
8044 #[doc = "Selecting Pads Involved in Daisy Chain."]
8045 pub mod DAISY {
8046 pub const offset: u32 = 0;
8047 pub const mask: u32 = 0x01 << offset;
8048 pub mod R {}
8049 pub mod W {}
8050 pub mod RW {
8051 #[doc = "Selecting Pad: GPIO_AD_09 for Mode: ALT0"]
8052 pub const GPIO_AD_09_ALT0: u32 = 0;
8053 #[doc = "Selecting Pad: GPIO_SD_09 for Mode: ALT1"]
8054 pub const GPIO_SD_09_ALT1: u32 = 0x01;
8055 }
8056 }
8057}
8058#[doc = "LPSPI2_SDO_SELECT_INPUT DAISY Register"]
8059pub mod LPSPI2_SDO_SELECT_INPUT {
8060 #[doc = "Selecting Pads Involved in Daisy Chain."]
8061 pub mod DAISY {
8062 pub const offset: u32 = 0;
8063 pub const mask: u32 = 0x01 << offset;
8064 pub mod R {}
8065 pub mod W {}
8066 pub mod RW {
8067 #[doc = "Selecting Pad: GPIO_AD_10 for Mode: ALT0"]
8068 pub const GPIO_AD_10_ALT0: u32 = 0;
8069 #[doc = "Selecting Pad: GPIO_SD_10 for Mode: ALT1"]
8070 pub const GPIO_SD_10_ALT1: u32 = 0x01;
8071 }
8072 }
8073}
8074#[doc = "LPUART1_RXD_SELECT_INPUT DAISY Register"]
8075pub mod LPUART1_RXD_SELECT_INPUT {
8076 #[doc = "Selecting Pads Involved in Daisy Chain."]
8077 pub mod DAISY {
8078 pub const offset: u32 = 0;
8079 pub const mask: u32 = 0x01 << offset;
8080 pub mod R {}
8081 pub mod W {}
8082 pub mod RW {
8083 #[doc = "Selecting Pad: GPIO_SD_11 for Mode: ALT2"]
8084 pub const GPIO_SD_11_ALT2: u32 = 0;
8085 #[doc = "Selecting Pad: GPIO_09 for Mode: ALT0"]
8086 pub const GPIO_09_ALT0: u32 = 0x01;
8087 }
8088 }
8089}
8090#[doc = "LPUART1_TXD_SELECT_INPUT DAISY Register"]
8091pub mod LPUART1_TXD_SELECT_INPUT {
8092 #[doc = "Selecting Pads Involved in Daisy Chain."]
8093 pub mod DAISY {
8094 pub const offset: u32 = 0;
8095 pub const mask: u32 = 0x01 << offset;
8096 pub mod R {}
8097 pub mod W {}
8098 pub mod RW {
8099 #[doc = "Selecting Pad: GPIO_SD_12 for Mode: ALT2"]
8100 pub const GPIO_SD_12_ALT2: u32 = 0;
8101 #[doc = "Selecting Pad: GPIO_10 for Mode: ALT0"]
8102 pub const GPIO_10_ALT0: u32 = 0x01;
8103 }
8104 }
8105}
8106#[doc = "LPUART2_RXD_SELECT_INPUT DAISY Register"]
8107pub mod LPUART2_RXD_SELECT_INPUT {
8108 #[doc = "Selecting Pads Involved in Daisy Chain."]
8109 pub mod DAISY {
8110 pub const offset: u32 = 0;
8111 pub const mask: u32 = 0x01 << offset;
8112 pub mod R {}
8113 pub mod W {}
8114 pub mod RW {
8115 #[doc = "Selecting Pad: GPIO_SD_09 for Mode: ALT2"]
8116 pub const GPIO_SD_09_ALT2: u32 = 0;
8117 #[doc = "Selecting Pad: GPIO_13 for Mode: ALT0"]
8118 pub const GPIO_13_ALT0: u32 = 0x01;
8119 }
8120 }
8121}
8122#[doc = "LPUART2_TXD_SELECT_INPUT DAISY Register"]
8123pub mod LPUART2_TXD_SELECT_INPUT {
8124 #[doc = "Selecting Pads Involved in Daisy Chain."]
8125 pub mod DAISY {
8126 pub const offset: u32 = 0;
8127 pub const mask: u32 = 0x01 << offset;
8128 pub mod R {}
8129 pub mod W {}
8130 pub mod RW {
8131 #[doc = "Selecting Pad: GPIO_AD_00 for Mode: ALT0"]
8132 pub const GPIO_AD_00_ALT0: u32 = 0;
8133 #[doc = "Selecting Pad: GPIO_SD_10 for Mode: ALT2"]
8134 pub const GPIO_SD_10_ALT2: u32 = 0x01;
8135 }
8136 }
8137}
8138#[doc = "LPUART3_RXD_SELECT_INPUT DAISY Register"]
8139pub mod LPUART3_RXD_SELECT_INPUT {
8140 #[doc = "Selecting Pads Involved in Daisy Chain."]
8141 pub mod DAISY {
8142 pub const offset: u32 = 0;
8143 pub const mask: u32 = 0x03 << offset;
8144 pub mod R {}
8145 pub mod W {}
8146 pub mod RW {
8147 #[doc = "Selecting Pad: GPIO_AD_07 for Mode: ALT1"]
8148 pub const GPIO_AD_07_ALT1: u32 = 0;
8149 #[doc = "Selecting Pad: GPIO_11 for Mode: ALT0"]
8150 pub const GPIO_11_ALT0: u32 = 0x01;
8151 #[doc = "Selecting Pad: GPIO_07 for Mode: ALT3"]
8152 pub const GPIO_07_ALT3: u32 = 0x02;
8153 }
8154 }
8155}
8156#[doc = "LPUART3_TXD_SELECT_INPUT DAISY Register"]
8157pub mod LPUART3_TXD_SELECT_INPUT {
8158 #[doc = "Selecting Pads Involved in Daisy Chain."]
8159 pub mod DAISY {
8160 pub const offset: u32 = 0;
8161 pub const mask: u32 = 0x03 << offset;
8162 pub mod R {}
8163 pub mod W {}
8164 pub mod RW {
8165 #[doc = "Selecting Pad: GPIO_AD_08 for Mode: ALT1"]
8166 pub const GPIO_AD_08_ALT1: u32 = 0;
8167 #[doc = "Selecting Pad: GPIO_12 for Mode: ALT0"]
8168 pub const GPIO_12_ALT0: u32 = 0x01;
8169 #[doc = "Selecting Pad: GPIO_08 for Mode: ALT3"]
8170 pub const GPIO_08_ALT3: u32 = 0x02;
8171 }
8172 }
8173}
8174#[doc = "LPUART4_RXD_SELECT_INPUT DAISY Register"]
8175pub mod LPUART4_RXD_SELECT_INPUT {
8176 #[doc = "Selecting Pads Involved in Daisy Chain."]
8177 pub mod DAISY {
8178 pub const offset: u32 = 0;
8179 pub const mask: u32 = 0x01 << offset;
8180 pub mod R {}
8181 pub mod W {}
8182 pub mod RW {
8183 #[doc = "Selecting Pad: GPIO_AD_01 for Mode: ALT0"]
8184 pub const GPIO_AD_01_ALT0: u32 = 0;
8185 #[doc = "Selecting Pad: GPIO_05 for Mode: ALT3"]
8186 pub const GPIO_05_ALT3: u32 = 0x01;
8187 }
8188 }
8189}
8190#[doc = "LPUART4_TXD_SELECT_INPUT DAISY Register"]
8191pub mod LPUART4_TXD_SELECT_INPUT {
8192 #[doc = "Selecting Pads Involved in Daisy Chain."]
8193 pub mod DAISY {
8194 pub const offset: u32 = 0;
8195 pub const mask: u32 = 0x01 << offset;
8196 pub mod R {}
8197 pub mod W {}
8198 pub mod RW {
8199 #[doc = "Selecting Pad: GPIO_AD_02 for Mode: ALT0"]
8200 pub const GPIO_AD_02_ALT0: u32 = 0;
8201 #[doc = "Selecting Pad: GPIO_06 for Mode: ALT3"]
8202 pub const GPIO_06_ALT3: u32 = 0x01;
8203 }
8204 }
8205}
8206#[doc = "NMI_GLUE_NMI_SELECT_INPUT DAISY Register"]
8207pub mod NMI_GLUE_NMI_SELECT_INPUT {
8208 #[doc = "Selecting Pads Involved in Daisy Chain."]
8209 pub mod DAISY {
8210 pub const offset: u32 = 0;
8211 pub const mask: u32 = 0x01 << offset;
8212 pub mod R {}
8213 pub mod W {}
8214 pub mod RW {
8215 #[doc = "Selecting Pad: GPIO_AD_13 for Mode: ALT6"]
8216 pub const GPIO_AD_13_ALT6: u32 = 0;
8217 #[doc = "Selecting Pad: GPIO_AD_00 for Mode: ALT6"]
8218 pub const GPIO_AD_00_ALT6: u32 = 0x01;
8219 }
8220 }
8221}
8222#[doc = "SPDIF_IN1_SELECT_INPUT DAISY Register"]
8223pub mod SPDIF_IN1_SELECT_INPUT {
8224 #[doc = "Selecting Pads Involved in Daisy Chain."]
8225 pub mod DAISY {
8226 pub const offset: u32 = 0;
8227 pub const mask: u32 = 0x01 << offset;
8228 pub mod R {}
8229 pub mod W {}
8230 pub mod RW {
8231 #[doc = "Selecting Pad: GPIO_10 for Mode: ALT6"]
8232 pub const GPIO_10_ALT6: u32 = 0;
8233 #[doc = "Selecting Pad: GPIO_04 for Mode: ALT4"]
8234 pub const GPIO_04_ALT4: u32 = 0x01;
8235 }
8236 }
8237}
8238#[doc = "SPDIF_TX_CLK2_SELECT_INPUT DAISY Register"]
8239pub mod SPDIF_TX_CLK2_SELECT_INPUT {
8240 #[doc = "Selecting Pads Involved in Daisy Chain."]
8241 pub mod DAISY {
8242 pub const offset: u32 = 0;
8243 pub const mask: u32 = 0x01 << offset;
8244 pub mod R {}
8245 pub mod W {}
8246 pub mod RW {
8247 #[doc = "Selecting Pad: GPIO_12 for Mode: ALT6"]
8248 pub const GPIO_12_ALT6: u32 = 0;
8249 #[doc = "Selecting Pad: GPIO_06 for Mode: ALT4"]
8250 pub const GPIO_06_ALT4: u32 = 0x01;
8251 }
8252 }
8253}
8254#[doc = "USB_OTG_OC_SELECT_INPUT DAISY Register"]
8255pub mod USB_OTG_OC_SELECT_INPUT {
8256 #[doc = "Selecting Pads Involved in Daisy Chain."]
8257 pub mod DAISY {
8258 pub const offset: u32 = 0;
8259 pub const mask: u32 = 0x01 << offset;
8260 pub mod R {}
8261 pub mod W {}
8262 pub mod RW {
8263 #[doc = "Selecting Pad: GPIO_AD_01 for Mode: ALT6"]
8264 pub const GPIO_AD_01_ALT6: u32 = 0;
8265 #[doc = "Selecting Pad: GPIO_12 for Mode: ALT3"]
8266 pub const GPIO_12_ALT3: u32 = 0x01;
8267 }
8268 }
8269}
8270#[doc = "XEV_GLUE_RXEV_SELECT_INPUT DAISY Register"]
8271pub mod XEV_GLUE_RXEV_SELECT_INPUT {
8272 #[doc = "Selecting Pads Involved in Daisy Chain."]
8273 pub mod DAISY {
8274 pub const offset: u32 = 0;
8275 pub const mask: u32 = 0x01 << offset;
8276 pub mod R {}
8277 pub mod W {}
8278 pub mod RW {
8279 #[doc = "Selecting Pad: GPIO_AD_07 for Mode: ALT2"]
8280 pub const GPIO_AD_07_ALT2: u32 = 0;
8281 #[doc = "Selecting Pad: GPIO_SD_00 for Mode: ALT2"]
8282 pub const GPIO_SD_00_ALT2: u32 = 0x01;
8283 }
8284 }
8285}