rp2040_pac/clocks/
clk_ref_div.rs

Help
1#[doc = "Register `CLK_REF_DIV` reader"]
2pub type R = crate::R<CLK_REF_DIV_SPEC>;
3#[doc = "Register `CLK_REF_DIV` writer"]
4pub type W = crate::W<CLK_REF_DIV_SPEC>;
5#[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"]
6pub type INT_R = crate::FieldReader;
7#[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"]
8pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9impl R {
10    #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"]
11    #[inline(always)]
12    pub fn int(&self) -> INT_R {
13        INT_R::new(((self.bits >> 8) & 3) as u8)
14    }
15}
16impl W {
17    #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"]
18    #[inline(always)]
19    #[must_use]
20    pub fn int(&mut self) -> INT_W<CLK_REF_DIV_SPEC> {
21        INT_W::new(self, 8)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "Clock divisor, can be changed on-the-fly  
35
36You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
37pub struct CLK_REF_DIV_SPEC;
38impl crate::RegisterSpec for CLK_REF_DIV_SPEC {
39    type Ux = u32;
40}
41#[doc = "`read()` method returns [`clk_ref_div::R`](R) reader structure"]
42impl crate::Readable for CLK_REF_DIV_SPEC {}
43#[doc = "`write(|w| ..)` method takes [`clk_ref_div::W`](W) writer structure"]
44impl crate::Writable for CLK_REF_DIV_SPEC {
45    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
46    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
47}
48#[doc = "`reset()` method sets CLK_REF_DIV to value 0x0100"]
49impl crate::Resettable for CLK_REF_DIV_SPEC {
50    const RESET_VALUE: u32 = 0x0100;
51}
rp2040_pac/clocks/clk_ref_div.rs

rp2040_pac/clocks/
clk_ref_div.rs
