rp2040_pac/i2c0/
ic_ss_scl_hcnt.rs

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1#[doc = "Register `IC_SS_SCL_HCNT` reader"]
2pub type R = crate::R<IC_SS_SCL_HCNT_SPEC>;
3#[doc = "Register `IC_SS_SCL_HCNT` writer"]
4pub type W = crate::W<IC_SS_SCL_HCNT_SPEC>;
5#[doc = "Field `IC_SS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.  
6
7 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
8register being set to 0. Writes at other times have no effect.  
9
10 The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.  
11
12 NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."]
13pub type IC_SS_SCL_HCNT_R = crate::FieldReader<u16>;
14#[doc = "Field `IC_SS_SCL_HCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.  
15
16 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
17register being set to 0. Writes at other times have no effect.  
18
19 The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.  
20
21 NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."]
22pub type IC_SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
23impl R {
24    #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.  
25
26 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
27register being set to 0. Writes at other times have no effect.  
28
29 The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.  
30
31 NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."]
32    #[inline(always)]
33    pub fn ic_ss_scl_hcnt(&self) -> IC_SS_SCL_HCNT_R {
34        IC_SS_SCL_HCNT_R::new((self.bits & 0xffff) as u16)
35    }
36}
37impl W {
38    #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.  
39
40 This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
41register being set to 0. Writes at other times have no effect.  
42
43 The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.  
44
45 NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."]
46    #[inline(always)]
47    #[must_use]
48    pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W<IC_SS_SCL_HCNT_SPEC> {
49        IC_SS_SCL_HCNT_W::new(self, 0)
50    }
51    #[doc = r" Writes raw bits to the register."]
52    #[doc = r""]
53    #[doc = r" # Safety"]
54    #[doc = r""]
55    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
58        self.bits = bits;
59        self
60    }
61}
62#[doc = "Standard Speed I2C Clock SCL High Count Register  
63
64You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_hcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct IC_SS_SCL_HCNT_SPEC;
66impl crate::RegisterSpec for IC_SS_SCL_HCNT_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`ic_ss_scl_hcnt::R`](R) reader structure"]
70impl crate::Readable for IC_SS_SCL_HCNT_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`ic_ss_scl_hcnt::W`](W) writer structure"]
72impl crate::Writable for IC_SS_SCL_HCNT_SPEC {
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75}
76#[doc = "`reset()` method sets IC_SS_SCL_HCNT to value 0x28"]
77impl crate::Resettable for IC_SS_SCL_HCNT_SPEC {
78    const RESET_VALUE: u32 = 0x28;
79}
rp2040_pac/i2c0/ic_ss_scl_hcnt.rs

rp2040_pac/i2c0/
ic_ss_scl_hcnt.rs
