rp2040_pac/clocks/
wake_en0.rs

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1#[doc = "Register `WAKE_EN0` reader"]
2pub type R = crate::R<WAKE_EN0_SPEC>;
3#[doc = "Register `WAKE_EN0` writer"]
4pub type W = crate::W<WAKE_EN0_SPEC>;
5#[doc = "Field `clk_sys_clocks` reader - "]
6pub type CLK_SYS_CLOCKS_R = crate::BitReader;
7#[doc = "Field `clk_sys_clocks` writer - "]
8pub type CLK_SYS_CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `clk_adc_adc` reader - "]
10pub type CLK_ADC_ADC_R = crate::BitReader;
11#[doc = "Field `clk_adc_adc` writer - "]
12pub type CLK_ADC_ADC_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `clk_sys_adc` reader - "]
14pub type CLK_SYS_ADC_R = crate::BitReader;
15#[doc = "Field `clk_sys_adc` writer - "]
16pub type CLK_SYS_ADC_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `clk_sys_busctrl` reader - "]
18pub type CLK_SYS_BUSCTRL_R = crate::BitReader;
19#[doc = "Field `clk_sys_busctrl` writer - "]
20pub type CLK_SYS_BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `clk_sys_busfabric` reader - "]
22pub type CLK_SYS_BUSFABRIC_R = crate::BitReader;
23#[doc = "Field `clk_sys_busfabric` writer - "]
24pub type CLK_SYS_BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `clk_sys_dma` reader - "]
26pub type CLK_SYS_DMA_R = crate::BitReader;
27#[doc = "Field `clk_sys_dma` writer - "]
28pub type CLK_SYS_DMA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `clk_sys_i2c0` reader - "]
30pub type CLK_SYS_I2C0_R = crate::BitReader;
31#[doc = "Field `clk_sys_i2c0` writer - "]
32pub type CLK_SYS_I2C0_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `clk_sys_i2c1` reader - "]
34pub type CLK_SYS_I2C1_R = crate::BitReader;
35#[doc = "Field `clk_sys_i2c1` writer - "]
36pub type CLK_SYS_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `clk_sys_io` reader - "]
38pub type CLK_SYS_IO_R = crate::BitReader;
39#[doc = "Field `clk_sys_io` writer - "]
40pub type CLK_SYS_IO_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `clk_sys_jtag` reader - "]
42pub type CLK_SYS_JTAG_R = crate::BitReader;
43#[doc = "Field `clk_sys_jtag` writer - "]
44pub type CLK_SYS_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "]
46pub type CLK_SYS_VREG_AND_CHIP_RESET_R = crate::BitReader;
47#[doc = "Field `clk_sys_vreg_and_chip_reset` writer - "]
48pub type CLK_SYS_VREG_AND_CHIP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `clk_sys_pads` reader - "]
50pub type CLK_SYS_PADS_R = crate::BitReader;
51#[doc = "Field `clk_sys_pads` writer - "]
52pub type CLK_SYS_PADS_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `clk_sys_pio0` reader - "]
54pub type CLK_SYS_PIO0_R = crate::BitReader;
55#[doc = "Field `clk_sys_pio0` writer - "]
56pub type CLK_SYS_PIO0_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `clk_sys_pio1` reader - "]
58pub type CLK_SYS_PIO1_R = crate::BitReader;
59#[doc = "Field `clk_sys_pio1` writer - "]
60pub type CLK_SYS_PIO1_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `clk_sys_pll_sys` reader - "]
62pub type CLK_SYS_PLL_SYS_R = crate::BitReader;
63#[doc = "Field `clk_sys_pll_sys` writer - "]
64pub type CLK_SYS_PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `clk_sys_pll_usb` reader - "]
66pub type CLK_SYS_PLL_USB_R = crate::BitReader;
67#[doc = "Field `clk_sys_pll_usb` writer - "]
68pub type CLK_SYS_PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `clk_sys_psm` reader - "]
70pub type CLK_SYS_PSM_R = crate::BitReader;
71#[doc = "Field `clk_sys_psm` writer - "]
72pub type CLK_SYS_PSM_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `clk_sys_pwm` reader - "]
74pub type CLK_SYS_PWM_R = crate::BitReader;
75#[doc = "Field `clk_sys_pwm` writer - "]
76pub type CLK_SYS_PWM_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `clk_sys_resets` reader - "]
78pub type CLK_SYS_RESETS_R = crate::BitReader;
79#[doc = "Field `clk_sys_resets` writer - "]
80pub type CLK_SYS_RESETS_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `clk_sys_rom` reader - "]
82pub type CLK_SYS_ROM_R = crate::BitReader;
83#[doc = "Field `clk_sys_rom` writer - "]
84pub type CLK_SYS_ROM_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `clk_sys_rosc` reader - "]
86pub type CLK_SYS_ROSC_R = crate::BitReader;
87#[doc = "Field `clk_sys_rosc` writer - "]
88pub type CLK_SYS_ROSC_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `clk_rtc_rtc` reader - "]
90pub type CLK_RTC_RTC_R = crate::BitReader;
91#[doc = "Field `clk_rtc_rtc` writer - "]
92pub type CLK_RTC_RTC_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `clk_sys_rtc` reader - "]
94pub type CLK_SYS_RTC_R = crate::BitReader;
95#[doc = "Field `clk_sys_rtc` writer - "]
96pub type CLK_SYS_RTC_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `clk_sys_sio` reader - "]
98pub type CLK_SYS_SIO_R = crate::BitReader;
99#[doc = "Field `clk_sys_sio` writer - "]
100pub type CLK_SYS_SIO_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `clk_peri_spi0` reader - "]
102pub type CLK_PERI_SPI0_R = crate::BitReader;
103#[doc = "Field `clk_peri_spi0` writer - "]
104pub type CLK_PERI_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `clk_sys_spi0` reader - "]
106pub type CLK_SYS_SPI0_R = crate::BitReader;
107#[doc = "Field `clk_sys_spi0` writer - "]
108pub type CLK_SYS_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `clk_peri_spi1` reader - "]
110pub type CLK_PERI_SPI1_R = crate::BitReader;
111#[doc = "Field `clk_peri_spi1` writer - "]
112pub type CLK_PERI_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `clk_sys_spi1` reader - "]
114pub type CLK_SYS_SPI1_R = crate::BitReader;
115#[doc = "Field `clk_sys_spi1` writer - "]
116pub type CLK_SYS_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `clk_sys_sram0` reader - "]
118pub type CLK_SYS_SRAM0_R = crate::BitReader;
119#[doc = "Field `clk_sys_sram0` writer - "]
120pub type CLK_SYS_SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `clk_sys_sram1` reader - "]
122pub type CLK_SYS_SRAM1_R = crate::BitReader;
123#[doc = "Field `clk_sys_sram1` writer - "]
124pub type CLK_SYS_SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>;
125#[doc = "Field `clk_sys_sram2` reader - "]
126pub type CLK_SYS_SRAM2_R = crate::BitReader;
127#[doc = "Field `clk_sys_sram2` writer - "]
128pub type CLK_SYS_SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>;
129#[doc = "Field `clk_sys_sram3` reader - "]
130pub type CLK_SYS_SRAM3_R = crate::BitReader;
131#[doc = "Field `clk_sys_sram3` writer - "]
132pub type CLK_SYS_SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>;
133impl R {
134    #[doc = "Bit 0"]
135    #[inline(always)]
136    pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R {
137        CLK_SYS_CLOCKS_R::new((self.bits & 1) != 0)
138    }
139    #[doc = "Bit 1"]
140    #[inline(always)]
141    pub fn clk_adc_adc(&self) -> CLK_ADC_ADC_R {
142        CLK_ADC_ADC_R::new(((self.bits >> 1) & 1) != 0)
143    }
144    #[doc = "Bit 2"]
145    #[inline(always)]
146    pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R {
147        CLK_SYS_ADC_R::new(((self.bits >> 2) & 1) != 0)
148    }
149    #[doc = "Bit 3"]
150    #[inline(always)]
151    pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R {
152        CLK_SYS_BUSCTRL_R::new(((self.bits >> 3) & 1) != 0)
153    }
154    #[doc = "Bit 4"]
155    #[inline(always)]
156    pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R {
157        CLK_SYS_BUSFABRIC_R::new(((self.bits >> 4) & 1) != 0)
158    }
159    #[doc = "Bit 5"]
160    #[inline(always)]
161    pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R {
162        CLK_SYS_DMA_R::new(((self.bits >> 5) & 1) != 0)
163    }
164    #[doc = "Bit 6"]
165    #[inline(always)]
166    pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R {
167        CLK_SYS_I2C0_R::new(((self.bits >> 6) & 1) != 0)
168    }
169    #[doc = "Bit 7"]
170    #[inline(always)]
171    pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R {
172        CLK_SYS_I2C1_R::new(((self.bits >> 7) & 1) != 0)
173    }
174    #[doc = "Bit 8"]
175    #[inline(always)]
176    pub fn clk_sys_io(&self) -> CLK_SYS_IO_R {
177        CLK_SYS_IO_R::new(((self.bits >> 8) & 1) != 0)
178    }
179    #[doc = "Bit 9"]
180    #[inline(always)]
181    pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R {
182        CLK_SYS_JTAG_R::new(((self.bits >> 9) & 1) != 0)
183    }
184    #[doc = "Bit 10"]
185    #[inline(always)]
186    pub fn clk_sys_vreg_and_chip_reset(&self) -> CLK_SYS_VREG_AND_CHIP_RESET_R {
187        CLK_SYS_VREG_AND_CHIP_RESET_R::new(((self.bits >> 10) & 1) != 0)
188    }
189    #[doc = "Bit 11"]
190    #[inline(always)]
191    pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R {
192        CLK_SYS_PADS_R::new(((self.bits >> 11) & 1) != 0)
193    }
194    #[doc = "Bit 12"]
195    #[inline(always)]
196    pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R {
197        CLK_SYS_PIO0_R::new(((self.bits >> 12) & 1) != 0)
198    }
199    #[doc = "Bit 13"]
200    #[inline(always)]
201    pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R {
202        CLK_SYS_PIO1_R::new(((self.bits >> 13) & 1) != 0)
203    }
204    #[doc = "Bit 14"]
205    #[inline(always)]
206    pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R {
207        CLK_SYS_PLL_SYS_R::new(((self.bits >> 14) & 1) != 0)
208    }
209    #[doc = "Bit 15"]
210    #[inline(always)]
211    pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R {
212        CLK_SYS_PLL_USB_R::new(((self.bits >> 15) & 1) != 0)
213    }
214    #[doc = "Bit 16"]
215    #[inline(always)]
216    pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R {
217        CLK_SYS_PSM_R::new(((self.bits >> 16) & 1) != 0)
218    }
219    #[doc = "Bit 17"]
220    #[inline(always)]
221    pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R {
222        CLK_SYS_PWM_R::new(((self.bits >> 17) & 1) != 0)
223    }
224    #[doc = "Bit 18"]
225    #[inline(always)]
226    pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R {
227        CLK_SYS_RESETS_R::new(((self.bits >> 18) & 1) != 0)
228    }
229    #[doc = "Bit 19"]
230    #[inline(always)]
231    pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R {
232        CLK_SYS_ROM_R::new(((self.bits >> 19) & 1) != 0)
233    }
234    #[doc = "Bit 20"]
235    #[inline(always)]
236    pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R {
237        CLK_SYS_ROSC_R::new(((self.bits >> 20) & 1) != 0)
238    }
239    #[doc = "Bit 21"]
240    #[inline(always)]
241    pub fn clk_rtc_rtc(&self) -> CLK_RTC_RTC_R {
242        CLK_RTC_RTC_R::new(((self.bits >> 21) & 1) != 0)
243    }
244    #[doc = "Bit 22"]
245    #[inline(always)]
246    pub fn clk_sys_rtc(&self) -> CLK_SYS_RTC_R {
247        CLK_SYS_RTC_R::new(((self.bits >> 22) & 1) != 0)
248    }
249    #[doc = "Bit 23"]
250    #[inline(always)]
251    pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R {
252        CLK_SYS_SIO_R::new(((self.bits >> 23) & 1) != 0)
253    }
254    #[doc = "Bit 24"]
255    #[inline(always)]
256    pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R {
257        CLK_PERI_SPI0_R::new(((self.bits >> 24) & 1) != 0)
258    }
259    #[doc = "Bit 25"]
260    #[inline(always)]
261    pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R {
262        CLK_SYS_SPI0_R::new(((self.bits >> 25) & 1) != 0)
263    }
264    #[doc = "Bit 26"]
265    #[inline(always)]
266    pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R {
267        CLK_PERI_SPI1_R::new(((self.bits >> 26) & 1) != 0)
268    }
269    #[doc = "Bit 27"]
270    #[inline(always)]
271    pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R {
272        CLK_SYS_SPI1_R::new(((self.bits >> 27) & 1) != 0)
273    }
274    #[doc = "Bit 28"]
275    #[inline(always)]
276    pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R {
277        CLK_SYS_SRAM0_R::new(((self.bits >> 28) & 1) != 0)
278    }
279    #[doc = "Bit 29"]
280    #[inline(always)]
281    pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R {
282        CLK_SYS_SRAM1_R::new(((self.bits >> 29) & 1) != 0)
283    }
284    #[doc = "Bit 30"]
285    #[inline(always)]
286    pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R {
287        CLK_SYS_SRAM2_R::new(((self.bits >> 30) & 1) != 0)
288    }
289    #[doc = "Bit 31"]
290    #[inline(always)]
291    pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R {
292        CLK_SYS_SRAM3_R::new(((self.bits >> 31) & 1) != 0)
293    }
294}
295impl W {
296    #[doc = "Bit 0"]
297    #[inline(always)]
298    #[must_use]
299    pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W<WAKE_EN0_SPEC> {
300        CLK_SYS_CLOCKS_W::new(self, 0)
301    }
302    #[doc = "Bit 1"]
303    #[inline(always)]
304    #[must_use]
305    pub fn clk_adc_adc(&mut self) -> CLK_ADC_ADC_W<WAKE_EN0_SPEC> {
306        CLK_ADC_ADC_W::new(self, 1)
307    }
308    #[doc = "Bit 2"]
309    #[inline(always)]
310    #[must_use]
311    pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W<WAKE_EN0_SPEC> {
312        CLK_SYS_ADC_W::new(self, 2)
313    }
314    #[doc = "Bit 3"]
315    #[inline(always)]
316    #[must_use]
317    pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W<WAKE_EN0_SPEC> {
318        CLK_SYS_BUSCTRL_W::new(self, 3)
319    }
320    #[doc = "Bit 4"]
321    #[inline(always)]
322    #[must_use]
323    pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W<WAKE_EN0_SPEC> {
324        CLK_SYS_BUSFABRIC_W::new(self, 4)
325    }
326    #[doc = "Bit 5"]
327    #[inline(always)]
328    #[must_use]
329    pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W<WAKE_EN0_SPEC> {
330        CLK_SYS_DMA_W::new(self, 5)
331    }
332    #[doc = "Bit 6"]
333    #[inline(always)]
334    #[must_use]
335    pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W<WAKE_EN0_SPEC> {
336        CLK_SYS_I2C0_W::new(self, 6)
337    }
338    #[doc = "Bit 7"]
339    #[inline(always)]
340    #[must_use]
341    pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W<WAKE_EN0_SPEC> {
342        CLK_SYS_I2C1_W::new(self, 7)
343    }
344    #[doc = "Bit 8"]
345    #[inline(always)]
346    #[must_use]
347    pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W<WAKE_EN0_SPEC> {
348        CLK_SYS_IO_W::new(self, 8)
349    }
350    #[doc = "Bit 9"]
351    #[inline(always)]
352    #[must_use]
353    pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W<WAKE_EN0_SPEC> {
354        CLK_SYS_JTAG_W::new(self, 9)
355    }
356    #[doc = "Bit 10"]
357    #[inline(always)]
358    #[must_use]
359    pub fn clk_sys_vreg_and_chip_reset(&mut self) -> CLK_SYS_VREG_AND_CHIP_RESET_W<WAKE_EN0_SPEC> {
360        CLK_SYS_VREG_AND_CHIP_RESET_W::new(self, 10)
361    }
362    #[doc = "Bit 11"]
363    #[inline(always)]
364    #[must_use]
365    pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W<WAKE_EN0_SPEC> {
366        CLK_SYS_PADS_W::new(self, 11)
367    }
368    #[doc = "Bit 12"]
369    #[inline(always)]
370    #[must_use]
371    pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W<WAKE_EN0_SPEC> {
372        CLK_SYS_PIO0_W::new(self, 12)
373    }
374    #[doc = "Bit 13"]
375    #[inline(always)]
376    #[must_use]
377    pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W<WAKE_EN0_SPEC> {
378        CLK_SYS_PIO1_W::new(self, 13)
379    }
380    #[doc = "Bit 14"]
381    #[inline(always)]
382    #[must_use]
383    pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W<WAKE_EN0_SPEC> {
384        CLK_SYS_PLL_SYS_W::new(self, 14)
385    }
386    #[doc = "Bit 15"]
387    #[inline(always)]
388    #[must_use]
389    pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W<WAKE_EN0_SPEC> {
390        CLK_SYS_PLL_USB_W::new(self, 15)
391    }
392    #[doc = "Bit 16"]
393    #[inline(always)]
394    #[must_use]
395    pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W<WAKE_EN0_SPEC> {
396        CLK_SYS_PSM_W::new(self, 16)
397    }
398    #[doc = "Bit 17"]
399    #[inline(always)]
400    #[must_use]
401    pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W<WAKE_EN0_SPEC> {
402        CLK_SYS_PWM_W::new(self, 17)
403    }
404    #[doc = "Bit 18"]
405    #[inline(always)]
406    #[must_use]
407    pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W<WAKE_EN0_SPEC> {
408        CLK_SYS_RESETS_W::new(self, 18)
409    }
410    #[doc = "Bit 19"]
411    #[inline(always)]
412    #[must_use]
413    pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W<WAKE_EN0_SPEC> {
414        CLK_SYS_ROM_W::new(self, 19)
415    }
416    #[doc = "Bit 20"]
417    #[inline(always)]
418    #[must_use]
419    pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W<WAKE_EN0_SPEC> {
420        CLK_SYS_ROSC_W::new(self, 20)
421    }
422    #[doc = "Bit 21"]
423    #[inline(always)]
424    #[must_use]
425    pub fn clk_rtc_rtc(&mut self) -> CLK_RTC_RTC_W<WAKE_EN0_SPEC> {
426        CLK_RTC_RTC_W::new(self, 21)
427    }
428    #[doc = "Bit 22"]
429    #[inline(always)]
430    #[must_use]
431    pub fn clk_sys_rtc(&mut self) -> CLK_SYS_RTC_W<WAKE_EN0_SPEC> {
432        CLK_SYS_RTC_W::new(self, 22)
433    }
434    #[doc = "Bit 23"]
435    #[inline(always)]
436    #[must_use]
437    pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W<WAKE_EN0_SPEC> {
438        CLK_SYS_SIO_W::new(self, 23)
439    }
440    #[doc = "Bit 24"]
441    #[inline(always)]
442    #[must_use]
443    pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W<WAKE_EN0_SPEC> {
444        CLK_PERI_SPI0_W::new(self, 24)
445    }
446    #[doc = "Bit 25"]
447    #[inline(always)]
448    #[must_use]
449    pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W<WAKE_EN0_SPEC> {
450        CLK_SYS_SPI0_W::new(self, 25)
451    }
452    #[doc = "Bit 26"]
453    #[inline(always)]
454    #[must_use]
455    pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W<WAKE_EN0_SPEC> {
456        CLK_PERI_SPI1_W::new(self, 26)
457    }
458    #[doc = "Bit 27"]
459    #[inline(always)]
460    #[must_use]
461    pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W<WAKE_EN0_SPEC> {
462        CLK_SYS_SPI1_W::new(self, 27)
463    }
464    #[doc = "Bit 28"]
465    #[inline(always)]
466    #[must_use]
467    pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W<WAKE_EN0_SPEC> {
468        CLK_SYS_SRAM0_W::new(self, 28)
469    }
470    #[doc = "Bit 29"]
471    #[inline(always)]
472    #[must_use]
473    pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W<WAKE_EN0_SPEC> {
474        CLK_SYS_SRAM1_W::new(self, 29)
475    }
476    #[doc = "Bit 30"]
477    #[inline(always)]
478    #[must_use]
479    pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W<WAKE_EN0_SPEC> {
480        CLK_SYS_SRAM2_W::new(self, 30)
481    }
482    #[doc = "Bit 31"]
483    #[inline(always)]
484    #[must_use]
485    pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W<WAKE_EN0_SPEC> {
486        CLK_SYS_SRAM3_W::new(self, 31)
487    }
488    #[doc = r" Writes raw bits to the register."]
489    #[doc = r""]
490    #[doc = r" # Safety"]
491    #[doc = r""]
492    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
493    #[inline(always)]
494    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
495        self.bits = bits;
496        self
497    }
498}
499#[doc = "enable clock in wake mode  
500
501You can [`read`](crate::generic::Reg::read) this register and get [`wake_en0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
502pub struct WAKE_EN0_SPEC;
503impl crate::RegisterSpec for WAKE_EN0_SPEC {
504    type Ux = u32;
505}
506#[doc = "`read()` method returns [`wake_en0::R`](R) reader structure"]
507impl crate::Readable for WAKE_EN0_SPEC {}
508#[doc = "`write(|w| ..)` method takes [`wake_en0::W`](W) writer structure"]
509impl crate::Writable for WAKE_EN0_SPEC {
510    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
511    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
512}
513#[doc = "`reset()` method sets WAKE_EN0 to value 0xffff_ffff"]
514impl crate::Resettable for WAKE_EN0_SPEC {
515    const RESET_VALUE: u32 = 0xffff_ffff;
516}
rp2040_pac/clocks/wake_en0.rs

rp2040_pac/clocks/
wake_en0.rs
