rp2040_pac/sio/
interp0_ctrl_lane0.rs

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1#[doc = "Register `INTERP0_CTRL_LANE0` reader"]
2pub type R = crate::R<INTERP0_CTRL_LANE0_SPEC>;
3#[doc = "Register `INTERP0_CTRL_LANE0` writer"]
4pub type W = crate::W<INTERP0_CTRL_LANE0_SPEC>;
5#[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"]
6pub type SHIFT_R = crate::FieldReader;
7#[doc = "Field `SHIFT` writer - Logical right-shift applied to accumulator before masking"]
8pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"]
10pub type MASK_LSB_R = crate::FieldReader;
11#[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"]
12pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive)  
14 Setting MSB &lt; LSB may cause chip to turn inside-out"]
15pub type MASK_MSB_R = crate::FieldReader;
16#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive)  
17 Setting MSB &lt; LSB may cause chip to turn inside-out"]
18pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
19#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
20 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
21pub type SIGNED_R = crate::BitReader;
22#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
23 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
24pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
26 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
27pub type CROSS_INPUT_R = crate::BitReader;
28#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
29 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
30pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
32pub type CROSS_RESULT_R = crate::BitReader;
33#[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
34pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
36pub type ADD_RAW_R = crate::BitReader;
37#[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
38pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
40 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
41 of pointers into flash or SRAM."]
42pub type FORCE_MSB_R = crate::FieldReader;
43#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
44 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
45 of pointers into flash or SRAM."]
46pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
47#[doc = "Field `BLEND` reader - Only present on INTERP0 on each core. If BLEND mode is enabled:  
48 - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled  
49 by the 8 LSBs of lane 1 shift and mask value (a fractional number between  
50 0 and 255/256ths)  
51 - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)  
52 - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)  
53 LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."]
54pub type BLEND_R = crate::BitReader;
55#[doc = "Field `BLEND` writer - Only present on INTERP0 on each core. If BLEND mode is enabled:  
56 - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled  
57 by the 8 LSBs of lane 1 shift and mask value (a fractional number between  
58 0 and 255/256ths)  
59 - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)  
60 - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)  
61 LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."]
62pub type BLEND_W<'a, REG> = crate::BitWriter<'a, REG>;
63#[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."]
64pub type OVERF0_R = crate::BitReader;
65#[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."]
66pub type OVERF1_R = crate::BitReader;
67#[doc = "Field `OVERF` reader - Set if either OVERF0 or OVERF1 is set."]
68pub type OVERF_R = crate::BitReader;
69impl R {
70    #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"]
71    #[inline(always)]
72    pub fn shift(&self) -> SHIFT_R {
73        SHIFT_R::new((self.bits & 0x1f) as u8)
74    }
75    #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
76    #[inline(always)]
77    pub fn mask_lsb(&self) -> MASK_LSB_R {
78        MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8)
79    }
80    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)  
81 Setting MSB &lt; LSB may cause chip to turn inside-out"]
82    #[inline(always)]
83    pub fn mask_msb(&self) -> MASK_MSB_R {
84        MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8)
85    }
86    #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
87 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
88    #[inline(always)]
89    pub fn signed(&self) -> SIGNED_R {
90        SIGNED_R::new(((self.bits >> 15) & 1) != 0)
91    }
92    #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
93 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
94    #[inline(always)]
95    pub fn cross_input(&self) -> CROSS_INPUT_R {
96        CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0)
97    }
98    #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
99    #[inline(always)]
100    pub fn cross_result(&self) -> CROSS_RESULT_R {
101        CROSS_RESULT_R::new(((self.bits >> 17) & 1) != 0)
102    }
103    #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
104    #[inline(always)]
105    pub fn add_raw(&self) -> ADD_RAW_R {
106        ADD_RAW_R::new(((self.bits >> 18) & 1) != 0)
107    }
108    #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
109 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
110 of pointers into flash or SRAM."]
111    #[inline(always)]
112    pub fn force_msb(&self) -> FORCE_MSB_R {
113        FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8)
114    }
115    #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled:  
116 - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled  
117 by the 8 LSBs of lane 1 shift and mask value (a fractional number between  
118 0 and 255/256ths)  
119 - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)  
120 - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)  
121 LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."]
122    #[inline(always)]
123    pub fn blend(&self) -> BLEND_R {
124        BLEND_R::new(((self.bits >> 21) & 1) != 0)
125    }
126    #[doc = "Bit 23 - Indicates if any masked-off MSBs in ACCUM0 are set."]
127    #[inline(always)]
128    pub fn overf0(&self) -> OVERF0_R {
129        OVERF0_R::new(((self.bits >> 23) & 1) != 0)
130    }
131    #[doc = "Bit 24 - Indicates if any masked-off MSBs in ACCUM1 are set."]
132    #[inline(always)]
133    pub fn overf1(&self) -> OVERF1_R {
134        OVERF1_R::new(((self.bits >> 24) & 1) != 0)
135    }
136    #[doc = "Bit 25 - Set if either OVERF0 or OVERF1 is set."]
137    #[inline(always)]
138    pub fn overf(&self) -> OVERF_R {
139        OVERF_R::new(((self.bits >> 25) & 1) != 0)
140    }
141}
142impl W {
143    #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"]
144    #[inline(always)]
145    #[must_use]
146    pub fn shift(&mut self) -> SHIFT_W<INTERP0_CTRL_LANE0_SPEC> {
147        SHIFT_W::new(self, 0)
148    }
149    #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
150    #[inline(always)]
151    #[must_use]
152    pub fn mask_lsb(&mut self) -> MASK_LSB_W<INTERP0_CTRL_LANE0_SPEC> {
153        MASK_LSB_W::new(self, 5)
154    }
155    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)  
156 Setting MSB &lt; LSB may cause chip to turn inside-out"]
157    #[inline(always)]
158    #[must_use]
159    pub fn mask_msb(&mut self) -> MASK_MSB_W<INTERP0_CTRL_LANE0_SPEC> {
160        MASK_MSB_W::new(self, 10)
161    }
162    #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits  
163 before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
164    #[inline(always)]
165    #[must_use]
166    pub fn signed(&mut self) -> SIGNED_W<INTERP0_CTRL_LANE0_SPEC> {
167        SIGNED_W::new(self, 15)
168    }
169    #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.  
170 Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
171    #[inline(always)]
172    #[must_use]
173    pub fn cross_input(&mut self) -> CROSS_INPUT_W<INTERP0_CTRL_LANE0_SPEC> {
174        CROSS_INPUT_W::new(self, 16)
175    }
176    #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
177    #[inline(always)]
178    #[must_use]
179    pub fn cross_result(&mut self) -> CROSS_RESULT_W<INTERP0_CTRL_LANE0_SPEC> {
180        CROSS_RESULT_W::new(self, 17)
181    }
182    #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
183    #[inline(always)]
184    #[must_use]
185    pub fn add_raw(&mut self) -> ADD_RAW_W<INTERP0_CTRL_LANE0_SPEC> {
186        ADD_RAW_W::new(self, 18)
187    }
188    #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.  
189 No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence  
190 of pointers into flash or SRAM."]
191    #[inline(always)]
192    #[must_use]
193    pub fn force_msb(&mut self) -> FORCE_MSB_W<INTERP0_CTRL_LANE0_SPEC> {
194        FORCE_MSB_W::new(self, 19)
195    }
196    #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled:  
197 - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled  
198 by the 8 LSBs of lane 1 shift and mask value (a fractional number between  
199 0 and 255/256ths)  
200 - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)  
201 - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)  
202 LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."]
203    #[inline(always)]
204    #[must_use]
205    pub fn blend(&mut self) -> BLEND_W<INTERP0_CTRL_LANE0_SPEC> {
206        BLEND_W::new(self, 21)
207    }
208    #[doc = r" Writes raw bits to the register."]
209    #[doc = r""]
210    #[doc = r" # Safety"]
211    #[doc = r""]
212    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
213    #[inline(always)]
214    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
215        self.bits = bits;
216        self
217    }
218}
219#[doc = "Control register for lane 0  
220
221You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
222pub struct INTERP0_CTRL_LANE0_SPEC;
223impl crate::RegisterSpec for INTERP0_CTRL_LANE0_SPEC {
224    type Ux = u32;
225}
226#[doc = "`read()` method returns [`interp0_ctrl_lane0::R`](R) reader structure"]
227impl crate::Readable for INTERP0_CTRL_LANE0_SPEC {}
228#[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane0::W`](W) writer structure"]
229impl crate::Writable for INTERP0_CTRL_LANE0_SPEC {
230    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
231    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
232}
233#[doc = "`reset()` method sets INTERP0_CTRL_LANE0 to value 0"]
234impl crate::Resettable for INTERP0_CTRL_LANE0_SPEC {
235    const RESET_VALUE: u32 = 0;
236}
rp2040_pac/sio/interp0_ctrl_lane0.rs

rp2040_pac/sio/
interp0_ctrl_lane0.rs
