imxrt_ral/blocks/imxrt1011/
usb.rs

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1#[doc = "USB"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Identification register"]
5    pub ID: crate::RORegister<u32>,
6    #[doc = "Hardware General"]
7    pub HWGENERAL: crate::RORegister<u32>,
8    #[doc = "Host Hardware Parameters"]
9    pub HWHOST: crate::RORegister<u32>,
10    #[doc = "Device Hardware Parameters"]
11    pub HWDEVICE: crate::RORegister<u32>,
12    #[doc = "TX Buffer Hardware Parameters"]
13    pub HWTXBUF: crate::RORegister<u32>,
14    #[doc = "RX Buffer Hardware Parameters"]
15    pub HWRXBUF: crate::RORegister<u32>,
16    _reserved0: [u8; 0x68],
17    #[doc = "General Purpose Timer #0 Load"]
18    pub GPTIMER0LD: crate::RWRegister<u32>,
19    #[doc = "General Purpose Timer #0 Controller"]
20    pub GPTIMER0CTRL: crate::RWRegister<u32>,
21    #[doc = "General Purpose Timer #1 Load"]
22    pub GPTIMER1LD: crate::RWRegister<u32>,
23    #[doc = "General Purpose Timer #1 Controller"]
24    pub GPTIMER1CTRL: crate::RWRegister<u32>,
25    #[doc = "System Bus Config"]
26    pub SBUSCFG: crate::RWRegister<u32>,
27    _reserved1: [u8; 0x6c],
28    #[doc = "Capability Registers Length"]
29    pub CAPLENGTH: crate::RORegister<u8>,
30    _reserved2: [u8; 0x01],
31    #[doc = "Host Controller Interface Version"]
32    pub HCIVERSION: crate::RORegister<u16>,
33    #[doc = "Host Controller Structural Parameters"]
34    pub HCSPARAMS: crate::RORegister<u32>,
35    #[doc = "Host Controller Capability Parameters"]
36    pub HCCPARAMS: crate::RORegister<u32>,
37    _reserved3: [u8; 0x14],
38    #[doc = "Device Controller Interface Version"]
39    pub DCIVERSION: crate::RORegister<u16>,
40    _reserved4: [u8; 0x02],
41    #[doc = "Device Controller Capability Parameters"]
42    pub DCCPARAMS: crate::RORegister<u32>,
43    _reserved5: [u8; 0x18],
44    #[doc = "USB Command Register"]
45    pub USBCMD: crate::RWRegister<u32>,
46    #[doc = "USB Status Register"]
47    pub USBSTS: crate::RWRegister<u32>,
48    #[doc = "Interrupt Enable Register"]
49    pub USBINTR: crate::RWRegister<u32>,
50    #[doc = "USB Frame Index"]
51    pub FRINDEX: crate::RWRegister<u32>,
52    _reserved6: [u8; 0x04],
53    #[doc = "Device Address"]
54    pub DEVICEADDR: crate::RWRegister<u32>,
55    #[doc = "Next Asynch. Address"]
56    pub ASYNCLISTADDR: crate::RWRegister<u32>,
57    _reserved7: [u8; 0x04],
58    #[doc = "Programmable Burst Size"]
59    pub BURSTSIZE: crate::RWRegister<u32>,
60    #[doc = "TX FIFO Fill Tuning"]
61    pub TXFILLTUNING: crate::RWRegister<u32>,
62    _reserved8: [u8; 0x10],
63    #[doc = "Endpoint NAK"]
64    pub ENDPTNAK: crate::RWRegister<u32>,
65    #[doc = "Endpoint NAK Enable"]
66    pub ENDPTNAKEN: crate::RWRegister<u32>,
67    #[doc = "Configure Flag Register"]
68    pub CONFIGFLAG: crate::RORegister<u32>,
69    #[doc = "Port Status & Control"]
70    pub PORTSC1: crate::RWRegister<u32>,
71    _reserved9: [u8; 0x1c],
72    #[doc = "On-The-Go Status & control"]
73    pub OTGSC: crate::RWRegister<u32>,
74    #[doc = "USB Device Mode"]
75    pub USBMODE: crate::RWRegister<u32>,
76    #[doc = "Endpoint Setup Status"]
77    pub ENDPTSETUPSTAT: crate::RWRegister<u32>,
78    #[doc = "Endpoint Prime"]
79    pub ENDPTPRIME: crate::RWRegister<u32>,
80    #[doc = "Endpoint Flush"]
81    pub ENDPTFLUSH: crate::RWRegister<u32>,
82    #[doc = "Endpoint Status"]
83    pub ENDPTSTAT: crate::RWRegister<u32>,
84    #[doc = "Endpoint Complete"]
85    pub ENDPTCOMPLETE: crate::RWRegister<u32>,
86    #[doc = "Endpoint Control0"]
87    pub ENDPTCTRL0: crate::RWRegister<u32>,
88    #[doc = "Endpoint Control"]
89    pub ENDPTCTRL: [crate::RWRegister<u32>; 7usize],
90}
91#[doc = "Identification register"]
92pub mod ID {
93    #[doc = "Configuration number"]
94    pub mod ID {
95        pub const offset: u32 = 0;
96        pub const mask: u32 = 0x3f << offset;
97        pub mod R {}
98        pub mod W {}
99        pub mod RW {}
100    }
101    #[doc = "Complement version of ID"]
102    pub mod NID {
103        pub const offset: u32 = 8;
104        pub const mask: u32 = 0x3f << offset;
105        pub mod R {}
106        pub mod W {}
107        pub mod RW {}
108    }
109    #[doc = "Revision number of the controller core."]
110    pub mod REVISION {
111        pub const offset: u32 = 16;
112        pub const mask: u32 = 0xff << offset;
113        pub mod R {}
114        pub mod W {}
115        pub mod RW {}
116    }
117}
118#[doc = "Hardware General"]
119pub mod HWGENERAL {
120    #[doc = "Data width of the transciever connected to the controller core. PHYW bit reset value is"]
121    pub mod PHYW {
122        pub const offset: u32 = 4;
123        pub const mask: u32 = 0x03 << offset;
124        pub mod R {}
125        pub mod W {}
126        pub mod RW {
127            #[doc = "8 bit wide data bus Software non-programmable"]
128            pub const PHYW_0: u32 = 0;
129            #[doc = "16 bit wide data bus Software non-programmable"]
130            pub const PHYW_1: u32 = 0x01;
131            #[doc = "Reset to 8 bit wide data bus Software programmable"]
132            pub const PHYW_2: u32 = 0x02;
133            #[doc = "Reset to 16 bit wide data bus Software programmable"]
134            pub const PHYW_3: u32 = 0x03;
135        }
136    }
137    #[doc = "Transciever type"]
138    pub mod PHYM {
139        pub const offset: u32 = 6;
140        pub const mask: u32 = 0x07 << offset;
141        pub mod R {}
142        pub mod W {}
143        pub mod RW {
144            #[doc = "UTMI/UMTI+"]
145            pub const PHYM_0: u32 = 0;
146            #[doc = "ULPI DDR"]
147            pub const PHYM_1: u32 = 0x01;
148            #[doc = "ULPI"]
149            pub const PHYM_2: u32 = 0x02;
150            #[doc = "Serial Only"]
151            pub const PHYM_3: u32 = 0x03;
152            #[doc = "Software programmable - reset to UTMI/UTMI+"]
153            pub const PHYM_4: u32 = 0x04;
154            #[doc = "Software programmable - reset to ULPI DDR"]
155            pub const PHYM_5: u32 = 0x05;
156            #[doc = "Software programmable - reset to ULPI"]
157            pub const PHYM_6: u32 = 0x06;
158            #[doc = "Software programmable - reset to Serial"]
159            pub const PHYM_7: u32 = 0x07;
160        }
161    }
162    #[doc = "Serial interface mode capability"]
163    pub mod SM {
164        pub const offset: u32 = 9;
165        pub const mask: u32 = 0x03 << offset;
166        pub mod R {}
167        pub mod W {}
168        pub mod RW {
169            #[doc = "No Serial Engine, always use parallel signalling."]
170            pub const SM_0: u32 = 0;
171            #[doc = "Serial Engine present, always use serial signalling for FS/LS."]
172            pub const SM_1: u32 = 0x01;
173            #[doc = "Software programmable - Reset to use parallel signalling for FS/LS"]
174            pub const SM_2: u32 = 0x02;
175            #[doc = "Software programmable - Reset to use serial signalling for FS/LS"]
176            pub const SM_3: u32 = 0x03;
177        }
178    }
179}
180#[doc = "Host Hardware Parameters"]
181pub mod HWHOST {
182    #[doc = "Host Capable. Indicating whether host operation mode is supported or not."]
183    pub mod HC {
184        pub const offset: u32 = 0;
185        pub const mask: u32 = 0x01 << offset;
186        pub mod R {}
187        pub mod W {}
188        pub mod RW {
189            #[doc = "Not supported"]
190            pub const HC_0: u32 = 0;
191            #[doc = "Supported"]
192            pub const HC_1: u32 = 0x01;
193        }
194    }
195    #[doc = "The Nmber of downstream ports supported by the host controller is (NPORT+1)"]
196    pub mod NPORT {
197        pub const offset: u32 = 1;
198        pub const mask: u32 = 0x07 << offset;
199        pub mod R {}
200        pub mod W {}
201        pub mod RW {}
202    }
203}
204#[doc = "Device Hardware Parameters"]
205pub mod HWDEVICE {
206    #[doc = "Device Capable. Indicating whether device operation mode is supported or not."]
207    pub mod DC {
208        pub const offset: u32 = 0;
209        pub const mask: u32 = 0x01 << offset;
210        pub mod R {}
211        pub mod W {}
212        pub mod RW {
213            #[doc = "Not supported"]
214            pub const DC_0: u32 = 0;
215            #[doc = "Supported"]
216            pub const DC_1: u32 = 0x01;
217        }
218    }
219    #[doc = "Device Endpoint Number"]
220    pub mod DEVEP {
221        pub const offset: u32 = 1;
222        pub const mask: u32 = 0x1f << offset;
223        pub mod R {}
224        pub mod W {}
225        pub mod RW {}
226    }
227}
228#[doc = "TX Buffer Hardware Parameters"]
229pub mod HWTXBUF {
230    #[doc = "Default burst size for memory to TX buffer transfer"]
231    pub mod TXBURST {
232        pub const offset: u32 = 0;
233        pub const mask: u32 = 0xff << offset;
234        pub mod R {}
235        pub mod W {}
236        pub mod RW {}
237    }
238    #[doc = "TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes"]
239    pub mod TXCHANADD {
240        pub const offset: u32 = 16;
241        pub const mask: u32 = 0xff << offset;
242        pub mod R {}
243        pub mod W {}
244        pub mod RW {}
245    }
246}
247#[doc = "RX Buffer Hardware Parameters"]
248pub mod HWRXBUF {
249    #[doc = "Default burst size for memory to RX buffer transfer"]
250    pub mod RXBURST {
251        pub const offset: u32 = 0;
252        pub const mask: u32 = 0xff << offset;
253        pub mod R {}
254        pub mod W {}
255        pub mod RW {}
256    }
257    #[doc = "Buffer total size for all receive endpoints is (2^RXADD)"]
258    pub mod RXADD {
259        pub const offset: u32 = 8;
260        pub const mask: u32 = 0xff << offset;
261        pub mod R {}
262        pub mod W {}
263        pub mod RW {}
264    }
265}
266#[doc = "General Purpose Timer #0 Load"]
267pub mod GPTIMER0LD {
268    #[doc = "General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'"]
269    pub mod GPTLD {
270        pub const offset: u32 = 0;
271        pub const mask: u32 = 0x00ff_ffff << offset;
272        pub mod R {}
273        pub mod W {}
274        pub mod RW {}
275    }
276}
277#[doc = "General Purpose Timer #0 Controller"]
278pub mod GPTIMER0CTRL {
279    #[doc = "General Purpose Timer Counter. This field is the count value of the countdown timer."]
280    pub mod GPTCNT {
281        pub const offset: u32 = 0;
282        pub const mask: u32 = 0x00ff_ffff << offset;
283        pub mod R {}
284        pub mod W {}
285        pub mod RW {}
286    }
287    #[doc = "General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again"]
288    pub mod GPTMODE {
289        pub const offset: u32 = 24;
290        pub const mask: u32 = 0x01 << offset;
291        pub mod R {}
292        pub mod W {}
293        pub mod RW {
294            #[doc = "One Shot Mode"]
295            pub const GPTMODE_0: u32 = 0;
296            #[doc = "Repeat Mode"]
297            pub const GPTMODE_1: u32 = 0x01;
298        }
299    }
300    #[doc = "General Purpose Timer Reset"]
301    pub mod GPTRST {
302        pub const offset: u32 = 30;
303        pub const mask: u32 = 0x01 << offset;
304        pub mod R {}
305        pub mod W {}
306        pub mod RW {
307            #[doc = "No action"]
308            pub const GPTRST_0: u32 = 0;
309            #[doc = "Load counter value from GPTLD bits in n_GPTIMER0LD"]
310            pub const GPTRST_1: u32 = 0x01;
311        }
312    }
313    #[doc = "General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit."]
314    pub mod GPTRUN {
315        pub const offset: u32 = 31;
316        pub const mask: u32 = 0x01 << offset;
317        pub mod R {}
318        pub mod W {}
319        pub mod RW {
320            #[doc = "Stop counting"]
321            pub const GPTRUN_0: u32 = 0;
322            #[doc = "Run"]
323            pub const GPTRUN_1: u32 = 0x01;
324        }
325    }
326}
327#[doc = "General Purpose Timer #1 Load"]
328pub mod GPTIMER1LD {
329    #[doc = "General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'"]
330    pub mod GPTLD {
331        pub const offset: u32 = 0;
332        pub const mask: u32 = 0x00ff_ffff << offset;
333        pub mod R {}
334        pub mod W {}
335        pub mod RW {}
336    }
337}
338#[doc = "General Purpose Timer #1 Controller"]
339pub mod GPTIMER1CTRL {
340    #[doc = "General Purpose Timer Counter. This field is the count value of the countdown timer."]
341    pub mod GPTCNT {
342        pub const offset: u32 = 0;
343        pub const mask: u32 = 0x00ff_ffff << offset;
344        pub mod R {}
345        pub mod W {}
346        pub mod RW {}
347    }
348    #[doc = "General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software"]
349    pub mod GPTMODE {
350        pub const offset: u32 = 24;
351        pub const mask: u32 = 0x01 << offset;
352        pub mod R {}
353        pub mod W {}
354        pub mod RW {
355            #[doc = "One Shot Mode"]
356            pub const GPTMODE_0: u32 = 0;
357            #[doc = "Repeat Mode"]
358            pub const GPTMODE_1: u32 = 0x01;
359        }
360    }
361    #[doc = "General Purpose Timer Reset"]
362    pub mod GPTRST {
363        pub const offset: u32 = 30;
364        pub const mask: u32 = 0x01 << offset;
365        pub mod R {}
366        pub mod W {}
367        pub mod RW {
368            #[doc = "No action"]
369            pub const GPTRST_0: u32 = 0;
370            #[doc = "Load counter value from GPTLD bits in USB_n_GPTIMER0LD"]
371            pub const GPTRST_1: u32 = 0x01;
372        }
373    }
374    #[doc = "General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit."]
375    pub mod GPTRUN {
376        pub const offset: u32 = 31;
377        pub const mask: u32 = 0x01 << offset;
378        pub mod R {}
379        pub mod W {}
380        pub mod RW {
381            #[doc = "Stop counting"]
382            pub const GPTRUN_0: u32 = 0;
383            #[doc = "Run"]
384            pub const GPTRUN_1: u32 = 0x01;
385        }
386    }
387}
388#[doc = "System Bus Config"]
389pub mod SBUSCFG {
390    #[doc = "AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority)"]
391    pub mod AHBBRST {
392        pub const offset: u32 = 0;
393        pub const mask: u32 = 0x07 << offset;
394        pub mod R {}
395        pub mod W {}
396        pub mod RW {
397            #[doc = "Incremental burst of unspecified length only"]
398            pub const AHBBRST_0: u32 = 0;
399            #[doc = "INCR4 burst, then single transfer"]
400            pub const AHBBRST_1: u32 = 0x01;
401            #[doc = "INCR8 burst, INCR4 burst, then single transfer"]
402            pub const AHBBRST_2: u32 = 0x02;
403            #[doc = "INCR16 burst, INCR8 burst, INCR4 burst, then single transfer"]
404            pub const AHBBRST_3: u32 = 0x03;
405            #[doc = "INCR4 burst, then incremental burst of unspecified length"]
406            pub const AHBBRST_5: u32 = 0x05;
407            #[doc = "INCR8 burst, INCR4 burst, then incremental burst of unspecified length"]
408            pub const AHBBRST_6: u32 = 0x06;
409            #[doc = "INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length"]
410            pub const AHBBRST_7: u32 = 0x07;
411        }
412    }
413}
414#[doc = "Capability Registers Length"]
415pub mod CAPLENGTH {
416    #[doc = "These bits are used as an offset to add to register base to find the beginning of the Operational Register"]
417    pub mod CAPLENGTH {
418        pub const offset: u8 = 0;
419        pub const mask: u8 = 0xff << offset;
420        pub mod R {}
421        pub mod W {}
422        pub mod RW {}
423    }
424}
425#[doc = "Host Controller Interface Version"]
426pub mod HCIVERSION {
427    #[doc = "Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0."]
428    pub mod HCIVERSION {
429        pub const offset: u16 = 0;
430        pub const mask: u16 = 0xffff << offset;
431        pub mod R {}
432        pub mod W {}
433        pub mod RW {}
434    }
435}
436#[doc = "Host Controller Structural Parameters"]
437pub mod HCSPARAMS {
438    #[doc = "Number of downstream ports"]
439    pub mod N_PORTS {
440        pub const offset: u32 = 0;
441        pub const mask: u32 = 0x0f << offset;
442        pub mod R {}
443        pub mod W {}
444        pub mod RW {}
445    }
446    #[doc = "Port Power Control This field indicates whether the host controller implementation includes port power control"]
447    pub mod PPC {
448        pub const offset: u32 = 4;
449        pub const mask: u32 = 0x01 << offset;
450        pub mod R {}
451        pub mod W {}
452        pub mod RW {}
453    }
454    #[doc = "Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller"]
455    pub mod N_PCC {
456        pub const offset: u32 = 8;
457        pub const mask: u32 = 0x0f << offset;
458        pub mod R {}
459        pub mod W {}
460        pub mod RW {}
461    }
462    #[doc = "Number of Companion Controller (N_CC)"]
463    pub mod N_CC {
464        pub const offset: u32 = 12;
465        pub const mask: u32 = 0x0f << offset;
466        pub mod R {}
467        pub mod W {}
468        pub mod RW {
469            #[doc = "There is no internal Companion Controller and port-ownership hand-off is not supported."]
470            pub const N_CC_0: u32 = 0;
471            #[doc = "There are internal companion controller(s) and port-ownership hand-offs is supported."]
472            pub const N_CC_1: u32 = 0x01;
473        }
474    }
475    #[doc = "Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control"]
476    pub mod PI {
477        pub const offset: u32 = 16;
478        pub const mask: u32 = 0x01 << offset;
479        pub mod R {}
480        pub mod W {}
481        pub mod RW {}
482    }
483    #[doc = "Number of Ports per Transaction Translator (N_PTT)"]
484    pub mod N_PTT {
485        pub const offset: u32 = 20;
486        pub const mask: u32 = 0x0f << offset;
487        pub mod R {}
488        pub mod W {}
489        pub mod RW {}
490    }
491    #[doc = "Number of Transaction Translators (N_TT)"]
492    pub mod N_TT {
493        pub const offset: u32 = 24;
494        pub const mask: u32 = 0x0f << offset;
495        pub mod R {}
496        pub mod W {}
497        pub mod RW {}
498    }
499}
500#[doc = "Host Controller Capability Parameters"]
501pub mod HCCPARAMS {
502    #[doc = "64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported"]
503    pub mod ADC {
504        pub const offset: u32 = 0;
505        pub const mask: u32 = 0x01 << offset;
506        pub mod R {}
507        pub mod W {}
508        pub mod RW {}
509    }
510    #[doc = "Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller"]
511    pub mod PFL {
512        pub const offset: u32 = 1;
513        pub const mask: u32 = 0x01 << offset;
514        pub mod R {}
515        pub mod W {}
516        pub mod RW {}
517    }
518    #[doc = "Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule"]
519    pub mod ASP {
520        pub const offset: u32 = 2;
521        pub const mask: u32 = 0x01 << offset;
522        pub mod R {}
523        pub mod W {}
524        pub mod RW {}
525    }
526    #[doc = "Isochronous Scheduling Threshold"]
527    pub mod IST {
528        pub const offset: u32 = 4;
529        pub const mask: u32 = 0x0f << offset;
530        pub mod R {}
531        pub mod W {}
532        pub mod RW {}
533    }
534    #[doc = "EHCI Extended Capabilities Pointer"]
535    pub mod EECP {
536        pub const offset: u32 = 8;
537        pub const mask: u32 = 0xff << offset;
538        pub mod R {}
539        pub mod W {}
540        pub mod RW {}
541    }
542}
543#[doc = "Device Controller Interface Version"]
544pub mod DCIVERSION {
545    #[doc = "Device Controller Interface Version Number Default value is '01h', which means rev0.1."]
546    pub mod DCIVERSION {
547        pub const offset: u16 = 0;
548        pub const mask: u16 = 0xffff << offset;
549        pub mod R {}
550        pub mod W {}
551        pub mod RW {}
552    }
553}
554#[doc = "Device Controller Capability Parameters"]
555pub mod DCCPARAMS {
556    #[doc = "Device Endpoint Number This field indicates the number of endpoints built into the device controller"]
557    pub mod DEN {
558        pub const offset: u32 = 0;
559        pub const mask: u32 = 0x1f << offset;
560        pub mod R {}
561        pub mod W {}
562        pub mod RW {}
563    }
564    #[doc = "Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device."]
565    pub mod DC {
566        pub const offset: u32 = 7;
567        pub const mask: u32 = 0x01 << offset;
568        pub mod R {}
569        pub mod W {}
570        pub mod RW {}
571    }
572    #[doc = "Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2"]
573    pub mod HC {
574        pub const offset: u32 = 8;
575        pub const mask: u32 = 0x01 << offset;
576        pub mod R {}
577        pub mod W {}
578        pub mod RW {}
579    }
580}
581#[doc = "USB Command Register"]
582pub mod USBCMD {
583    #[doc = "Run/Stop (RS) - Read/Write"]
584    pub mod RS {
585        pub const offset: u32 = 0;
586        pub const mask: u32 = 0x01 << offset;
587        pub mod R {}
588        pub mod W {}
589        pub mod RW {}
590    }
591    #[doc = "Controller Reset (RESET) - Read/Write"]
592    pub mod RST {
593        pub const offset: u32 = 1;
594        pub const mask: u32 = 0x01 << offset;
595        pub mod R {}
596        pub mod W {}
597        pub mod RW {}
598    }
599    #[doc = "See description at bit 15"]
600    pub mod FS_1 {
601        pub const offset: u32 = 2;
602        pub const mask: u32 = 0x03 << offset;
603        pub mod R {}
604        pub mod W {}
605        pub mod RW {}
606    }
607    #[doc = "Periodic Schedule Enable- Read/Write"]
608    pub mod PSE {
609        pub const offset: u32 = 4;
610        pub const mask: u32 = 0x01 << offset;
611        pub mod R {}
612        pub mod W {}
613        pub mod RW {
614            #[doc = "Do not process the Periodic Schedule"]
615            pub const PSE_0: u32 = 0;
616            #[doc = "Use the PERIODICLISTBASE register to access the Periodic Schedule."]
617            pub const PSE_1: u32 = 0x01;
618        }
619    }
620    #[doc = "Asynchronous Schedule Enable - Read/Write"]
621    pub mod ASE {
622        pub const offset: u32 = 5;
623        pub const mask: u32 = 0x01 << offset;
624        pub mod R {}
625        pub mod W {}
626        pub mod RW {
627            #[doc = "Do not process the Asynchronous Schedule."]
628            pub const ASE_0: u32 = 0;
629            #[doc = "Use the ASYNCLISTADDR register to access the Asynchronous Schedule."]
630            pub const ASE_1: u32 = 0x01;
631        }
632    }
633    #[doc = "Interrupt on Async Advance Doorbell - Read/Write"]
634    pub mod IAA {
635        pub const offset: u32 = 6;
636        pub const mask: u32 = 0x01 << offset;
637        pub mod R {}
638        pub mod W {}
639        pub mod RW {}
640    }
641    #[doc = "Asynchronous Schedule Park Mode Count - Read/Write"]
642    pub mod ASP {
643        pub const offset: u32 = 8;
644        pub const mask: u32 = 0x03 << offset;
645        pub mod R {}
646        pub mod W {}
647        pub mod RW {}
648    }
649    #[doc = "Asynchronous Schedule Park Mode Enable - Read/Write"]
650    pub mod ASPE {
651        pub const offset: u32 = 11;
652        pub const mask: u32 = 0x01 << offset;
653        pub mod R {}
654        pub mod W {}
655        pub mod RW {}
656    }
657    #[doc = "Setup TripWire - Read/Write"]
658    pub mod SUTW {
659        pub const offset: u32 = 13;
660        pub const mask: u32 = 0x01 << offset;
661        pub mod R {}
662        pub mod W {}
663        pub mod RW {}
664    }
665    #[doc = "Add dTD TripWire - Read/Write"]
666    pub mod ATDTW {
667        pub const offset: u32 = 14;
668        pub const mask: u32 = 0x01 << offset;
669        pub mod R {}
670        pub mod W {}
671        pub mod RW {}
672    }
673    #[doc = "Frame List Size - (Read/Write or Read Only)"]
674    pub mod FS_2 {
675        pub const offset: u32 = 15;
676        pub const mask: u32 = 0x01 << offset;
677        pub mod R {}
678        pub mod W {}
679        pub mod RW {}
680    }
681    #[doc = "Interrupt Threshold Control -Read/Write"]
682    pub mod ITC {
683        pub const offset: u32 = 16;
684        pub const mask: u32 = 0xff << offset;
685        pub mod R {}
686        pub mod W {}
687        pub mod RW {
688            #[doc = "Immediate (no threshold)"]
689            pub const ITC_0: u32 = 0;
690            #[doc = "1 micro-frame"]
691            pub const ITC_1: u32 = 0x01;
692            #[doc = "2 micro-frames"]
693            pub const ITC_2: u32 = 0x02;
694            #[doc = "4 micro-frames"]
695            pub const ITC_4: u32 = 0x04;
696            #[doc = "8 micro-frames"]
697            pub const ITC_8: u32 = 0x08;
698            #[doc = "16 micro-frames"]
699            pub const ITC_16: u32 = 0x10;
700            #[doc = "32 micro-frames"]
701            pub const ITC_32: u32 = 0x20;
702            #[doc = "64 micro-frames"]
703            pub const ITC_64: u32 = 0x40;
704        }
705    }
706}
707#[doc = "USB Status Register"]
708pub mod USBSTS {
709    #[doc = "USB Interrupt (USBINT) - R/WC"]
710    pub mod UI {
711        pub const offset: u32 = 0;
712        pub const mask: u32 = 0x01 << offset;
713        pub mod R {}
714        pub mod W {}
715        pub mod RW {}
716    }
717    #[doc = "USB Error Interrupt (USBERRINT) - R/WC"]
718    pub mod UEI {
719        pub const offset: u32 = 1;
720        pub const mask: u32 = 0x01 << offset;
721        pub mod R {}
722        pub mod W {}
723        pub mod RW {}
724    }
725    #[doc = "Port Change Detect - R/WC"]
726    pub mod PCI {
727        pub const offset: u32 = 2;
728        pub const mask: u32 = 0x01 << offset;
729        pub mod R {}
730        pub mod W {}
731        pub mod RW {}
732    }
733    #[doc = "Frame List Rollover - R/WC"]
734    pub mod FRI {
735        pub const offset: u32 = 3;
736        pub const mask: u32 = 0x01 << offset;
737        pub mod R {}
738        pub mod W {}
739        pub mod RW {}
740    }
741    #[doc = "System Error- R/WC"]
742    pub mod SEI {
743        pub const offset: u32 = 4;
744        pub const mask: u32 = 0x01 << offset;
745        pub mod R {}
746        pub mod W {}
747        pub mod RW {}
748    }
749    #[doc = "Interrupt on Async Advance - R/WC"]
750    pub mod AAI {
751        pub const offset: u32 = 5;
752        pub const mask: u32 = 0x01 << offset;
753        pub mod R {}
754        pub mod W {}
755        pub mod RW {}
756    }
757    #[doc = "USB Reset Received - R/WC"]
758    pub mod URI {
759        pub const offset: u32 = 6;
760        pub const mask: u32 = 0x01 << offset;
761        pub mod R {}
762        pub mod W {}
763        pub mod RW {}
764    }
765    #[doc = "SOF Received - R/WC"]
766    pub mod SRI {
767        pub const offset: u32 = 7;
768        pub const mask: u32 = 0x01 << offset;
769        pub mod R {}
770        pub mod W {}
771        pub mod RW {}
772    }
773    #[doc = "DCSuspend - R/WC"]
774    pub mod SLI {
775        pub const offset: u32 = 8;
776        pub const mask: u32 = 0x01 << offset;
777        pub mod R {}
778        pub mod W {}
779        pub mod RW {}
780    }
781    #[doc = "ULPI Interrupt - R/WC"]
782    pub mod ULPII {
783        pub const offset: u32 = 10;
784        pub const mask: u32 = 0x01 << offset;
785        pub mod R {}
786        pub mod W {}
787        pub mod RW {}
788    }
789    #[doc = "HCHaIted - Read Only"]
790    pub mod HCH {
791        pub const offset: u32 = 12;
792        pub const mask: u32 = 0x01 << offset;
793        pub mod R {}
794        pub mod W {}
795        pub mod RW {}
796    }
797    #[doc = "Reclamation - Read Only"]
798    pub mod RCL {
799        pub const offset: u32 = 13;
800        pub const mask: u32 = 0x01 << offset;
801        pub mod R {}
802        pub mod W {}
803        pub mod RW {}
804    }
805    #[doc = "Periodic Schedule Status - Read Only"]
806    pub mod PS {
807        pub const offset: u32 = 14;
808        pub const mask: u32 = 0x01 << offset;
809        pub mod R {}
810        pub mod W {}
811        pub mod RW {}
812    }
813    #[doc = "Asynchronous Schedule Status - Read Only"]
814    pub mod AS {
815        pub const offset: u32 = 15;
816        pub const mask: u32 = 0x01 << offset;
817        pub mod R {}
818        pub mod W {}
819        pub mod RW {}
820    }
821    #[doc = "NAK Interrupt Bit--RO"]
822    pub mod NAKI {
823        pub const offset: u32 = 16;
824        pub const mask: u32 = 0x01 << offset;
825        pub mod R {}
826        pub mod W {}
827        pub mod RW {}
828    }
829    #[doc = "General Purpose Timer Interrupt 0(GPTINT0)--R/WC"]
830    pub mod TI0 {
831        pub const offset: u32 = 24;
832        pub const mask: u32 = 0x01 << offset;
833        pub mod R {}
834        pub mod W {}
835        pub mod RW {}
836    }
837    #[doc = "General Purpose Timer Interrupt 1(GPTINT1)--R/WC"]
838    pub mod TI1 {
839        pub const offset: u32 = 25;
840        pub const mask: u32 = 0x01 << offset;
841        pub mod R {}
842        pub mod W {}
843        pub mod RW {}
844    }
845}
846#[doc = "Interrupt Enable Register"]
847pub mod USBINTR {
848    #[doc = "USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt"]
849    pub mod UE {
850        pub const offset: u32 = 0;
851        pub const mask: u32 = 0x01 << offset;
852        pub mod R {}
853        pub mod W {}
854        pub mod RW {}
855    }
856    #[doc = "USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt"]
857    pub mod UEE {
858        pub const offset: u32 = 1;
859        pub const mask: u32 = 0x01 << offset;
860        pub mod R {}
861        pub mod W {}
862        pub mod RW {}
863    }
864    #[doc = "Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt"]
865    pub mod PCE {
866        pub const offset: u32 = 2;
867        pub const mask: u32 = 0x01 << offset;
868        pub mod R {}
869        pub mod W {}
870        pub mod RW {}
871    }
872    #[doc = "Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt"]
873    pub mod FRE {
874        pub const offset: u32 = 3;
875        pub const mask: u32 = 0x01 << offset;
876        pub mod R {}
877        pub mod W {}
878        pub mod RW {}
879    }
880    #[doc = "System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt"]
881    pub mod SEE {
882        pub const offset: u32 = 4;
883        pub const mask: u32 = 0x01 << offset;
884        pub mod R {}
885        pub mod W {}
886        pub mod RW {}
887    }
888    #[doc = "Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt"]
889    pub mod AAE {
890        pub const offset: u32 = 5;
891        pub const mask: u32 = 0x01 << offset;
892        pub mod R {}
893        pub mod W {}
894        pub mod RW {}
895    }
896    #[doc = "USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt"]
897    pub mod URE {
898        pub const offset: u32 = 6;
899        pub const mask: u32 = 0x01 << offset;
900        pub mod R {}
901        pub mod W {}
902        pub mod RW {}
903    }
904    #[doc = "SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt"]
905    pub mod SRE {
906        pub const offset: u32 = 7;
907        pub const mask: u32 = 0x01 << offset;
908        pub mod R {}
909        pub mod W {}
910        pub mod RW {}
911    }
912    #[doc = "Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt"]
913    pub mod SLE {
914        pub const offset: u32 = 8;
915        pub const mask: u32 = 0x01 << offset;
916        pub mod R {}
917        pub mod W {}
918        pub mod RW {}
919    }
920    #[doc = "ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt"]
921    pub mod ULPIE {
922        pub const offset: u32 = 10;
923        pub const mask: u32 = 0x01 << offset;
924        pub mod R {}
925        pub mod W {}
926        pub mod RW {}
927    }
928    #[doc = "NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt"]
929    pub mod NAKE {
930        pub const offset: u32 = 16;
931        pub const mask: u32 = 0x01 << offset;
932        pub mod R {}
933        pub mod W {}
934        pub mod RW {}
935    }
936    #[doc = "USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold"]
937    pub mod UAIE {
938        pub const offset: u32 = 18;
939        pub const mask: u32 = 0x01 << offset;
940        pub mod R {}
941        pub mod W {}
942        pub mod RW {}
943    }
944    #[doc = "USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold"]
945    pub mod UPIE {
946        pub const offset: u32 = 19;
947        pub const mask: u32 = 0x01 << offset;
948        pub mod R {}
949        pub mod W {}
950        pub mod RW {}
951    }
952    #[doc = "General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt"]
953    pub mod TIE0 {
954        pub const offset: u32 = 24;
955        pub const mask: u32 = 0x01 << offset;
956        pub mod R {}
957        pub mod W {}
958        pub mod RW {}
959    }
960    #[doc = "General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt"]
961    pub mod TIE1 {
962        pub const offset: u32 = 25;
963        pub const mask: u32 = 0x01 << offset;
964        pub mod R {}
965        pub mod W {}
966        pub mod RW {}
967    }
968}
969#[doc = "USB Frame Index"]
970pub mod FRINDEX {
971    #[doc = "Frame Index"]
972    pub mod FRINDEX {
973        pub const offset: u32 = 0;
974        pub const mask: u32 = 0x3fff << offset;
975        pub mod R {}
976        pub mod W {}
977        pub mod RW {
978            #[doc = "(1024) 12"]
979            pub const FRINDEX_0: u32 = 0;
980            #[doc = "(512) 11"]
981            pub const FRINDEX_1: u32 = 0x01;
982            #[doc = "(256) 10"]
983            pub const FRINDEX_2: u32 = 0x02;
984            #[doc = "(128) 9"]
985            pub const FRINDEX_3: u32 = 0x03;
986            #[doc = "(64) 8"]
987            pub const FRINDEX_4: u32 = 0x04;
988            #[doc = "(32) 7"]
989            pub const FRINDEX_5: u32 = 0x05;
990            #[doc = "(16) 6"]
991            pub const FRINDEX_6: u32 = 0x06;
992            #[doc = "(8) 5"]
993            pub const FRINDEX_7: u32 = 0x07;
994        }
995    }
996}
997#[doc = "Device Address"]
998pub mod DEVICEADDR {
999    #[doc = "Device Address Advance"]
1000    pub mod USBADRA {
1001        pub const offset: u32 = 24;
1002        pub const mask: u32 = 0x01 << offset;
1003        pub mod R {}
1004        pub mod W {}
1005        pub mod RW {}
1006    }
1007    #[doc = "Device Address. These bits correspond to the USB device address"]
1008    pub mod USBADR {
1009        pub const offset: u32 = 25;
1010        pub const mask: u32 = 0x7f << offset;
1011        pub mod R {}
1012        pub mod W {}
1013        pub mod RW {}
1014    }
1015}
1016#[doc = "Next Asynch. Address"]
1017pub mod ASYNCLISTADDR {
1018    #[doc = "Link Pointer Low (LPL)"]
1019    pub mod ASYBASE {
1020        pub const offset: u32 = 5;
1021        pub const mask: u32 = 0x07ff_ffff << offset;
1022        pub mod R {}
1023        pub mod W {}
1024        pub mod RW {}
1025    }
1026}
1027#[doc = "Programmable Burst Size"]
1028pub mod BURSTSIZE {
1029    #[doc = "Programmable RX Burst Size"]
1030    pub mod RXPBURST {
1031        pub const offset: u32 = 0;
1032        pub const mask: u32 = 0xff << offset;
1033        pub mod R {}
1034        pub mod W {}
1035        pub mod RW {}
1036    }
1037    #[doc = "Programmable TX Burst Size"]
1038    pub mod TXPBURST {
1039        pub const offset: u32 = 8;
1040        pub const mask: u32 = 0x01ff << offset;
1041        pub mod R {}
1042        pub mod W {}
1043        pub mod RW {}
1044    }
1045}
1046#[doc = "TX FIFO Fill Tuning"]
1047pub mod TXFILLTUNING {
1048    #[doc = "Scheduler Overhead"]
1049    pub mod TXSCHOH {
1050        pub const offset: u32 = 0;
1051        pub const mask: u32 = 0xff << offset;
1052        pub mod R {}
1053        pub mod W {}
1054        pub mod RW {}
1055    }
1056    #[doc = "Scheduler Health Counter"]
1057    pub mod TXSCHHEALTH {
1058        pub const offset: u32 = 8;
1059        pub const mask: u32 = 0x1f << offset;
1060        pub mod R {}
1061        pub mod W {}
1062        pub mod RW {}
1063    }
1064    #[doc = "FIFO Burst Threshold"]
1065    pub mod TXFIFOTHRES {
1066        pub const offset: u32 = 16;
1067        pub const mask: u32 = 0x3f << offset;
1068        pub mod R {}
1069        pub mod W {}
1070        pub mod RW {}
1071    }
1072}
1073#[doc = "Endpoint NAK"]
1074pub mod ENDPTNAK {
1075    #[doc = "RX Endpoint NAK - R/WC"]
1076    pub mod EPRN {
1077        pub const offset: u32 = 0;
1078        pub const mask: u32 = 0xff << offset;
1079        pub mod R {}
1080        pub mod W {}
1081        pub mod RW {}
1082    }
1083    #[doc = "TX Endpoint NAK - R/WC"]
1084    pub mod EPTN {
1085        pub const offset: u32 = 16;
1086        pub const mask: u32 = 0xff << offset;
1087        pub mod R {}
1088        pub mod W {}
1089        pub mod RW {}
1090    }
1091}
1092#[doc = "Endpoint NAK Enable"]
1093pub mod ENDPTNAKEN {
1094    #[doc = "RX Endpoint NAK Enable - R/W"]
1095    pub mod EPRNE {
1096        pub const offset: u32 = 0;
1097        pub const mask: u32 = 0xff << offset;
1098        pub mod R {}
1099        pub mod W {}
1100        pub mod RW {}
1101    }
1102    #[doc = "TX Endpoint NAK Enable - R/W"]
1103    pub mod EPTNE {
1104        pub const offset: u32 = 16;
1105        pub const mask: u32 = 0xff << offset;
1106        pub mod R {}
1107        pub mod W {}
1108        pub mod RW {}
1109    }
1110}
1111#[doc = "Configure Flag Register"]
1112pub mod CONFIGFLAG {
1113    #[doc = "Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller"]
1114    pub mod CF {
1115        pub const offset: u32 = 0;
1116        pub const mask: u32 = 0x01 << offset;
1117        pub mod R {}
1118        pub mod W {}
1119        pub mod RW {
1120            #[doc = "Port routing control logic default-routes each port to an implementation dependent classic host controller."]
1121            pub const CF_0: u32 = 0;
1122            #[doc = "Port routing control logic default-routes all ports to this host controller."]
1123            pub const CF_1: u32 = 0x01;
1124        }
1125    }
1126}
1127#[doc = "Port Status & Control"]
1128pub mod PORTSC1 {
1129    #[doc = "Current Connect Status-Read Only"]
1130    pub mod CCS {
1131        pub const offset: u32 = 0;
1132        pub const mask: u32 = 0x01 << offset;
1133        pub mod R {}
1134        pub mod W {}
1135        pub mod RW {}
1136    }
1137    #[doc = "Connect Status Change-R/WC"]
1138    pub mod CSC {
1139        pub const offset: u32 = 1;
1140        pub const mask: u32 = 0x01 << offset;
1141        pub mod R {}
1142        pub mod W {}
1143        pub mod RW {}
1144    }
1145    #[doc = "Port Enabled/Disabled-Read/Write"]
1146    pub mod PE {
1147        pub const offset: u32 = 2;
1148        pub const mask: u32 = 0x01 << offset;
1149        pub mod R {}
1150        pub mod W {}
1151        pub mod RW {}
1152    }
1153    #[doc = "Port Enable/Disable Change-R/WC"]
1154    pub mod PEC {
1155        pub const offset: u32 = 3;
1156        pub const mask: u32 = 0x01 << offset;
1157        pub mod R {}
1158        pub mod W {}
1159        pub mod RW {}
1160    }
1161    #[doc = "Over-current Active-Read Only"]
1162    pub mod OCA {
1163        pub const offset: u32 = 4;
1164        pub const mask: u32 = 0x01 << offset;
1165        pub mod R {}
1166        pub mod W {}
1167        pub mod RW {
1168            #[doc = "This port does not have an over-current condition."]
1169            pub const OCA_0: u32 = 0;
1170            #[doc = "This port currently has an over-current condition"]
1171            pub const OCA_1: u32 = 0x01;
1172        }
1173    }
1174    #[doc = "Over-current Change-R/WC"]
1175    pub mod OCC {
1176        pub const offset: u32 = 5;
1177        pub const mask: u32 = 0x01 << offset;
1178        pub mod R {}
1179        pub mod W {}
1180        pub mod RW {}
1181    }
1182    #[doc = "Force Port Resume -Read/Write"]
1183    pub mod FPR {
1184        pub const offset: u32 = 6;
1185        pub const mask: u32 = 0x01 << offset;
1186        pub mod R {}
1187        pub mod W {}
1188        pub mod RW {}
1189    }
1190    #[doc = "Suspend - Read/Write or Read Only"]
1191    pub mod SUSP {
1192        pub const offset: u32 = 7;
1193        pub const mask: u32 = 0x01 << offset;
1194        pub mod R {}
1195        pub mod W {}
1196        pub mod RW {}
1197    }
1198    #[doc = "Port Reset - Read/Write or Read Only"]
1199    pub mod PR {
1200        pub const offset: u32 = 8;
1201        pub const mask: u32 = 0x01 << offset;
1202        pub mod R {}
1203        pub mod W {}
1204        pub mod RW {}
1205    }
1206    #[doc = "High-Speed Port - Read Only"]
1207    pub mod HSP {
1208        pub const offset: u32 = 9;
1209        pub const mask: u32 = 0x01 << offset;
1210        pub mod R {}
1211        pub mod W {}
1212        pub mod RW {}
1213    }
1214    #[doc = "Line Status-Read Only"]
1215    pub mod LS {
1216        pub const offset: u32 = 10;
1217        pub const mask: u32 = 0x03 << offset;
1218        pub mod R {}
1219        pub mod W {}
1220        pub mod RW {
1221            #[doc = "SE0"]
1222            pub const LS_0: u32 = 0;
1223            #[doc = "K-state"]
1224            pub const LS_1: u32 = 0x01;
1225            #[doc = "J-state"]
1226            pub const LS_2: u32 = 0x02;
1227            #[doc = "Undefined"]
1228            pub const LS_3: u32 = 0x03;
1229        }
1230    }
1231    #[doc = "Port Power (PP)-Read/Write or Read Only"]
1232    pub mod PP {
1233        pub const offset: u32 = 12;
1234        pub const mask: u32 = 0x01 << offset;
1235        pub mod R {}
1236        pub mod W {}
1237        pub mod RW {}
1238    }
1239    #[doc = "Port Owner-Read/Write"]
1240    pub mod PO {
1241        pub const offset: u32 = 13;
1242        pub const mask: u32 = 0x01 << offset;
1243        pub mod R {}
1244        pub mod W {}
1245        pub mod RW {}
1246    }
1247    #[doc = "Port Indicator Control - Read/Write"]
1248    pub mod PIC {
1249        pub const offset: u32 = 14;
1250        pub const mask: u32 = 0x03 << offset;
1251        pub mod R {}
1252        pub mod W {}
1253        pub mod RW {
1254            #[doc = "Port indicators are off"]
1255            pub const PIC_0: u32 = 0;
1256            #[doc = "Amber"]
1257            pub const PIC_1: u32 = 0x01;
1258            #[doc = "Green"]
1259            pub const PIC_2: u32 = 0x02;
1260            #[doc = "Undefined"]
1261            pub const PIC_3: u32 = 0x03;
1262        }
1263    }
1264    #[doc = "Port Test Control - Read/Write"]
1265    pub mod PTC {
1266        pub const offset: u32 = 16;
1267        pub const mask: u32 = 0x0f << offset;
1268        pub mod R {}
1269        pub mod W {}
1270        pub mod RW {
1271            #[doc = "TEST_MODE_DISABLE"]
1272            pub const PTC_0: u32 = 0;
1273            #[doc = "J_STATE"]
1274            pub const PTC_1: u32 = 0x01;
1275            #[doc = "K_STATE"]
1276            pub const PTC_2: u32 = 0x02;
1277            #[doc = "SE0 (host) / NAK (device)"]
1278            pub const PTC_3: u32 = 0x03;
1279            #[doc = "Packet"]
1280            pub const PTC_4: u32 = 0x04;
1281            #[doc = "FORCE_ENABLE_HS"]
1282            pub const PTC_5: u32 = 0x05;
1283            #[doc = "FORCE_ENABLE_FS"]
1284            pub const PTC_6: u32 = 0x06;
1285            #[doc = "FORCE_ENABLE_LS"]
1286            pub const PTC_7: u32 = 0x07;
1287        }
1288    }
1289    #[doc = "Wake on Connect Enable (WKCNNT_E) - Read/Write"]
1290    pub mod WKCN {
1291        pub const offset: u32 = 20;
1292        pub const mask: u32 = 0x01 << offset;
1293        pub mod R {}
1294        pub mod W {}
1295        pub mod RW {}
1296    }
1297    #[doc = "Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write"]
1298    pub mod WKDC {
1299        pub const offset: u32 = 21;
1300        pub const mask: u32 = 0x01 << offset;
1301        pub mod R {}
1302        pub mod W {}
1303        pub mod RW {}
1304    }
1305    #[doc = "Wake on Over-current Enable (WKOC_E) - Read/Write"]
1306    pub mod WKOC {
1307        pub const offset: u32 = 22;
1308        pub const mask: u32 = 0x01 << offset;
1309        pub mod R {}
1310        pub mod W {}
1311        pub mod RW {}
1312    }
1313    #[doc = "PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write"]
1314    pub mod PHCD {
1315        pub const offset: u32 = 23;
1316        pub const mask: u32 = 0x01 << offset;
1317        pub mod R {}
1318        pub mod W {}
1319        pub mod RW {
1320            #[doc = "Enable PHY clock"]
1321            pub const PHCD_0: u32 = 0;
1322            #[doc = "Disable PHY clock"]
1323            pub const PHCD_1: u32 = 0x01;
1324        }
1325    }
1326    #[doc = "Port Force Full Speed Connect - Read/Write"]
1327    pub mod PFSC {
1328        pub const offset: u32 = 24;
1329        pub const mask: u32 = 0x01 << offset;
1330        pub mod R {}
1331        pub mod W {}
1332        pub mod RW {
1333            #[doc = "Normal operation"]
1334            pub const PFSC_0: u32 = 0;
1335            #[doc = "Forced to full speed"]
1336            pub const PFSC_1: u32 = 0x01;
1337        }
1338    }
1339    #[doc = "See description at bits 31-30"]
1340    pub mod PTS_2 {
1341        pub const offset: u32 = 25;
1342        pub const mask: u32 = 0x01 << offset;
1343        pub mod R {}
1344        pub mod W {}
1345        pub mod RW {}
1346    }
1347    #[doc = "Port Speed - Read Only. This register field indicates the speed at which the port is operating."]
1348    pub mod PSPD {
1349        pub const offset: u32 = 26;
1350        pub const mask: u32 = 0x03 << offset;
1351        pub mod R {}
1352        pub mod W {}
1353        pub mod RW {
1354            #[doc = "Full Speed"]
1355            pub const PSPD_0: u32 = 0;
1356            #[doc = "Low Speed"]
1357            pub const PSPD_1: u32 = 0x01;
1358            #[doc = "High Speed"]
1359            pub const PSPD_2: u32 = 0x02;
1360            #[doc = "Undefined"]
1361            pub const PSPD_3: u32 = 0x03;
1362        }
1363    }
1364    #[doc = "Parallel Transceiver Width This bit has no effect if serial interface engine is used"]
1365    pub mod PTW {
1366        pub const offset: u32 = 28;
1367        pub const mask: u32 = 0x01 << offset;
1368        pub mod R {}
1369        pub mod W {}
1370        pub mod RW {
1371            #[doc = "Select the 8-bit UTMI interface \\[60MHz\\]"]
1372            pub const PTW_0: u32 = 0;
1373            #[doc = "Select the 16-bit UTMI interface \\[30MHz\\]"]
1374            pub const PTW_1: u32 = 0x01;
1375        }
1376    }
1377    #[doc = "Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals"]
1378    pub mod STS {
1379        pub const offset: u32 = 29;
1380        pub const mask: u32 = 0x01 << offset;
1381        pub mod R {}
1382        pub mod W {}
1383        pub mod RW {}
1384    }
1385    #[doc = "All USB port interface modes are listed in this field description, but not all are supported"]
1386    pub mod PTS_1 {
1387        pub const offset: u32 = 30;
1388        pub const mask: u32 = 0x03 << offset;
1389        pub mod R {}
1390        pub mod W {}
1391        pub mod RW {}
1392    }
1393}
1394#[doc = "On-The-Go Status & control"]
1395pub mod OTGSC {
1396    #[doc = "VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor."]
1397    pub mod VD {
1398        pub const offset: u32 = 0;
1399        pub const mask: u32 = 0x01 << offset;
1400        pub mod R {}
1401        pub mod W {}
1402        pub mod RW {}
1403    }
1404    #[doc = "VBUS Charge - Read/Write"]
1405    pub mod VC {
1406        pub const offset: u32 = 1;
1407        pub const mask: u32 = 0x01 << offset;
1408        pub mod R {}
1409        pub mod W {}
1410        pub mod RW {}
1411    }
1412    #[doc = "OTG Termination - Read/Write"]
1413    pub mod OT {
1414        pub const offset: u32 = 3;
1415        pub const mask: u32 = 0x01 << offset;
1416        pub mod R {}
1417        pub mod W {}
1418        pub mod RW {}
1419    }
1420    #[doc = "Data Pulsing - Read/Write"]
1421    pub mod DP {
1422        pub const offset: u32 = 4;
1423        pub const mask: u32 = 0x01 << offset;
1424        pub mod R {}
1425        pub mod W {}
1426        pub mod RW {}
1427    }
1428    #[doc = "ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on \\[default\\]"]
1429    pub mod IDPU {
1430        pub const offset: u32 = 5;
1431        pub const mask: u32 = 0x01 << offset;
1432        pub mod R {}
1433        pub mod W {}
1434        pub mod RW {}
1435    }
1436    #[doc = "USB ID - Read Only. 0 = A device, 1 = B device"]
1437    pub mod ID {
1438        pub const offset: u32 = 8;
1439        pub const mask: u32 = 0x01 << offset;
1440        pub mod R {}
1441        pub mod W {}
1442        pub mod RW {}
1443    }
1444    #[doc = "A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold."]
1445    pub mod AVV {
1446        pub const offset: u32 = 9;
1447        pub const mask: u32 = 0x01 << offset;
1448        pub mod R {}
1449        pub mod W {}
1450        pub mod RW {}
1451    }
1452    #[doc = "A Session Valid - Read Only. Indicates VBus is above the A session valid threshold."]
1453    pub mod ASV {
1454        pub const offset: u32 = 10;
1455        pub const mask: u32 = 0x01 << offset;
1456        pub mod R {}
1457        pub mod W {}
1458        pub mod RW {}
1459    }
1460    #[doc = "B Session Valid - Read Only. Indicates VBus is above the B session valid threshold."]
1461    pub mod BSV {
1462        pub const offset: u32 = 11;
1463        pub const mask: u32 = 0x01 << offset;
1464        pub mod R {}
1465        pub mod W {}
1466        pub mod RW {}
1467    }
1468    #[doc = "B Session End - Read Only. Indicates VBus is below the B session end threshold."]
1469    pub mod BSE {
1470        pub const offset: u32 = 12;
1471        pub const mask: u32 = 0x01 << offset;
1472        pub mod R {}
1473        pub mod W {}
1474        pub mod RW {}
1475    }
1476    #[doc = "1 millisecond timer toggle - Read Only. This bit toggles once per millisecond."]
1477    pub mod TOG_1MS {
1478        pub const offset: u32 = 13;
1479        pub const mask: u32 = 0x01 << offset;
1480        pub mod R {}
1481        pub mod W {}
1482        pub mod RW {}
1483    }
1484    #[doc = "Data Bus Pulsing Status - Read Only"]
1485    pub mod DPS {
1486        pub const offset: u32 = 14;
1487        pub const mask: u32 = 0x01 << offset;
1488        pub mod R {}
1489        pub mod W {}
1490        pub mod RW {}
1491    }
1492    #[doc = "USB ID Interrupt Status - Read/Write"]
1493    pub mod IDIS {
1494        pub const offset: u32 = 16;
1495        pub const mask: u32 = 0x01 << offset;
1496        pub mod R {}
1497        pub mod W {}
1498        pub mod RW {}
1499    }
1500    #[doc = "A VBus Valid Interrupt Status - Read/Write to Clear"]
1501    pub mod AVVIS {
1502        pub const offset: u32 = 17;
1503        pub const mask: u32 = 0x01 << offset;
1504        pub mod R {}
1505        pub mod W {}
1506        pub mod RW {}
1507    }
1508    #[doc = "A Session Valid Interrupt Status - Read/Write to Clear"]
1509    pub mod ASVIS {
1510        pub const offset: u32 = 18;
1511        pub const mask: u32 = 0x01 << offset;
1512        pub mod R {}
1513        pub mod W {}
1514        pub mod RW {}
1515    }
1516    #[doc = "B Session Valid Interrupt Status - Read/Write to Clear"]
1517    pub mod BSVIS {
1518        pub const offset: u32 = 19;
1519        pub const mask: u32 = 0x01 << offset;
1520        pub mod R {}
1521        pub mod W {}
1522        pub mod RW {}
1523    }
1524    #[doc = "B Session End Interrupt Status - Read/Write to Clear"]
1525    pub mod BSEIS {
1526        pub const offset: u32 = 20;
1527        pub const mask: u32 = 0x01 << offset;
1528        pub mod R {}
1529        pub mod W {}
1530        pub mod RW {}
1531    }
1532    #[doc = "1 millisecond timer Interrupt Status - Read/Write to Clear"]
1533    pub mod STATUS_1MS {
1534        pub const offset: u32 = 21;
1535        pub const mask: u32 = 0x01 << offset;
1536        pub mod R {}
1537        pub mod W {}
1538        pub mod RW {}
1539    }
1540    #[doc = "Data Pulse Interrupt Status - Read/Write to Clear"]
1541    pub mod DPIS {
1542        pub const offset: u32 = 22;
1543        pub const mask: u32 = 0x01 << offset;
1544        pub mod R {}
1545        pub mod W {}
1546        pub mod RW {}
1547    }
1548    #[doc = "USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt."]
1549    pub mod IDIE {
1550        pub const offset: u32 = 24;
1551        pub const mask: u32 = 0x01 << offset;
1552        pub mod R {}
1553        pub mod W {}
1554        pub mod RW {}
1555    }
1556    #[doc = "A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt."]
1557    pub mod AVVIE {
1558        pub const offset: u32 = 25;
1559        pub const mask: u32 = 0x01 << offset;
1560        pub mod R {}
1561        pub mod W {}
1562        pub mod RW {}
1563    }
1564    #[doc = "A Session Valid Interrupt Enable - Read/Write"]
1565    pub mod ASVIE {
1566        pub const offset: u32 = 26;
1567        pub const mask: u32 = 0x01 << offset;
1568        pub mod R {}
1569        pub mod W {}
1570        pub mod RW {}
1571    }
1572    #[doc = "B Session Valid Interrupt Enable - Read/Write"]
1573    pub mod BSVIE {
1574        pub const offset: u32 = 27;
1575        pub const mask: u32 = 0x01 << offset;
1576        pub mod R {}
1577        pub mod W {}
1578        pub mod RW {}
1579    }
1580    #[doc = "B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt."]
1581    pub mod BSEIE {
1582        pub const offset: u32 = 28;
1583        pub const mask: u32 = 0x01 << offset;
1584        pub mod R {}
1585        pub mod W {}
1586        pub mod RW {}
1587    }
1588    #[doc = "1 millisecond timer Interrupt Enable - Read/Write"]
1589    pub mod EN_1MS {
1590        pub const offset: u32 = 29;
1591        pub const mask: u32 = 0x01 << offset;
1592        pub mod R {}
1593        pub mod W {}
1594        pub mod RW {}
1595    }
1596    #[doc = "Data Pulse Interrupt Enable"]
1597    pub mod DPIE {
1598        pub const offset: u32 = 30;
1599        pub const mask: u32 = 0x01 << offset;
1600        pub mod R {}
1601        pub mod W {}
1602        pub mod RW {}
1603    }
1604}
1605#[doc = "USB Device Mode"]
1606pub mod USBMODE {
1607    #[doc = "Controller Mode - R/WO"]
1608    pub mod CM {
1609        pub const offset: u32 = 0;
1610        pub const mask: u32 = 0x03 << offset;
1611        pub mod R {}
1612        pub mod W {}
1613        pub mod RW {
1614            #[doc = "Idle \\[Default for combination host/device\\]"]
1615            pub const CM_0: u32 = 0;
1616            #[doc = "Device Controller \\[Default for device only controller\\]"]
1617            pub const CM_2: u32 = 0x02;
1618            #[doc = "Host Controller \\[Default for host only controller\\]"]
1619            pub const CM_3: u32 = 0x03;
1620        }
1621    }
1622    #[doc = "Endian Select - Read/Write"]
1623    pub mod ES {
1624        pub const offset: u32 = 2;
1625        pub const mask: u32 = 0x01 << offset;
1626        pub mod R {}
1627        pub mod W {}
1628        pub mod RW {
1629            #[doc = "Little Endian \\[Default\\]"]
1630            pub const ES_0: u32 = 0;
1631            #[doc = "Big Endian"]
1632            pub const ES_1: u32 = 0x01;
1633        }
1634    }
1635    #[doc = "Setup Lockout Mode"]
1636    pub mod SLOM {
1637        pub const offset: u32 = 3;
1638        pub const mask: u32 = 0x01 << offset;
1639        pub mod R {}
1640        pub mod W {}
1641        pub mod RW {
1642            #[doc = "Setup Lockouts On (default);"]
1643            pub const SLOM_0: u32 = 0;
1644            #[doc = "Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register ."]
1645            pub const SLOM_1: u32 = 0x01;
1646        }
1647    }
1648    #[doc = "Stream Disable Mode"]
1649    pub mod SDIS {
1650        pub const offset: u32 = 4;
1651        pub const mask: u32 = 0x01 << offset;
1652        pub mod R {}
1653        pub mod W {}
1654        pub mod RW {}
1655    }
1656}
1657#[doc = "Endpoint Setup Status"]
1658pub mod ENDPTSETUPSTAT {
1659    #[doc = "Setup Endpoint Status"]
1660    pub mod ENDPTSETUPSTAT {
1661        pub const offset: u32 = 0;
1662        pub const mask: u32 = 0xffff << offset;
1663        pub mod R {}
1664        pub mod W {}
1665        pub mod RW {}
1666    }
1667}
1668#[doc = "Endpoint Prime"]
1669pub mod ENDPTPRIME {
1670    #[doc = "Prime Endpoint Receive Buffer - R/WS"]
1671    pub mod PERB {
1672        pub const offset: u32 = 0;
1673        pub const mask: u32 = 0xff << offset;
1674        pub mod R {}
1675        pub mod W {}
1676        pub mod RW {}
1677    }
1678    #[doc = "Prime Endpoint Transmit Buffer - R/WS"]
1679    pub mod PETB {
1680        pub const offset: u32 = 16;
1681        pub const mask: u32 = 0xff << offset;
1682        pub mod R {}
1683        pub mod W {}
1684        pub mod RW {}
1685    }
1686}
1687#[doc = "Endpoint Flush"]
1688pub mod ENDPTFLUSH {
1689    #[doc = "Flush Endpoint Receive Buffer - R/WS"]
1690    pub mod FERB {
1691        pub const offset: u32 = 0;
1692        pub const mask: u32 = 0xff << offset;
1693        pub mod R {}
1694        pub mod W {}
1695        pub mod RW {}
1696    }
1697    #[doc = "Flush Endpoint Transmit Buffer - R/WS"]
1698    pub mod FETB {
1699        pub const offset: u32 = 16;
1700        pub const mask: u32 = 0xff << offset;
1701        pub mod R {}
1702        pub mod W {}
1703        pub mod RW {}
1704    }
1705}
1706#[doc = "Endpoint Status"]
1707pub mod ENDPTSTAT {
1708    #[doc = "Endpoint Receive Buffer Ready -- Read Only"]
1709    pub mod ERBR {
1710        pub const offset: u32 = 0;
1711        pub const mask: u32 = 0xff << offset;
1712        pub mod R {}
1713        pub mod W {}
1714        pub mod RW {}
1715    }
1716    #[doc = "Endpoint Transmit Buffer Ready -- Read Only"]
1717    pub mod ETBR {
1718        pub const offset: u32 = 16;
1719        pub const mask: u32 = 0xff << offset;
1720        pub mod R {}
1721        pub mod W {}
1722        pub mod RW {}
1723    }
1724}
1725#[doc = "Endpoint Complete"]
1726pub mod ENDPTCOMPLETE {
1727    #[doc = "Endpoint Receive Complete Event - RW/C"]
1728    pub mod ERCE {
1729        pub const offset: u32 = 0;
1730        pub const mask: u32 = 0xff << offset;
1731        pub mod R {}
1732        pub mod W {}
1733        pub mod RW {}
1734    }
1735    #[doc = "Endpoint Transmit Complete Event - R/WC"]
1736    pub mod ETCE {
1737        pub const offset: u32 = 16;
1738        pub const mask: u32 = 0xff << offset;
1739        pub mod R {}
1740        pub mod W {}
1741        pub mod RW {}
1742    }
1743}
1744#[doc = "Endpoint Control0"]
1745pub mod ENDPTCTRL0 {
1746    #[doc = "RX Endpoint Stall - Read/Write 0 End Point OK"]
1747    pub mod RXS {
1748        pub const offset: u32 = 0;
1749        pub const mask: u32 = 0x01 << offset;
1750        pub mod R {}
1751        pub mod W {}
1752        pub mod RW {}
1753    }
1754    #[doc = "RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point."]
1755    pub mod RXT {
1756        pub const offset: u32 = 2;
1757        pub const mask: u32 = 0x03 << offset;
1758        pub mod R {}
1759        pub mod W {}
1760        pub mod RW {}
1761    }
1762    #[doc = "RX Endpoint Enable 1 Enabled Endpoint0 is always enabled."]
1763    pub mod RXE {
1764        pub const offset: u32 = 7;
1765        pub const mask: u32 = 0x01 << offset;
1766        pub mod R {}
1767        pub mod W {}
1768        pub mod RW {}
1769    }
1770    #[doc = "TX Endpoint Stall - Read/Write 0 End Point OK \\[Default\\] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host"]
1771    pub mod TXS {
1772        pub const offset: u32 = 16;
1773        pub const mask: u32 = 0x01 << offset;
1774        pub mod R {}
1775        pub mod W {}
1776        pub mod RW {}
1777    }
1778    #[doc = "TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point."]
1779    pub mod TXT {
1780        pub const offset: u32 = 18;
1781        pub const mask: u32 = 0x03 << offset;
1782        pub mod R {}
1783        pub mod W {}
1784        pub mod RW {}
1785    }
1786    #[doc = "TX Endpoint Enable 1 Enabled Endpoint0 is always enabled."]
1787    pub mod TXE {
1788        pub const offset: u32 = 23;
1789        pub const mask: u32 = 0x01 << offset;
1790        pub mod R {}
1791        pub mod W {}
1792        pub mod RW {}
1793    }
1794}
1795#[doc = "Endpoint Control"]
1796pub mod ENDPTCTRL {
1797    #[doc = "RX Endpoint Stall - Read/Write 0 End Point OK"]
1798    pub mod RXS {
1799        pub const offset: u32 = 0;
1800        pub const mask: u32 = 0x01 << offset;
1801        pub mod R {}
1802        pub mod W {}
1803        pub mod RW {}
1804    }
1805    #[doc = "RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine \\[Default\\] Should always be written as zero"]
1806    pub mod RXD {
1807        pub const offset: u32 = 1;
1808        pub const mask: u32 = 0x01 << offset;
1809        pub mod R {}
1810        pub mod W {}
1811        pub mod RW {}
1812    }
1813    #[doc = "RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
1814    pub mod RXT {
1815        pub const offset: u32 = 2;
1816        pub const mask: u32 = 0x03 << offset;
1817        pub mod R {}
1818        pub mod W {}
1819        pub mod RW {}
1820    }
1821    #[doc = "RX Data Toggle Inhibit 0 Disabled \\[Default\\] 1 Enabled This bit is only used for test and should always be written as zero"]
1822    pub mod RXI {
1823        pub const offset: u32 = 5;
1824        pub const mask: u32 = 0x01 << offset;
1825        pub mod R {}
1826        pub mod W {}
1827        pub mod RW {}
1828    }
1829    #[doc = "RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device"]
1830    pub mod RXR {
1831        pub const offset: u32 = 6;
1832        pub const mask: u32 = 0x01 << offset;
1833        pub mod R {}
1834        pub mod W {}
1835        pub mod RW {}
1836    }
1837    #[doc = "RX Endpoint Enable 0 Disabled \\[Default\\] 1 Enabled An Endpoint should be enabled only after it has been configured"]
1838    pub mod RXE {
1839        pub const offset: u32 = 7;
1840        pub const mask: u32 = 0x01 << offset;
1841        pub mod R {}
1842        pub mod W {}
1843        pub mod RW {}
1844    }
1845    #[doc = "TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared"]
1846    pub mod TXS {
1847        pub const offset: u32 = 16;
1848        pub const mask: u32 = 0x01 << offset;
1849        pub mod R {}
1850        pub mod W {}
1851        pub mod RW {}
1852    }
1853    #[doc = "TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine \\[DEFAULT\\] Should always be written as 0"]
1854    pub mod TXD {
1855        pub const offset: u32 = 17;
1856        pub const mask: u32 = 0x01 << offset;
1857        pub mod R {}
1858        pub mod W {}
1859        pub mod RW {}
1860    }
1861    #[doc = "TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
1862    pub mod TXT {
1863        pub const offset: u32 = 18;
1864        pub const mask: u32 = 0x03 << offset;
1865        pub mod R {}
1866        pub mod W {}
1867        pub mod RW {}
1868    }
1869    #[doc = "TX Data Toggle Inhibit 0 PID Sequencing Enabled"]
1870    pub mod TXI {
1871        pub const offset: u32 = 21;
1872        pub const mask: u32 = 0x01 << offset;
1873        pub mod R {}
1874        pub mod W {}
1875        pub mod RW {}
1876    }
1877    #[doc = "TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device"]
1878    pub mod TXR {
1879        pub const offset: u32 = 22;
1880        pub const mask: u32 = 0x01 << offset;
1881        pub mod R {}
1882        pub mod W {}
1883        pub mod RW {}
1884    }
1885    #[doc = "TX Endpoint Enable 0 Disabled \\[Default\\] 1 Enabled An Endpoint should be enabled only after it has been configured"]
1886    pub mod TXE {
1887        pub const offset: u32 = 23;
1888        pub const mask: u32 = 0x01 << offset;
1889        pub mod R {}
1890        pub mod W {}
1891        pub mod RW {}
1892    }
1893}
imxrt_ral/blocks/imxrt1011/usb.rs

imxrt_ral/blocks/imxrt1011/
usb.rs
