rp2040_pac/usbctrl_dpram/
ep_control.rs

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1#[doc = "Register `EP_CONTROL%s` reader"]
2pub type R = crate::R<EP_CONTROL_SPEC>;
3#[doc = "Register `EP_CONTROL%s` writer"]
4pub type W = crate::W<EP_CONTROL_SPEC>;
5#[doc = "Field `BUFFER_ADDRESS` reader - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
6pub type BUFFER_ADDRESS_R = crate::FieldReader<u16>;
7#[doc = "Field `BUFFER_ADDRESS` writer - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
8pub type BUFFER_ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `INTERRUPT_ON_NAK` reader - Trigger an interrupt if a NAK is sent. Intended for debug only."]
10pub type INTERRUPT_ON_NAK_R = crate::BitReader;
11#[doc = "Field `INTERRUPT_ON_NAK` writer - Trigger an interrupt if a NAK is sent. Intended for debug only."]
12pub type INTERRUPT_ON_NAK_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `HOST_POLL_INTERVAL` reader - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms."]
14pub type HOST_POLL_INTERVAL_R = crate::FieldReader<u16>;
15#[doc = "Field `HOST_POLL_INTERVAL` writer - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms."]
16pub type HOST_POLL_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
17#[doc = "Field `INTERRUPT_ON_STALL` reader - Trigger an interrupt if a STALL is sent. Intended for debug only."]
18pub type INTERRUPT_ON_STALL_R = crate::BitReader;
19#[doc = "Field `INTERRUPT_ON_STALL` writer - Trigger an interrupt if a STALL is sent. Intended for debug only."]
20pub type INTERRUPT_ON_STALL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ENDPOINT_TYPE` reader - "]
22pub type ENDPOINT_TYPE_R = crate::FieldReader<ENDPOINT_TYPE_A>;
23#[doc = "  
24
25Value on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27#[repr(u8)]
28pub enum ENDPOINT_TYPE_A {
29    #[doc = "0: `0`"]
30    CONTROL = 0,
31    #[doc = "1: `1`"]
32    ISOCHRONOUS = 1,
33    #[doc = "2: `10`"]
34    BULK = 2,
35    #[doc = "3: `11`"]
36    INTERRUPT = 3,
37}
38impl From<ENDPOINT_TYPE_A> for u8 {
39    #[inline(always)]
40    fn from(variant: ENDPOINT_TYPE_A) -> Self {
41        variant as _
42    }
43}
44impl crate::FieldSpec for ENDPOINT_TYPE_A {
45    type Ux = u8;
46}
47impl ENDPOINT_TYPE_R {
48    #[doc = "Get enumerated values variant"]
49    #[inline(always)]
50    pub const fn variant(&self) -> ENDPOINT_TYPE_A {
51        match self.bits {
52            0 => ENDPOINT_TYPE_A::CONTROL,
53            1 => ENDPOINT_TYPE_A::ISOCHRONOUS,
54            2 => ENDPOINT_TYPE_A::BULK,
55            3 => ENDPOINT_TYPE_A::INTERRUPT,
56            _ => unreachable!(),
57        }
58    }
59    #[doc = "`0`"]
60    #[inline(always)]
61    pub fn is_control(&self) -> bool {
62        *self == ENDPOINT_TYPE_A::CONTROL
63    }
64    #[doc = "`1`"]
65    #[inline(always)]
66    pub fn is_isochronous(&self) -> bool {
67        *self == ENDPOINT_TYPE_A::ISOCHRONOUS
68    }
69    #[doc = "`10`"]
70    #[inline(always)]
71    pub fn is_bulk(&self) -> bool {
72        *self == ENDPOINT_TYPE_A::BULK
73    }
74    #[doc = "`11`"]
75    #[inline(always)]
76    pub fn is_interrupt(&self) -> bool {
77        *self == ENDPOINT_TYPE_A::INTERRUPT
78    }
79}
80#[doc = "Field `ENDPOINT_TYPE` writer - "]
81pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ENDPOINT_TYPE_A>;
82impl<'a, REG> ENDPOINT_TYPE_W<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn control(self) -> &'a mut crate::W<REG> {
90        self.variant(ENDPOINT_TYPE_A::CONTROL)
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn isochronous(self) -> &'a mut crate::W<REG> {
95        self.variant(ENDPOINT_TYPE_A::ISOCHRONOUS)
96    }
97    #[doc = "`10`"]
98    #[inline(always)]
99    pub fn bulk(self) -> &'a mut crate::W<REG> {
100        self.variant(ENDPOINT_TYPE_A::BULK)
101    }
102    #[doc = "`11`"]
103    #[inline(always)]
104    pub fn interrupt(self) -> &'a mut crate::W<REG> {
105        self.variant(ENDPOINT_TYPE_A::INTERRUPT)
106    }
107}
108#[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` reader - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
109pub type INTERRUPT_PER_DOUBLE_BUFF_R = crate::BitReader;
110#[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` writer - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
111pub type INTERRUPT_PER_DOUBLE_BUFF_W<'a, REG> = crate::BitWriter<'a, REG>;
112#[doc = "Field `INTERRUPT_PER_BUFF` reader - Trigger an interrupt each time a buffer is done."]
113pub type INTERRUPT_PER_BUFF_R = crate::BitReader;
114#[doc = "Field `INTERRUPT_PER_BUFF` writer - Trigger an interrupt each time a buffer is done."]
115pub type INTERRUPT_PER_BUFF_W<'a, REG> = crate::BitWriter<'a, REG>;
116#[doc = "Field `DOUBLE_BUFFERED` reader - This endpoint is double buffered."]
117pub type DOUBLE_BUFFERED_R = crate::BitReader;
118#[doc = "Field `DOUBLE_BUFFERED` writer - This endpoint is double buffered."]
119pub type DOUBLE_BUFFERED_W<'a, REG> = crate::BitWriter<'a, REG>;
120#[doc = "Field `ENABLE` reader - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
121pub type ENABLE_R = crate::BitReader;
122#[doc = "Field `ENABLE` writer - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
123pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
124impl R {
125    #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
126    #[inline(always)]
127    pub fn buffer_address(&self) -> BUFFER_ADDRESS_R {
128        BUFFER_ADDRESS_R::new((self.bits & 0xffff) as u16)
129    }
130    #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."]
131    #[inline(always)]
132    pub fn interrupt_on_nak(&self) -> INTERRUPT_ON_NAK_R {
133        INTERRUPT_ON_NAK_R::new(((self.bits >> 16) & 1) != 0)
134    }
135    #[doc = "Bits 16:25 - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms."]
136    #[inline(always)]
137    pub fn host_poll_interval(&self) -> HOST_POLL_INTERVAL_R {
138        HOST_POLL_INTERVAL_R::new(((self.bits >> 16) & 0x03ff) as u16)
139    }
140    #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."]
141    #[inline(always)]
142    pub fn interrupt_on_stall(&self) -> INTERRUPT_ON_STALL_R {
143        INTERRUPT_ON_STALL_R::new(((self.bits >> 17) & 1) != 0)
144    }
145    #[doc = "Bits 26:27"]
146    #[inline(always)]
147    pub fn endpoint_type(&self) -> ENDPOINT_TYPE_R {
148        ENDPOINT_TYPE_R::new(((self.bits >> 26) & 3) as u8)
149    }
150    #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
151    #[inline(always)]
152    pub fn interrupt_per_double_buff(&self) -> INTERRUPT_PER_DOUBLE_BUFF_R {
153        INTERRUPT_PER_DOUBLE_BUFF_R::new(((self.bits >> 28) & 1) != 0)
154    }
155    #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."]
156    #[inline(always)]
157    pub fn interrupt_per_buff(&self) -> INTERRUPT_PER_BUFF_R {
158        INTERRUPT_PER_BUFF_R::new(((self.bits >> 29) & 1) != 0)
159    }
160    #[doc = "Bit 30 - This endpoint is double buffered."]
161    #[inline(always)]
162    pub fn double_buffered(&self) -> DOUBLE_BUFFERED_R {
163        DOUBLE_BUFFERED_R::new(((self.bits >> 30) & 1) != 0)
164    }
165    #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
166    #[inline(always)]
167    pub fn enable(&self) -> ENABLE_R {
168        ENABLE_R::new(((self.bits >> 31) & 1) != 0)
169    }
170}
171impl W {
172    #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
173    #[inline(always)]
174    #[must_use]
175    pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W<EP_CONTROL_SPEC> {
176        BUFFER_ADDRESS_W::new(self, 0)
177    }
178    #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."]
179    #[inline(always)]
180    #[must_use]
181    pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W<EP_CONTROL_SPEC> {
182        INTERRUPT_ON_NAK_W::new(self, 16)
183    }
184    #[doc = "Bits 16:25 - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms."]
185    #[inline(always)]
186    #[must_use]
187    pub fn host_poll_interval(&mut self) -> HOST_POLL_INTERVAL_W<EP_CONTROL_SPEC> {
188        HOST_POLL_INTERVAL_W::new(self, 16)
189    }
190    #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."]
191    #[inline(always)]
192    #[must_use]
193    pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W<EP_CONTROL_SPEC> {
194        INTERRUPT_ON_STALL_W::new(self, 17)
195    }
196    #[doc = "Bits 26:27"]
197    #[inline(always)]
198    #[must_use]
199    pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W<EP_CONTROL_SPEC> {
200        ENDPOINT_TYPE_W::new(self, 26)
201    }
202    #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
203    #[inline(always)]
204    #[must_use]
205    pub fn interrupt_per_double_buff(&mut self) -> INTERRUPT_PER_DOUBLE_BUFF_W<EP_CONTROL_SPEC> {
206        INTERRUPT_PER_DOUBLE_BUFF_W::new(self, 28)
207    }
208    #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."]
209    #[inline(always)]
210    #[must_use]
211    pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W<EP_CONTROL_SPEC> {
212        INTERRUPT_PER_BUFF_W::new(self, 29)
213    }
214    #[doc = "Bit 30 - This endpoint is double buffered."]
215    #[inline(always)]
216    #[must_use]
217    pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W<EP_CONTROL_SPEC> {
218        DOUBLE_BUFFERED_W::new(self, 30)
219    }
220    #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
221    #[inline(always)]
222    #[must_use]
223    pub fn enable(&mut self) -> ENABLE_W<EP_CONTROL_SPEC> {
224        ENABLE_W::new(self, 31)
225    }
226    #[doc = r" Writes raw bits to the register."]
227    #[doc = r""]
228    #[doc = r" # Safety"]
229    #[doc = r""]
230    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
231    #[inline(always)]
232    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
233        self.bits = bits;
234        self
235    }
236}
237#[doc = "-  
238
239You can [`read`](crate::generic::Reg::read) this register and get [`ep_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
240pub struct EP_CONTROL_SPEC;
241impl crate::RegisterSpec for EP_CONTROL_SPEC {
242    type Ux = u32;
243}
244#[doc = "`read()` method returns [`ep_control::R`](R) reader structure"]
245impl crate::Readable for EP_CONTROL_SPEC {}
246#[doc = "`write(|w| ..)` method takes [`ep_control::W`](W) writer structure"]
247impl crate::Writable for EP_CONTROL_SPEC {
248    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
249    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
250}
251#[doc = "`reset()` method sets EP_CONTROL%s to value 0"]
252impl crate::Resettable for EP_CONTROL_SPEC {
253    const RESET_VALUE: u32 = 0;
254}
rp2040_pac/usbctrl_dpram/ep_control.rs

rp2040_pac/usbctrl_dpram/
ep_control.rs
