imxrt_ral/blocks/imxrt1011/
flexspi.rs1#[doc = "FlexSPI"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Module Control Register 0"]
5 pub MCR0: crate::RWRegister<u32>,
6 #[doc = "Module Control Register 1"]
7 pub MCR1: crate::RWRegister<u32>,
8 #[doc = "Module Control Register 2"]
9 pub MCR2: crate::RWRegister<u32>,
10 #[doc = "AHB Bus Control Register"]
11 pub AHBCR: crate::RWRegister<u32>,
12 #[doc = "Interrupt Enable Register"]
13 pub INTEN: crate::RWRegister<u32>,
14 #[doc = "Interrupt Register"]
15 pub INTR: crate::RWRegister<u32>,
16 #[doc = "LUT Key Register"]
17 pub LUTKEY: crate::RWRegister<u32>,
18 #[doc = "LUT Control Register"]
19 pub LUTCR: crate::RWRegister<u32>,
20 #[doc = "AHB RX Buffer 0 Control Register 0"]
21 pub AHBRXBUF0CR0: crate::RWRegister<u32>,
22 #[doc = "AHB RX Buffer 1 Control Register 0"]
23 pub AHBRXBUF1CR0: crate::RWRegister<u32>,
24 #[doc = "AHB RX Buffer 2 Control Register 0"]
25 pub AHBRXBUF2CR0: crate::RWRegister<u32>,
26 #[doc = "AHB RX Buffer 3 Control Register 0"]
27 pub AHBRXBUF3CR0: crate::RWRegister<u32>,
28 _reserved0: [u8; 0x30],
29 #[doc = "Flash Control Register 0"]
30 pub FLSHA1CR0: crate::RWRegister<u32>,
31 #[doc = "Flash Control Register 0"]
32 pub FLSHA2CR0: crate::RWRegister<u32>,
33 #[doc = "Flash Control Register 0"]
34 pub FLSHB1CR0: crate::RWRegister<u32>,
35 #[doc = "Flash Control Register 0"]
36 pub FLSHB2CR0: crate::RWRegister<u32>,
37 #[doc = "Flash Control Register 1"]
38 pub FLSHCR1: [crate::RWRegister<u32>; 4usize],
39 #[doc = "Flash Control Register 2"]
40 pub FLSHCR2: [crate::RWRegister<u32>; 4usize],
41 _reserved1: [u8; 0x04],
42 #[doc = "Flash Control Register 4"]
43 pub FLSHCR4: crate::RWRegister<u32>,
44 _reserved2: [u8; 0x08],
45 #[doc = "IP Control Register 0"]
46 pub IPCR0: crate::RWRegister<u32>,
47 #[doc = "IP Control Register 1"]
48 pub IPCR1: crate::RWRegister<u32>,
49 _reserved3: [u8; 0x08],
50 #[doc = "IP Command Register"]
51 pub IPCMD: crate::RWRegister<u32>,
52 _reserved4: [u8; 0x04],
53 #[doc = "IP RX FIFO Control Register"]
54 pub IPRXFCR: crate::RWRegister<u32>,
55 #[doc = "IP TX FIFO Control Register"]
56 pub IPTXFCR: crate::RWRegister<u32>,
57 #[doc = "DLL Control Register 0"]
58 pub DLLCR: [crate::RWRegister<u32>; 2usize],
59 _reserved5: [u8; 0x18],
60 #[doc = "Status Register 0"]
61 pub STS0: crate::RORegister<u32>,
62 #[doc = "Status Register 1"]
63 pub STS1: crate::RORegister<u32>,
64 #[doc = "Status Register 2"]
65 pub STS2: crate::RORegister<u32>,
66 #[doc = "AHB Suspend Status Register"]
67 pub AHBSPNDSTS: crate::RORegister<u32>,
68 #[doc = "IP RX FIFO Status Register"]
69 pub IPRXFSTS: crate::RORegister<u32>,
70 #[doc = "IP TX FIFO Status Register"]
71 pub IPTXFSTS: crate::RORegister<u32>,
72 _reserved6: [u8; 0x08],
73 #[doc = "IP RX FIFO Data Register 0"]
74 pub RFDR: [crate::RORegister<u32>; 32usize],
75 #[doc = "IP TX FIFO Data Register 0"]
76 pub TFDR: [crate::WORegister<u32>; 32usize],
77 #[doc = "LUT 0"]
78 pub LUT: [crate::RWRegister<u32>; 64usize],
79}
80#[doc = "Module Control Register 0"]
81pub mod MCR0 {
82 #[doc = "Software Reset"]
83 pub mod SWRESET {
84 pub const offset: u32 = 0;
85 pub const mask: u32 = 0x01 << offset;
86 pub mod R {}
87 pub mod W {}
88 pub mod RW {}
89 }
90 #[doc = "Module Disable"]
91 pub mod MDIS {
92 pub const offset: u32 = 1;
93 pub const mask: u32 = 0x01 << offset;
94 pub mod R {}
95 pub mod W {}
96 pub mod RW {}
97 }
98 #[doc = "Sample Clock source selection for Flash Reading"]
99 pub mod RXCLKSRC {
100 pub const offset: u32 = 4;
101 pub const mask: u32 = 0x03 << offset;
102 pub mod R {}
103 pub mod W {}
104 pub mod RW {
105 #[doc = "Dummy Read strobe generated by FlexSPI Controller and loopback internally."]
106 pub const RXCLKSRC_0: u32 = 0;
107 #[doc = "Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad."]
108 pub const RXCLKSRC_1: u32 = 0x01;
109 #[doc = "Flash provided Read strobe and input from DQS pad"]
110 pub const RXCLKSRC_3: u32 = 0x03;
111 }
112 }
113 #[doc = "Enable AHB bus Read Access to IP RX FIFO."]
114 pub mod ARDFEN {
115 pub const offset: u32 = 6;
116 pub const mask: u32 = 0x01 << offset;
117 pub mod R {}
118 pub mod W {}
119 pub mod RW {
120 #[doc = "IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response."]
121 pub const ARDFEN_0: u32 = 0;
122 #[doc = "IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response."]
123 pub const ARDFEN_1: u32 = 0x01;
124 }
125 }
126 #[doc = "Enable AHB bus Write Access to IP TX FIFO."]
127 pub mod ATDFEN {
128 pub const offset: u32 = 7;
129 pub const mask: u32 = 0x01 << offset;
130 pub mod R {}
131 pub mod W {}
132 pub mod RW {
133 #[doc = "IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response."]
134 pub const ATDFEN_0: u32 = 0;
135 #[doc = "IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response."]
136 pub const ATDFEN_1: u32 = 0x01;
137 }
138 }
139 #[doc = "The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking."]
140 pub mod SERCLKDIV {
141 pub const offset: u32 = 8;
142 pub const mask: u32 = 0x07 << offset;
143 pub mod R {}
144 pub mod W {}
145 pub mod RW {
146 #[doc = "Divided by 1"]
147 pub const SERCLKDIV_0: u32 = 0;
148 #[doc = "Divided by 2"]
149 pub const SERCLKDIV_1: u32 = 0x01;
150 #[doc = "Divided by 3"]
151 pub const SERCLKDIV_2: u32 = 0x02;
152 #[doc = "Divided by 4"]
153 pub const SERCLKDIV_3: u32 = 0x03;
154 #[doc = "Divided by 5"]
155 pub const SERCLKDIV_4: u32 = 0x04;
156 #[doc = "Divided by 6"]
157 pub const SERCLKDIV_5: u32 = 0x05;
158 #[doc = "Divided by 7"]
159 pub const SERCLKDIV_6: u32 = 0x06;
160 #[doc = "Divided by 8"]
161 pub const SERCLKDIV_7: u32 = 0x07;
162 }
163 }
164 #[doc = "Half Speed Serial Flash access Enable."]
165 pub mod HSEN {
166 pub const offset: u32 = 11;
167 pub const mask: u32 = 0x01 << offset;
168 pub mod R {}
169 pub mod W {}
170 pub mod RW {
171 #[doc = "Disable divide by 2 of serial flash clock for half speed commands."]
172 pub const HSEN_0: u32 = 0;
173 #[doc = "Enable divide by 2 of serial flash clock for half speed commands."]
174 pub const HSEN_1: u32 = 0x01;
175 }
176 }
177 #[doc = "Doze mode enable bit"]
178 pub mod DOZEEN {
179 pub const offset: u32 = 12;
180 pub const mask: u32 = 0x01 << offset;
181 pub mod R {}
182 pub mod W {}
183 pub mod RW {
184 #[doc = "Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system."]
185 pub const DOZEEN_0: u32 = 0;
186 #[doc = "Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system."]
187 pub const DOZEEN_1: u32 = 0x01;
188 }
189 }
190 #[doc = "This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA\\[3:0\\] and B_DATA\\[3:0\\])."]
191 pub mod COMBINATIONEN {
192 pub const offset: u32 = 13;
193 pub const mask: u32 = 0x01 << offset;
194 pub mod R {}
195 pub mod W {}
196 pub mod RW {
197 #[doc = "Disable."]
198 pub const COMBINATIONEN_0: u32 = 0;
199 #[doc = "Enable."]
200 pub const COMBINATIONEN_1: u32 = 0x01;
201 }
202 }
203 #[doc = "This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0\\[RXCLKSRC\\]=2)."]
204 pub mod SCKFREERUNEN {
205 pub const offset: u32 = 14;
206 pub const mask: u32 = 0x01 << offset;
207 pub mod R {}
208 pub mod W {}
209 pub mod RW {
210 #[doc = "Disable."]
211 pub const SCKFREERUNEN_0: u32 = 0;
212 #[doc = "Enable."]
213 pub const SCKFREERUNEN_1: u32 = 0x01;
214 }
215 }
216 #[doc = "Time out wait cycle for IP command grant."]
217 pub mod IPGRANTWAIT {
218 pub const offset: u32 = 16;
219 pub const mask: u32 = 0xff << offset;
220 pub mod R {}
221 pub mod W {}
222 pub mod RW {}
223 }
224 #[doc = "Timeout wait cycle for AHB command grant."]
225 pub mod AHBGRANTWAIT {
226 pub const offset: u32 = 24;
227 pub const mask: u32 = 0xff << offset;
228 pub mod R {}
229 pub mod W {}
230 pub mod RW {}
231 }
232}
233#[doc = "Module Control Register 1"]
234pub mod MCR1 {
235 #[doc = "AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response"]
236 pub mod AHBBUSWAIT {
237 pub const offset: u32 = 0;
238 pub const mask: u32 = 0xffff << offset;
239 pub mod R {}
240 pub mod W {}
241 pub mod RW {}
242 }
243 #[doc = "Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"]
244 pub mod SEQWAIT {
245 pub const offset: u32 = 16;
246 pub const mask: u32 = 0xffff << offset;
247 pub mod R {}
248 pub mod W {}
249 pub mod RW {}
250 }
251}
252#[doc = "Module Control Register 2"]
253pub mod MCR2 {
254 #[doc = "This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid."]
255 pub mod CLRAHBBUFOPT {
256 pub const offset: u32 = 11;
257 pub const mask: u32 = 0x01 << offset;
258 pub mod R {}
259 pub mod W {}
260 pub mod RW {
261 #[doc = "AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK."]
262 pub const CLRAHBBUFOPT_0: u32 = 0;
263 #[doc = "AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK."]
264 pub const CLRAHBBUFOPT_1: u32 = 0x01;
265 }
266 }
267 #[doc = "The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
268 pub mod CLRLEARNPHASE {
269 pub const offset: u32 = 14;
270 pub const mask: u32 = 0x01 << offset;
271 pub mod R {}
272 pub mod W {}
273 pub mod RW {}
274 }
275 #[doc = "All external devices are same devices (both in types and size) for A1/A2/B1/B2."]
276 pub mod SAMEDEVICEEN {
277 pub const offset: u32 = 15;
278 pub const mask: u32 = 0x01 << offset;
279 pub mod R {}
280 pub mod W {}
281 pub mod RW {
282 #[doc = "In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored."]
283 pub const SAMEDEVICEEN_0: u32 = 0;
284 #[doc = "FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored."]
285 pub const SAMEDEVICEEN_1: u32 = 0x01;
286 }
287 }
288 #[doc = "B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0\\[SWRESET\\] should be set."]
289 pub mod SCKBDIFFOPT {
290 pub const offset: u32 = 19;
291 pub const mask: u32 = 0x01 << offset;
292 pub mod R {}
293 pub mod W {}
294 pub mod RW {
295 #[doc = "B_SCLK pad is used as port B SCLK clock output. Port B flash access is available."]
296 pub const SCKBDIFFOPT_0: u32 = 0;
297 #[doc = "B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available."]
298 pub const SCKBDIFFOPT_1: u32 = 0x01;
299 }
300 }
301 #[doc = "Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed."]
302 pub mod RESUMEWAIT {
303 pub const offset: u32 = 24;
304 pub const mask: u32 = 0xff << offset;
305 pub mod R {}
306 pub mod W {}
307 pub mod RW {}
308 }
309}
310#[doc = "AHB Bus Control Register"]
311pub mod AHBCR {
312 #[doc = "Parallel mode enabled for AHB triggered Command (both read and write) ."]
313 pub mod APAREN {
314 pub const offset: u32 = 0;
315 pub const mask: u32 = 0x01 << offset;
316 pub mod R {}
317 pub mod W {}
318 pub mod RW {
319 #[doc = "Flash will be accessed in Individual mode."]
320 pub const APAREN_0: u32 = 0;
321 #[doc = "Flash will be accessed in Parallel mode."]
322 pub const APAREN_1: u32 = 0x01;
323 }
324 }
325 #[doc = "Clear the status/pointers of AHB RX Buffer. Auto-cleared."]
326 pub mod CLRAHBRXBUF {
327 pub const offset: u32 = 1;
328 pub const mask: u32 = 0x01 << offset;
329 pub mod R {}
330 pub mod W {}
331 pub mod RW {}
332 }
333 #[doc = "Clear the status/pointers of AHB TX Buffer. Auto-cleared."]
334 pub mod CLRAHBTXBUF {
335 pub const offset: u32 = 2;
336 pub const mask: u32 = 0x01 << offset;
337 pub mod R {}
338 pub mod W {}
339 pub mod RW {}
340 }
341 #[doc = "Enable AHB bus cachable read access support."]
342 pub mod CACHABLEEN {
343 pub const offset: u32 = 3;
344 pub const mask: u32 = 0x01 << offset;
345 pub mod R {}
346 pub mod W {}
347 pub mod RW {
348 #[doc = "Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer."]
349 pub const CACHABLEEN_0: u32 = 0;
350 #[doc = "Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first."]
351 pub const CACHABLEEN_1: u32 = 0x01;
352 }
353 }
354 #[doc = "Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write."]
355 pub mod BUFFERABLEEN {
356 pub const offset: u32 = 4;
357 pub const mask: u32 = 0x01 << offset;
358 pub mod R {}
359 pub mod W {}
360 pub mod RW {
361 #[doc = "Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished."]
362 pub const BUFFERABLEEN_0: u32 = 0;
363 #[doc = "Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished."]
364 pub const BUFFERABLEEN_1: u32 = 0x01;
365 }
366 }
367 #[doc = "AHB Read Prefetch Enable."]
368 pub mod PREFETCHEN {
369 pub const offset: u32 = 5;
370 pub const mask: u32 = 0x01 << offset;
371 pub mod R {}
372 pub mod W {}
373 pub mod RW {}
374 }
375 #[doc = "AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation."]
376 pub mod READADDROPT {
377 pub const offset: u32 = 6;
378 pub const mask: u32 = 0x01 << offset;
379 pub mod R {}
380 pub mod W {}
381 pub mod RW {
382 #[doc = "There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable."]
383 pub const READADDROPT_0: u32 = 0;
384 #[doc = "There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement."]
385 pub const READADDROPT_1: u32 = 0x01;
386 }
387 }
388 #[doc = "AHB Read Size Alignment"]
389 pub mod READSZALIGN {
390 pub const offset: u32 = 10;
391 pub const mask: u32 = 0x01 << offset;
392 pub mod R {}
393 pub mod W {}
394 pub mod RW {
395 #[doc = "AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN..."]
396 pub const READSZALIGN_0: u32 = 0;
397 #[doc = "AHB read size to up size to 8 bytes aligned, no prefetching"]
398 pub const READSZALIGN_1: u32 = 0x01;
399 }
400 }
401}
402#[doc = "Interrupt Enable Register"]
403pub mod INTEN {
404 #[doc = "IP triggered Command Sequences Execution finished interrupt enable."]
405 pub mod IPCMDDONEEN {
406 pub const offset: u32 = 0;
407 pub const mask: u32 = 0x01 << offset;
408 pub mod R {}
409 pub mod W {}
410 pub mod RW {}
411 }
412 #[doc = "IP triggered Command Sequences Grant Timeout interrupt enable."]
413 pub mod IPCMDGEEN {
414 pub const offset: u32 = 1;
415 pub const mask: u32 = 0x01 << offset;
416 pub mod R {}
417 pub mod W {}
418 pub mod RW {}
419 }
420 #[doc = "AHB triggered Command Sequences Grant Timeout interrupt enable."]
421 pub mod AHBCMDGEEN {
422 pub const offset: u32 = 2;
423 pub const mask: u32 = 0x01 << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {}
427 }
428 #[doc = "IP triggered Command Sequences Error Detected interrupt enable."]
429 pub mod IPCMDERREN {
430 pub const offset: u32 = 3;
431 pub const mask: u32 = 0x01 << offset;
432 pub mod R {}
433 pub mod W {}
434 pub mod RW {}
435 }
436 #[doc = "AHB triggered Command Sequences Error Detected interrupt enable."]
437 pub mod AHBCMDERREN {
438 pub const offset: u32 = 4;
439 pub const mask: u32 = 0x01 << offset;
440 pub mod R {}
441 pub mod W {}
442 pub mod RW {}
443 }
444 #[doc = "IP RX FIFO WaterMark available interrupt enable."]
445 pub mod IPRXWAEN {
446 pub const offset: u32 = 5;
447 pub const mask: u32 = 0x01 << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {}
451 }
452 #[doc = "IP TX FIFO WaterMark empty interrupt enable."]
453 pub mod IPTXWEEN {
454 pub const offset: u32 = 6;
455 pub const mask: u32 = 0x01 << offset;
456 pub mod R {}
457 pub mod W {}
458 pub mod RW {}
459 }
460 #[doc = "SCLK is stopped during command sequence because Async RX FIFO full interrupt enable."]
461 pub mod SCKSTOPBYRDEN {
462 pub const offset: u32 = 8;
463 pub const mask: u32 = 0x01 << offset;
464 pub mod R {}
465 pub mod W {}
466 pub mod RW {}
467 }
468 #[doc = "SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable."]
469 pub mod SCKSTOPBYWREN {
470 pub const offset: u32 = 9;
471 pub const mask: u32 = 0x01 << offset;
472 pub mod R {}
473 pub mod W {}
474 pub mod RW {}
475 }
476 #[doc = "AHB Bus error interrupt enable.Refer Interrupts chapter for more details."]
477 pub mod AHBBUSERROREN {
478 pub const offset: u32 = 10;
479 pub const mask: u32 = 0x01 << offset;
480 pub mod R {}
481 pub mod W {}
482 pub mod RW {}
483 }
484 #[doc = "Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details."]
485 pub mod SEQTIMEOUTEN {
486 pub const offset: u32 = 11;
487 pub const mask: u32 = 0x01 << offset;
488 pub mod R {}
489 pub mod W {}
490 pub mod RW {}
491 }
492 #[doc = "OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details."]
493 pub mod KEYDONEEN {
494 pub const offset: u32 = 12;
495 pub const mask: u32 = 0x01 << offset;
496 pub mod R {}
497 pub mod W {}
498 pub mod RW {}
499 }
500 #[doc = "OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details."]
501 pub mod KEYERROREN {
502 pub const offset: u32 = 13;
503 pub const mask: u32 = 0x01 << offset;
504 pub mod R {}
505 pub mod W {}
506 pub mod RW {}
507 }
508}
509#[doc = "Interrupt Register"]
510pub mod INTR {
511 #[doc = "IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated."]
512 pub mod IPCMDDONE {
513 pub const offset: u32 = 0;
514 pub const mask: u32 = 0x01 << offset;
515 pub mod R {}
516 pub mod W {}
517 pub mod RW {}
518 }
519 #[doc = "IP triggered Command Sequences Grant Timeout interrupt."]
520 pub mod IPCMDGE {
521 pub const offset: u32 = 1;
522 pub const mask: u32 = 0x01 << offset;
523 pub mod R {}
524 pub mod W {}
525 pub mod RW {}
526 }
527 #[doc = "AHB triggered Command Sequences Grant Timeout interrupt."]
528 pub mod AHBCMDGE {
529 pub const offset: u32 = 2;
530 pub const mask: u32 = 0x01 << offset;
531 pub mod R {}
532 pub mod W {}
533 pub mod RW {}
534 }
535 #[doc = "IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all."]
536 pub mod IPCMDERR {
537 pub const offset: u32 = 3;
538 pub const mask: u32 = 0x01 << offset;
539 pub mod R {}
540 pub mod W {}
541 pub mod RW {}
542 }
543 #[doc = "AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all."]
544 pub mod AHBCMDERR {
545 pub const offset: u32 = 4;
546 pub const mask: u32 = 0x01 << offset;
547 pub mod R {}
548 pub mod W {}
549 pub mod RW {}
550 }
551 #[doc = "IP RX FIFO watermark available interrupt."]
552 pub mod IPRXWA {
553 pub const offset: u32 = 5;
554 pub const mask: u32 = 0x01 << offset;
555 pub mod R {}
556 pub mod W {}
557 pub mod RW {}
558 }
559 #[doc = "IP TX FIFO watermark empty interrupt."]
560 pub mod IPTXWE {
561 pub const offset: u32 = 6;
562 pub const mask: u32 = 0x01 << offset;
563 pub mod R {}
564 pub mod W {}
565 pub mod RW {}
566 }
567 #[doc = "SCLK is stopped during command sequence because Async RX FIFO full interrupt."]
568 pub mod SCKSTOPBYRD {
569 pub const offset: u32 = 8;
570 pub const mask: u32 = 0x01 << offset;
571 pub mod R {}
572 pub mod W {}
573 pub mod RW {}
574 }
575 #[doc = "SCLK is stopped during command sequence because Async TX FIFO empty interrupt."]
576 pub mod SCKSTOPBYWR {
577 pub const offset: u32 = 9;
578 pub const mask: u32 = 0x01 << offset;
579 pub mod R {}
580 pub mod W {}
581 pub mod RW {}
582 }
583 #[doc = "AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt."]
584 pub mod AHBBUSERROR {
585 pub const offset: u32 = 10;
586 pub const mask: u32 = 0x01 << offset;
587 pub mod R {}
588 pub mod W {}
589 pub mod RW {}
590 }
591 #[doc = "Sequence execution timeout interrupt."]
592 pub mod SEQTIMEOUT {
593 pub const offset: u32 = 11;
594 pub const mask: u32 = 0x01 << offset;
595 pub mod R {}
596 pub mod W {}
597 pub mod RW {}
598 }
599 #[doc = "OTFAD key blob processing done interrupt."]
600 pub mod KEYDONE {
601 pub const offset: u32 = 12;
602 pub const mask: u32 = 0x01 << offset;
603 pub mod R {}
604 pub mod W {}
605 pub mod RW {}
606 }
607 #[doc = "OTFAD key blob processing error interrupt."]
608 pub mod KEYERROR {
609 pub const offset: u32 = 13;
610 pub const mask: u32 = 0x01 << offset;
611 pub mod R {}
612 pub mod W {}
613 pub mod RW {}
614 }
615}
616#[doc = "LUT Key Register"]
617pub mod LUTKEY {
618 #[doc = "The Key to lock or unlock LUT."]
619 pub mod KEY {
620 pub const offset: u32 = 0;
621 pub const mask: u32 = 0xffff_ffff << offset;
622 pub mod R {}
623 pub mod W {}
624 pub mod RW {}
625 }
626}
627#[doc = "LUT Control Register"]
628pub mod LUTCR {
629 #[doc = "Lock LUT"]
630 pub mod LOCK {
631 pub const offset: u32 = 0;
632 pub const mask: u32 = 0x01 << offset;
633 pub mod R {}
634 pub mod W {}
635 pub mod RW {}
636 }
637 #[doc = "Unlock LUT"]
638 pub mod UNLOCK {
639 pub const offset: u32 = 1;
640 pub const mask: u32 = 0x01 << offset;
641 pub mod R {}
642 pub mod W {}
643 pub mod RW {}
644 }
645}
646#[doc = "AHB RX Buffer 0 Control Register 0"]
647pub mod AHBRXBUF0CR0 {
648 #[doc = "AHB RX Buffer Size in 64 bits."]
649 pub mod BUFSZ {
650 pub const offset: u32 = 0;
651 pub const mask: u32 = 0xff << offset;
652 pub mod R {}
653 pub mod W {}
654 pub mod RW {}
655 }
656 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
657 pub mod MSTRID {
658 pub const offset: u32 = 16;
659 pub const mask: u32 = 0x0f << offset;
660 pub mod R {}
661 pub mod W {}
662 pub mod RW {}
663 }
664 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
665 pub mod PRIORITY {
666 pub const offset: u32 = 24;
667 pub const mask: u32 = 0x03 << offset;
668 pub mod R {}
669 pub mod W {}
670 pub mod RW {}
671 }
672 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
673 pub mod PREFETCHEN {
674 pub const offset: u32 = 31;
675 pub const mask: u32 = 0x01 << offset;
676 pub mod R {}
677 pub mod W {}
678 pub mod RW {}
679 }
680}
681#[doc = "AHB RX Buffer 1 Control Register 0"]
682pub mod AHBRXBUF1CR0 {
683 #[doc = "AHB RX Buffer Size in 64 bits."]
684 pub mod BUFSZ {
685 pub const offset: u32 = 0;
686 pub const mask: u32 = 0xff << offset;
687 pub mod R {}
688 pub mod W {}
689 pub mod RW {}
690 }
691 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
692 pub mod MSTRID {
693 pub const offset: u32 = 16;
694 pub const mask: u32 = 0x0f << offset;
695 pub mod R {}
696 pub mod W {}
697 pub mod RW {}
698 }
699 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
700 pub mod PRIORITY {
701 pub const offset: u32 = 24;
702 pub const mask: u32 = 0x03 << offset;
703 pub mod R {}
704 pub mod W {}
705 pub mod RW {}
706 }
707 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
708 pub mod PREFETCHEN {
709 pub const offset: u32 = 31;
710 pub const mask: u32 = 0x01 << offset;
711 pub mod R {}
712 pub mod W {}
713 pub mod RW {}
714 }
715}
716#[doc = "AHB RX Buffer 2 Control Register 0"]
717pub mod AHBRXBUF2CR0 {
718 #[doc = "AHB RX Buffer Size in 64 bits."]
719 pub mod BUFSZ {
720 pub const offset: u32 = 0;
721 pub const mask: u32 = 0xff << offset;
722 pub mod R {}
723 pub mod W {}
724 pub mod RW {}
725 }
726 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
727 pub mod MSTRID {
728 pub const offset: u32 = 16;
729 pub const mask: u32 = 0x0f << offset;
730 pub mod R {}
731 pub mod W {}
732 pub mod RW {}
733 }
734 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
735 pub mod PRIORITY {
736 pub const offset: u32 = 24;
737 pub const mask: u32 = 0x03 << offset;
738 pub mod R {}
739 pub mod W {}
740 pub mod RW {}
741 }
742 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
743 pub mod PREFETCHEN {
744 pub const offset: u32 = 31;
745 pub const mask: u32 = 0x01 << offset;
746 pub mod R {}
747 pub mod W {}
748 pub mod RW {}
749 }
750}
751#[doc = "AHB RX Buffer 3 Control Register 0"]
752pub mod AHBRXBUF3CR0 {
753 #[doc = "AHB RX Buffer Size in 64 bits."]
754 pub mod BUFSZ {
755 pub const offset: u32 = 0;
756 pub const mask: u32 = 0xff << offset;
757 pub mod R {}
758 pub mod W {}
759 pub mod RW {}
760 }
761 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
762 pub mod MSTRID {
763 pub const offset: u32 = 16;
764 pub const mask: u32 = 0x0f << offset;
765 pub mod R {}
766 pub mod W {}
767 pub mod RW {}
768 }
769 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
770 pub mod PRIORITY {
771 pub const offset: u32 = 24;
772 pub const mask: u32 = 0x03 << offset;
773 pub mod R {}
774 pub mod W {}
775 pub mod RW {}
776 }
777 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
778 pub mod PREFETCHEN {
779 pub const offset: u32 = 31;
780 pub const mask: u32 = 0x01 << offset;
781 pub mod R {}
782 pub mod W {}
783 pub mod RW {}
784 }
785}
786#[doc = "Flash Control Register 0"]
787pub mod FLSHA1CR0 {
788 #[doc = "Flash Size in KByte."]
789 pub mod FLSHSZ {
790 pub const offset: u32 = 0;
791 pub const mask: u32 = 0x007f_ffff << offset;
792 pub mod R {}
793 pub mod W {}
794 pub mod RW {}
795 }
796}
797#[doc = "Flash Control Register 0"]
798pub mod FLSHA2CR0 {
799 #[doc = "Flash Size in KByte."]
800 pub mod FLSHSZ {
801 pub const offset: u32 = 0;
802 pub const mask: u32 = 0x007f_ffff << offset;
803 pub mod R {}
804 pub mod W {}
805 pub mod RW {}
806 }
807}
808#[doc = "Flash Control Register 0"]
809pub mod FLSHB1CR0 {
810 #[doc = "Flash Size in KByte."]
811 pub mod FLSHSZ {
812 pub const offset: u32 = 0;
813 pub const mask: u32 = 0x007f_ffff << offset;
814 pub mod R {}
815 pub mod W {}
816 pub mod RW {}
817 }
818}
819#[doc = "Flash Control Register 0"]
820pub mod FLSHB2CR0 {
821 #[doc = "Flash Size in KByte."]
822 pub mod FLSHSZ {
823 pub const offset: u32 = 0;
824 pub const mask: u32 = 0x007f_ffff << offset;
825 pub mod R {}
826 pub mod W {}
827 pub mod RW {}
828 }
829}
830#[doc = "Flash Control Register 1"]
831pub mod FLSHCR1 {
832 #[doc = "Serial Flash CS setup time."]
833 pub mod TCSS {
834 pub const offset: u32 = 0;
835 pub const mask: u32 = 0x1f << offset;
836 pub mod R {}
837 pub mod W {}
838 pub mod RW {}
839 }
840 #[doc = "Serial Flash CS Hold time."]
841 pub mod TCSH {
842 pub const offset: u32 = 5;
843 pub const mask: u32 = 0x1f << offset;
844 pub mod R {}
845 pub mod W {}
846 pub mod RW {}
847 }
848 #[doc = "Word Addressable."]
849 pub mod WA {
850 pub const offset: u32 = 10;
851 pub const mask: u32 = 0x01 << offset;
852 pub mod R {}
853 pub mod W {}
854 pub mod RW {}
855 }
856 #[doc = "Column Address Size."]
857 pub mod CAS {
858 pub const offset: u32 = 11;
859 pub const mask: u32 = 0x0f << offset;
860 pub mod R {}
861 pub mod W {}
862 pub mod RW {}
863 }
864 #[doc = "CS interval unit"]
865 pub mod CSINTERVALUNIT {
866 pub const offset: u32 = 15;
867 pub const mask: u32 = 0x01 << offset;
868 pub mod R {}
869 pub mod W {}
870 pub mod RW {
871 #[doc = "The CS interval unit is 1 serial clock cycle"]
872 pub const CSINTERVALUNIT_0: u32 = 0;
873 #[doc = "The CS interval unit is 256 serial clock cycle"]
874 pub const CSINTERVALUNIT_1: u32 = 0x01;
875 }
876 }
877 #[doc = "This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0."]
878 pub mod CSINTERVAL {
879 pub const offset: u32 = 16;
880 pub const mask: u32 = 0xffff << offset;
881 pub mod R {}
882 pub mod W {}
883 pub mod RW {}
884 }
885}
886#[doc = "Flash Control Register 2"]
887pub mod FLSHCR2 {
888 #[doc = "Sequence Index for AHB Read triggered Command in LUT."]
889 pub mod ARDSEQID {
890 pub const offset: u32 = 0;
891 pub const mask: u32 = 0x0f << offset;
892 pub mod R {}
893 pub mod W {}
894 pub mod RW {}
895 }
896 #[doc = "Sequence Number for AHB Read triggered Command in LUT."]
897 pub mod ARDSEQNUM {
898 pub const offset: u32 = 5;
899 pub const mask: u32 = 0x07 << offset;
900 pub mod R {}
901 pub mod W {}
902 pub mod RW {}
903 }
904 #[doc = "Sequence Index for AHB Write triggered Command."]
905 pub mod AWRSEQID {
906 pub const offset: u32 = 8;
907 pub const mask: u32 = 0x0f << offset;
908 pub mod R {}
909 pub mod W {}
910 pub mod RW {}
911 }
912 #[doc = "Sequence Number for AHB Write triggered Command."]
913 pub mod AWRSEQNUM {
914 pub const offset: u32 = 13;
915 pub const mask: u32 = 0x07 << offset;
916 pub mod R {}
917 pub mod W {}
918 pub mod RW {}
919 }
920 #[doc = "For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"]
921 pub mod AWRWAIT {
922 pub const offset: u32 = 16;
923 pub const mask: u32 = 0x0fff << offset;
924 pub mod R {}
925 pub mod W {}
926 pub mod RW {}
927 }
928 #[doc = "AWRWAIT unit"]
929 pub mod AWRWAITUNIT {
930 pub const offset: u32 = 28;
931 pub const mask: u32 = 0x07 << offset;
932 pub mod R {}
933 pub mod W {}
934 pub mod RW {
935 #[doc = "The AWRWAIT unit is 2 ahb clock cycle"]
936 pub const AWRWAITUNIT_0: u32 = 0;
937 #[doc = "The AWRWAIT unit is 8 ahb clock cycle"]
938 pub const AWRWAITUNIT_1: u32 = 0x01;
939 #[doc = "The AWRWAIT unit is 32 ahb clock cycle"]
940 pub const AWRWAITUNIT_2: u32 = 0x02;
941 #[doc = "The AWRWAIT unit is 128 ahb clock cycle"]
942 pub const AWRWAITUNIT_3: u32 = 0x03;
943 #[doc = "The AWRWAIT unit is 512 ahb clock cycle"]
944 pub const AWRWAITUNIT_4: u32 = 0x04;
945 #[doc = "The AWRWAIT unit is 2048 ahb clock cycle"]
946 pub const AWRWAITUNIT_5: u32 = 0x05;
947 #[doc = "The AWRWAIT unit is 8192 ahb clock cycle"]
948 pub const AWRWAITUNIT_6: u32 = 0x06;
949 #[doc = "The AWRWAIT unit is 32768 ahb clock cycle"]
950 pub const AWRWAITUNIT_7: u32 = 0x07;
951 }
952 }
953 #[doc = "Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details."]
954 pub mod CLRINSTRPTR {
955 pub const offset: u32 = 31;
956 pub const mask: u32 = 0x01 << offset;
957 pub mod R {}
958 pub mod W {}
959 pub mod RW {}
960 }
961}
962#[doc = "Flash Control Register 4"]
963pub mod FLSHCR4 {
964 #[doc = "Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation."]
965 pub mod WMOPT1 {
966 pub const offset: u32 = 0;
967 pub const mask: u32 = 0x01 << offset;
968 pub mod R {}
969 pub mod W {}
970 pub mod RW {
971 #[doc = "DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode."]
972 pub const WMOPT1_0: u32 = 0;
973 #[doc = "DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode."]
974 pub const WMOPT1_1: u32 = 0x01;
975 }
976 }
977 #[doc = "Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set."]
978 pub mod WMENA {
979 pub const offset: u32 = 2;
980 pub const mask: u32 = 0x01 << offset;
981 pub mod R {}
982 pub mod W {}
983 pub mod RW {
984 #[doc = "Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device."]
985 pub const WMENA_0: u32 = 0;
986 #[doc = "Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device."]
987 pub const WMENA_1: u32 = 0x01;
988 }
989 }
990 #[doc = "Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set."]
991 pub mod WMENB {
992 pub const offset: u32 = 3;
993 pub const mask: u32 = 0x01 << offset;
994 pub mod R {}
995 pub mod W {}
996 pub mod RW {
997 #[doc = "Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device."]
998 pub const WMENB_0: u32 = 0;
999 #[doc = "Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device."]
1000 pub const WMENB_1: u32 = 0x01;
1001 }
1002 }
1003}
1004#[doc = "IP Control Register 0"]
1005pub mod IPCR0 {
1006 #[doc = "Serial Flash Address for IP command."]
1007 pub mod SFAR {
1008 pub const offset: u32 = 0;
1009 pub const mask: u32 = 0xffff_ffff << offset;
1010 pub mod R {}
1011 pub mod W {}
1012 pub mod RW {}
1013 }
1014}
1015#[doc = "IP Control Register 1"]
1016pub mod IPCR1 {
1017 #[doc = "Flash Read/Program Data Size (in Bytes) for IP command."]
1018 pub mod IDATSZ {
1019 pub const offset: u32 = 0;
1020 pub const mask: u32 = 0xffff << offset;
1021 pub mod R {}
1022 pub mod W {}
1023 pub mod RW {}
1024 }
1025 #[doc = "Sequence Index in LUT for IP command."]
1026 pub mod ISEQID {
1027 pub const offset: u32 = 16;
1028 pub const mask: u32 = 0x0f << offset;
1029 pub mod R {}
1030 pub mod W {}
1031 pub mod RW {}
1032 }
1033 #[doc = "Sequence Number for IP command: ISEQNUM+1."]
1034 pub mod ISEQNUM {
1035 pub const offset: u32 = 24;
1036 pub const mask: u32 = 0x07 << offset;
1037 pub mod R {}
1038 pub mod W {}
1039 pub mod RW {}
1040 }
1041 #[doc = "Parallel mode Enabled for IP command."]
1042 pub mod IPAREN {
1043 pub const offset: u32 = 31;
1044 pub const mask: u32 = 0x01 << offset;
1045 pub mod R {}
1046 pub mod W {}
1047 pub mod RW {
1048 #[doc = "Flash will be accessed in Individual mode."]
1049 pub const IPAREN_0: u32 = 0;
1050 #[doc = "Flash will be accessed in Parallel mode."]
1051 pub const IPAREN_1: u32 = 0x01;
1052 }
1053 }
1054}
1055#[doc = "IP Command Register"]
1056pub mod IPCMD {
1057 #[doc = "Setting this bit will trigger an IP Command."]
1058 pub mod TRG {
1059 pub const offset: u32 = 0;
1060 pub const mask: u32 = 0x01 << offset;
1061 pub mod R {}
1062 pub mod W {}
1063 pub mod RW {}
1064 }
1065}
1066#[doc = "IP RX FIFO Control Register"]
1067pub mod IPRXFCR {
1068 #[doc = "Clear all valid data entries in IP RX FIFO."]
1069 pub mod CLRIPRXF {
1070 pub const offset: u32 = 0;
1071 pub const mask: u32 = 0x01 << offset;
1072 pub mod R {}
1073 pub mod W {}
1074 pub mod RW {}
1075 }
1076 #[doc = "IP RX FIFO reading by DMA enabled."]
1077 pub mod RXDMAEN {
1078 pub const offset: u32 = 1;
1079 pub const mask: u32 = 0x01 << offset;
1080 pub mod R {}
1081 pub mod W {}
1082 pub mod RW {
1083 #[doc = "IP RX FIFO would be read by processor."]
1084 pub const RXDMAEN_0: u32 = 0;
1085 #[doc = "IP RX FIFO would be read by DMA."]
1086 pub const RXDMAEN_1: u32 = 0x01;
1087 }
1088 }
1089 #[doc = "Watermark level is (RXWMRK+1)*64 Bits."]
1090 pub mod RXWMRK {
1091 pub const offset: u32 = 2;
1092 pub const mask: u32 = 0x0f << offset;
1093 pub mod R {}
1094 pub mod W {}
1095 pub mod RW {}
1096 }
1097}
1098#[doc = "IP TX FIFO Control Register"]
1099pub mod IPTXFCR {
1100 #[doc = "Clear all valid data entries in IP TX FIFO."]
1101 pub mod CLRIPTXF {
1102 pub const offset: u32 = 0;
1103 pub const mask: u32 = 0x01 << offset;
1104 pub mod R {}
1105 pub mod W {}
1106 pub mod RW {}
1107 }
1108 #[doc = "IP TX FIFO filling by DMA enabled."]
1109 pub mod TXDMAEN {
1110 pub const offset: u32 = 1;
1111 pub const mask: u32 = 0x01 << offset;
1112 pub mod R {}
1113 pub mod W {}
1114 pub mod RW {
1115 #[doc = "IP TX FIFO would be filled by processor."]
1116 pub const TXDMAEN_0: u32 = 0;
1117 #[doc = "IP TX FIFO would be filled by DMA."]
1118 pub const TXDMAEN_1: u32 = 0x01;
1119 }
1120 }
1121 #[doc = "Watermark level is (TXWMRK+1)*64 Bits."]
1122 pub mod TXWMRK {
1123 pub const offset: u32 = 2;
1124 pub const mask: u32 = 0x0f << offset;
1125 pub mod R {}
1126 pub mod W {}
1127 pub mod RW {}
1128 }
1129}
1130#[doc = "DLL Control Register 0"]
1131pub mod DLLCR {
1132 #[doc = "DLL calibration enable."]
1133 pub mod DLLEN {
1134 pub const offset: u32 = 0;
1135 pub const mask: u32 = 0x01 << offset;
1136 pub mod R {}
1137 pub mod W {}
1138 pub mod RW {}
1139 }
1140 #[doc = "Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation)."]
1141 pub mod DLLRESET {
1142 pub const offset: u32 = 1;
1143 pub const mask: u32 = 0x01 << offset;
1144 pub mod R {}
1145 pub mod W {}
1146 pub mod RW {}
1147 }
1148 #[doc = "The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended."]
1149 pub mod SLVDLYTARGET {
1150 pub const offset: u32 = 3;
1151 pub const mask: u32 = 0x0f << offset;
1152 pub mod R {}
1153 pub mod W {}
1154 pub mod RW {}
1155 }
1156 #[doc = "Slave clock delay line delay cell number selection override enable."]
1157 pub mod OVRDEN {
1158 pub const offset: u32 = 8;
1159 pub const mask: u32 = 0x01 << offset;
1160 pub mod R {}
1161 pub mod W {}
1162 pub mod RW {}
1163 }
1164 #[doc = "Slave clock delay line delay cell number selection override value."]
1165 pub mod OVRDVAL {
1166 pub const offset: u32 = 9;
1167 pub const mask: u32 = 0x3f << offset;
1168 pub mod R {}
1169 pub mod W {}
1170 pub mod RW {}
1171 }
1172}
1173#[doc = "Status Register 0"]
1174pub mod STS0 {
1175 #[doc = "This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface."]
1176 pub mod SEQIDLE {
1177 pub const offset: u32 = 0;
1178 pub const mask: u32 = 0x01 << offset;
1179 pub mod R {}
1180 pub mod W {}
1181 pub mod RW {}
1182 }
1183 #[doc = "This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE."]
1184 pub mod ARBIDLE {
1185 pub const offset: u32 = 1;
1186 pub const mask: u32 = 0x01 << offset;
1187 pub mod R {}
1188 pub mod W {}
1189 pub mod RW {}
1190 }
1191 #[doc = "This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0\\[ARBIDLE\\]=0x1)."]
1192 pub mod ARBCMDSRC {
1193 pub const offset: u32 = 2;
1194 pub const mask: u32 = 0x03 << offset;
1195 pub mod R {}
1196 pub mod W {}
1197 pub mod RW {
1198 #[doc = "Triggered by AHB read command (triggered by AHB read)."]
1199 pub const ARBCMDSRC_0: u32 = 0;
1200 #[doc = "Triggered by AHB write command (triggered by AHB Write)."]
1201 pub const ARBCMDSRC_1: u32 = 0x01;
1202 #[doc = "Triggered by IP command (triggered by setting register bit IPCMD.TRG)."]
1203 pub const ARBCMDSRC_2: u32 = 0x02;
1204 #[doc = "Triggered by suspended command (resumed)."]
1205 pub const ARBCMDSRC_3: u32 = 0x03;
1206 }
1207 }
1208}
1209#[doc = "Status Register 1"]
1210pub mod STS1 {
1211 #[doc = "Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR\\[AHBCMDERR\\] is write-1-clear(w1c)."]
1212 pub mod AHBCMDERRID {
1213 pub const offset: u32 = 0;
1214 pub const mask: u32 = 0x0f << offset;
1215 pub mod R {}
1216 pub mod W {}
1217 pub mod RW {}
1218 }
1219 #[doc = "Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR\\[AHBCMDERR\\] is write-1-clear(w1c)."]
1220 pub mod AHBCMDERRCODE {
1221 pub const offset: u32 = 8;
1222 pub const mask: u32 = 0x0f << offset;
1223 pub mod R {}
1224 pub mod W {}
1225 pub mod RW {
1226 #[doc = "No error."]
1227 pub const AHBCMDERRCODE_0: u32 = 0;
1228 #[doc = "AHB Write command with JMP_ON_CS instruction used in the sequence."]
1229 pub const AHBCMDERRCODE_2: u32 = 0x02;
1230 #[doc = "There is unknown instruction opcode in the sequence."]
1231 pub const AHBCMDERRCODE_3: u32 = 0x03;
1232 #[doc = "Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence."]
1233 pub const AHBCMDERRCODE_4: u32 = 0x04;
1234 #[doc = "Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence."]
1235 pub const AHBCMDERRCODE_5: u32 = 0x05;
1236 #[doc = "Sequence execution timeout."]
1237 pub const AHBCMDERRCODE_14: u32 = 0x0e;
1238 }
1239 }
1240 #[doc = "Indicates the sequence Index when IP command error detected. This field will be cleared when INTR\\[IPCMDERR\\] is write-1-clear(w1c)."]
1241 pub mod IPCMDERRID {
1242 pub const offset: u32 = 16;
1243 pub const mask: u32 = 0x0f << offset;
1244 pub mod R {}
1245 pub mod W {}
1246 pub mod RW {}
1247 }
1248 #[doc = "Indicates the Error Code when IP command Error detected. This field will be cleared when INTR\\[IPCMDERR\\] is write-1-clear(w1c)."]
1249 pub mod IPCMDERRCODE {
1250 pub const offset: u32 = 24;
1251 pub const mask: u32 = 0x0f << offset;
1252 pub mod R {}
1253 pub mod W {}
1254 pub mod RW {
1255 #[doc = "No error."]
1256 pub const IPCMDERRCODE_0: u32 = 0;
1257 #[doc = "IP command with JMP_ON_CS instruction used in the sequence."]
1258 pub const IPCMDERRCODE_2: u32 = 0x02;
1259 #[doc = "There is unknown instruction opcode in the sequence."]
1260 pub const IPCMDERRCODE_3: u32 = 0x03;
1261 #[doc = "Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence."]
1262 pub const IPCMDERRCODE_4: u32 = 0x04;
1263 #[doc = "Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence."]
1264 pub const IPCMDERRCODE_5: u32 = 0x05;
1265 #[doc = "Flash access start address exceed the whole flash address range (A1/A2/B1/B2)."]
1266 pub const IPCMDERRCODE_6: u32 = 0x06;
1267 #[doc = "Sequence execution timeout."]
1268 pub const IPCMDERRCODE_14: u32 = 0x0e;
1269 #[doc = "Flash boundary crossed."]
1270 pub const IPCMDERRCODE_15: u32 = 0x0f;
1271 }
1272 }
1273}
1274#[doc = "Status Register 2"]
1275pub mod STS2 {
1276 #[doc = "Flash A sample clock slave delay line locked."]
1277 pub mod ASLVLOCK {
1278 pub const offset: u32 = 0;
1279 pub const mask: u32 = 0x01 << offset;
1280 pub mod R {}
1281 pub mod W {}
1282 pub mod RW {}
1283 }
1284 #[doc = "Flash A sample clock reference delay line locked."]
1285 pub mod AREFLOCK {
1286 pub const offset: u32 = 1;
1287 pub const mask: u32 = 0x01 << offset;
1288 pub mod R {}
1289 pub mod W {}
1290 pub mod RW {}
1291 }
1292 #[doc = "Flash A sample clock slave delay line delay cell number selection ."]
1293 pub mod ASLVSEL {
1294 pub const offset: u32 = 2;
1295 pub const mask: u32 = 0x3f << offset;
1296 pub mod R {}
1297 pub mod W {}
1298 pub mod RW {}
1299 }
1300 #[doc = "Flash A sample clock reference delay line delay cell number selection."]
1301 pub mod AREFSEL {
1302 pub const offset: u32 = 8;
1303 pub const mask: u32 = 0x3f << offset;
1304 pub mod R {}
1305 pub mod W {}
1306 pub mod RW {}
1307 }
1308 #[doc = "Flash B sample clock slave delay line locked."]
1309 pub mod BSLVLOCK {
1310 pub const offset: u32 = 16;
1311 pub const mask: u32 = 0x01 << offset;
1312 pub mod R {}
1313 pub mod W {}
1314 pub mod RW {}
1315 }
1316 #[doc = "Flash B sample clock reference delay line locked."]
1317 pub mod BREFLOCK {
1318 pub const offset: u32 = 17;
1319 pub const mask: u32 = 0x01 << offset;
1320 pub mod R {}
1321 pub mod W {}
1322 pub mod RW {}
1323 }
1324 #[doc = "Flash B sample clock slave delay line delay cell number selection."]
1325 pub mod BSLVSEL {
1326 pub const offset: u32 = 18;
1327 pub const mask: u32 = 0x3f << offset;
1328 pub mod R {}
1329 pub mod W {}
1330 pub mod RW {}
1331 }
1332 #[doc = "Flash B sample clock reference delay line delay cell number selection."]
1333 pub mod BREFSEL {
1334 pub const offset: u32 = 24;
1335 pub const mask: u32 = 0x3f << offset;
1336 pub mod R {}
1337 pub mod W {}
1338 pub mod RW {}
1339 }
1340}
1341#[doc = "AHB Suspend Status Register"]
1342pub mod AHBSPNDSTS {
1343 #[doc = "Indicates if an AHB read prefetch command sequence has been suspended."]
1344 pub mod ACTIVE {
1345 pub const offset: u32 = 0;
1346 pub const mask: u32 = 0x01 << offset;
1347 pub mod R {}
1348 pub mod W {}
1349 pub mod RW {}
1350 }
1351 #[doc = "AHB RX BUF ID for suspended command sequence."]
1352 pub mod BUFID {
1353 pub const offset: u32 = 1;
1354 pub const mask: u32 = 0x07 << offset;
1355 pub mod R {}
1356 pub mod W {}
1357 pub mod RW {}
1358 }
1359 #[doc = "Left Data size for suspended command sequence (in byte)."]
1360 pub mod DATLFT {
1361 pub const offset: u32 = 16;
1362 pub const mask: u32 = 0xffff << offset;
1363 pub mod R {}
1364 pub mod W {}
1365 pub mod RW {}
1366 }
1367}
1368#[doc = "IP RX FIFO Status Register"]
1369pub mod IPRXFSTS {
1370 #[doc = "Fill level of IP RX FIFO."]
1371 pub mod FILL {
1372 pub const offset: u32 = 0;
1373 pub const mask: u32 = 0xff << offset;
1374 pub mod R {}
1375 pub mod W {}
1376 pub mod RW {}
1377 }
1378 #[doc = "Total Read Data Counter: RDCNTR * 64 Bits."]
1379 pub mod RDCNTR {
1380 pub const offset: u32 = 16;
1381 pub const mask: u32 = 0xffff << offset;
1382 pub mod R {}
1383 pub mod W {}
1384 pub mod RW {}
1385 }
1386}
1387#[doc = "IP TX FIFO Status Register"]
1388pub mod IPTXFSTS {
1389 #[doc = "Fill level of IP TX FIFO."]
1390 pub mod FILL {
1391 pub const offset: u32 = 0;
1392 pub const mask: u32 = 0xff << offset;
1393 pub mod R {}
1394 pub mod W {}
1395 pub mod RW {}
1396 }
1397 #[doc = "Total Write Data Counter: WRCNTR * 64 Bits."]
1398 pub mod WRCNTR {
1399 pub const offset: u32 = 16;
1400 pub const mask: u32 = 0xffff << offset;
1401 pub mod R {}
1402 pub mod W {}
1403 pub mod RW {}
1404 }
1405}
1406#[doc = "IP RX FIFO Data Register 0"]
1407pub mod RFDR {
1408 #[doc = "RX Data"]
1409 pub mod RXDATA {
1410 pub const offset: u32 = 0;
1411 pub const mask: u32 = 0xffff_ffff << offset;
1412 pub mod R {}
1413 pub mod W {}
1414 pub mod RW {}
1415 }
1416}
1417#[doc = "IP TX FIFO Data Register 0"]
1418pub mod TFDR {
1419 #[doc = "TX Data"]
1420 pub mod TXDATA {
1421 pub const offset: u32 = 0;
1422 pub const mask: u32 = 0xffff_ffff << offset;
1423 pub mod R {}
1424 pub mod W {}
1425 pub mod RW {}
1426 }
1427}
1428#[doc = "LUT 0"]
1429pub mod LUT {
1430 #[doc = "OPERAND0"]
1431 pub mod OPERAND0 {
1432 pub const offset: u32 = 0;
1433 pub const mask: u32 = 0xff << offset;
1434 pub mod R {}
1435 pub mod W {}
1436 pub mod RW {}
1437 }
1438 #[doc = "NUM_PADS0"]
1439 pub mod NUM_PADS0 {
1440 pub const offset: u32 = 8;
1441 pub const mask: u32 = 0x03 << offset;
1442 pub mod R {}
1443 pub mod W {}
1444 pub mod RW {}
1445 }
1446 #[doc = "OPCODE"]
1447 pub mod OPCODE0 {
1448 pub const offset: u32 = 10;
1449 pub const mask: u32 = 0x3f << offset;
1450 pub mod R {}
1451 pub mod W {}
1452 pub mod RW {}
1453 }
1454 #[doc = "OPERAND1"]
1455 pub mod OPERAND1 {
1456 pub const offset: u32 = 16;
1457 pub const mask: u32 = 0xff << offset;
1458 pub mod R {}
1459 pub mod W {}
1460 pub mod RW {}
1461 }
1462 #[doc = "NUM_PADS1"]
1463 pub mod NUM_PADS1 {
1464 pub const offset: u32 = 24;
1465 pub const mask: u32 = 0x03 << offset;
1466 pub mod R {}
1467 pub mod W {}
1468 pub mod RW {}
1469 }
1470 #[doc = "OPCODE1"]
1471 pub mod OPCODE1 {
1472 pub const offset: u32 = 26;
1473 pub const mask: u32 = 0x3f << offset;
1474 pub mod R {}
1475 pub mod W {}
1476 pub mod RW {}
1477 }
1478}