rp2040_pac/xip_ctrl/
stream_fifo.rs

1#[doc = "Register `STREAM_FIFO` reader"]
2pub type R = crate::R<STREAM_FIFO_SPEC>;
3impl core::fmt::Debug for R {
4    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5        write!(f, "{}", self.bits())
6    }
7}
8impl core::fmt::Debug for crate::generic::Reg<STREAM_FIFO_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        core::fmt::Debug::fmt(&self.read(), f)
11    }
12}
13#[doc = "FIFO stream data  
14 Streamed data is buffered here, for retrieval by the system DMA.  
15 This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing  
16 the DMA to bus stalls caused by other XIP traffic.  
17
18You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct STREAM_FIFO_SPEC;
20impl crate::RegisterSpec for STREAM_FIFO_SPEC {
21    type Ux = u32;
22}
23#[doc = "`read()` method returns [`stream_fifo::R`](R) reader structure"]
24impl crate::Readable for STREAM_FIFO_SPEC {}
25#[doc = "`reset()` method sets STREAM_FIFO to value 0"]
26impl crate::Resettable for STREAM_FIFO_SPEC {
27    const RESET_VALUE: u32 = 0;
28}