rp2040_pac/xip_ctrl/
ctr_hit.rs

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1#[doc = "Register `CTR_HIT` reader"]
2pub type R = crate::R<CTR_HIT_SPEC>;
3#[doc = "Register `CTR_HIT` writer"]
4pub type W = crate::W<CTR_HIT_SPEC>;
5impl core::fmt::Debug for R {
6    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7        write!(f, "{}", self.bits())
8    }
9}
10impl core::fmt::Debug for crate::generic::Reg<CTR_HIT_SPEC> {
11    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12        core::fmt::Debug::fmt(&self.read(), f)
13    }
14}
15impl W {
16    #[doc = r" Writes raw bits to the register."]
17    #[doc = r""]
18    #[doc = r" # Safety"]
19    #[doc = r""]
20    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
21    #[inline(always)]
22    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
23        self.bits = bits;
24        self
25    }
26}
27#[doc = "Cache Hit counter  
28 A 32 bit saturating counter that increments upon each cache hit,  
29 i.e. when an XIP access is serviced directly from cached data.  
30 Write any value to clear.  
31
32You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
33pub struct CTR_HIT_SPEC;
34impl crate::RegisterSpec for CTR_HIT_SPEC {
35    type Ux = u32;
36}
37#[doc = "`read()` method returns [`ctr_hit::R`](R) reader structure"]
38impl crate::Readable for CTR_HIT_SPEC {}
39#[doc = "`write(|w| ..)` method takes [`ctr_hit::W`](W) writer structure"]
40impl crate::Writable for CTR_HIT_SPEC {
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets CTR_HIT to value 0"]
45impl crate::Resettable for CTR_HIT_SPEC {
46    const RESET_VALUE: u32 = 0;
47}
rp2040_pac/xip_ctrl/ctr_hit.rs

rp2040_pac/xip_ctrl/
ctr_hit.rs
