rp2040_pac/pio0/sm/
sm_execctrl.rs

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1#[doc = "Register `SM_EXECCTRL` reader"]
2pub type R = crate::R<SM_EXECCTRL_SPEC>;
3#[doc = "Register `SM_EXECCTRL` writer"]
4pub type W = crate::W<SM_EXECCTRL_SPEC>;
5#[doc = "Field `STATUS_N` reader - Comparison level for the MOV x, STATUS instruction"]
6pub type STATUS_N_R = crate::FieldReader;
7#[doc = "Field `STATUS_N` writer - Comparison level for the MOV x, STATUS instruction"]
8pub type STATUS_N_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `STATUS_SEL` reader - Comparison used for the MOV x, STATUS instruction."]
10pub type STATUS_SEL_R = crate::BitReader<STATUS_SEL_A>;
11#[doc = "Comparison used for the MOV x, STATUS instruction.  
12
13Value on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15pub enum STATUS_SEL_A {
16    #[doc = "0: All-ones if TX FIFO level &lt; N, otherwise all-zeroes"]
17    TXLEVEL = 0,
18    #[doc = "1: All-ones if RX FIFO level &lt; N, otherwise all-zeroes"]
19    RXLEVEL = 1,
20}
21impl From<STATUS_SEL_A> for bool {
22    #[inline(always)]
23    fn from(variant: STATUS_SEL_A) -> Self {
24        variant as u8 != 0
25    }
26}
27impl STATUS_SEL_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> STATUS_SEL_A {
31        match self.bits {
32            false => STATUS_SEL_A::TXLEVEL,
33            true => STATUS_SEL_A::RXLEVEL,
34        }
35    }
36    #[doc = "All-ones if TX FIFO level &lt; N, otherwise all-zeroes"]
37    #[inline(always)]
38    pub fn is_txlevel(&self) -> bool {
39        *self == STATUS_SEL_A::TXLEVEL
40    }
41    #[doc = "All-ones if RX FIFO level &lt; N, otherwise all-zeroes"]
42    #[inline(always)]
43    pub fn is_rxlevel(&self) -> bool {
44        *self == STATUS_SEL_A::RXLEVEL
45    }
46}
47#[doc = "Field `STATUS_SEL` writer - Comparison used for the MOV x, STATUS instruction."]
48pub type STATUS_SEL_W<'a, REG> = crate::BitWriter<'a, REG, STATUS_SEL_A>;
49impl<'a, REG> STATUS_SEL_W<'a, REG>
50where
51    REG: crate::Writable + crate::RegisterSpec,
52{
53    #[doc = "All-ones if TX FIFO level &lt; N, otherwise all-zeroes"]
54    #[inline(always)]
55    pub fn txlevel(self) -> &'a mut crate::W<REG> {
56        self.variant(STATUS_SEL_A::TXLEVEL)
57    }
58    #[doc = "All-ones if RX FIFO level &lt; N, otherwise all-zeroes"]
59    #[inline(always)]
60    pub fn rxlevel(self) -> &'a mut crate::W<REG> {
61        self.variant(STATUS_SEL_A::RXLEVEL)
62    }
63}
64#[doc = "Field `WRAP_BOTTOM` reader - After reaching wrap_top, execution is wrapped to this address."]
65pub type WRAP_BOTTOM_R = crate::FieldReader;
66#[doc = "Field `WRAP_BOTTOM` writer - After reaching wrap_top, execution is wrapped to this address."]
67pub type WRAP_BOTTOM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
68#[doc = "Field `WRAP_TOP` reader - After reaching this address, execution is wrapped to wrap_bottom.  
69 If the instruction is a jump, and the jump condition is true, the jump takes priority."]
70pub type WRAP_TOP_R = crate::FieldReader;
71#[doc = "Field `WRAP_TOP` writer - After reaching this address, execution is wrapped to wrap_bottom.  
72 If the instruction is a jump, and the jump condition is true, the jump takes priority."]
73pub type WRAP_TOP_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
74#[doc = "Field `OUT_STICKY` reader - Continuously assert the most recent OUT/SET to the pins"]
75pub type OUT_STICKY_R = crate::BitReader;
76#[doc = "Field `OUT_STICKY` writer - Continuously assert the most recent OUT/SET to the pins"]
77pub type OUT_STICKY_W<'a, REG> = crate::BitWriter<'a, REG>;
78#[doc = "Field `INLINE_OUT_EN` reader - If 1, use a bit of OUT data as an auxiliary write enable  
79 When used in conjunction with OUT_STICKY, writes with an enable of 0 will  
80 deassert the latest pin write. This can create useful masking/override behaviour  
81 due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
82pub type INLINE_OUT_EN_R = crate::BitReader;
83#[doc = "Field `INLINE_OUT_EN` writer - If 1, use a bit of OUT data as an auxiliary write enable  
84 When used in conjunction with OUT_STICKY, writes with an enable of 0 will  
85 deassert the latest pin write. This can create useful masking/override behaviour  
86 due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
87pub type INLINE_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
88#[doc = "Field `OUT_EN_SEL` reader - Which data bit to use for inline OUT enable"]
89pub type OUT_EN_SEL_R = crate::FieldReader;
90#[doc = "Field `OUT_EN_SEL` writer - Which data bit to use for inline OUT enable"]
91pub type OUT_EN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
92#[doc = "Field `JMP_PIN` reader - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
93pub type JMP_PIN_R = crate::FieldReader;
94#[doc = "Field `JMP_PIN` writer - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
95pub type JMP_PIN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
96#[doc = "Field `SIDE_PINDIR` reader - If 1, side-set data is asserted to pin directions, instead of pin values"]
97pub type SIDE_PINDIR_R = crate::BitReader;
98#[doc = "Field `SIDE_PINDIR` writer - If 1, side-set data is asserted to pin directions, instead of pin values"]
99pub type SIDE_PINDIR_W<'a, REG> = crate::BitWriter<'a, REG>;
100#[doc = "Field `SIDE_EN` reader - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
101pub type SIDE_EN_R = crate::BitReader;
102#[doc = "Field `SIDE_EN` writer - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
103pub type SIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
104#[doc = "Field `EXEC_STALLED` reader - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."]
105pub type EXEC_STALLED_R = crate::BitReader;
106impl R {
107    #[doc = "Bits 0:3 - Comparison level for the MOV x, STATUS instruction"]
108    #[inline(always)]
109    pub fn status_n(&self) -> STATUS_N_R {
110        STATUS_N_R::new((self.bits & 0x0f) as u8)
111    }
112    #[doc = "Bit 4 - Comparison used for the MOV x, STATUS instruction."]
113    #[inline(always)]
114    pub fn status_sel(&self) -> STATUS_SEL_R {
115        STATUS_SEL_R::new(((self.bits >> 4) & 1) != 0)
116    }
117    #[doc = "Bits 7:11 - After reaching wrap_top, execution is wrapped to this address."]
118    #[inline(always)]
119    pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R {
120        WRAP_BOTTOM_R::new(((self.bits >> 7) & 0x1f) as u8)
121    }
122    #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.  
123 If the instruction is a jump, and the jump condition is true, the jump takes priority."]
124    #[inline(always)]
125    pub fn wrap_top(&self) -> WRAP_TOP_R {
126        WRAP_TOP_R::new(((self.bits >> 12) & 0x1f) as u8)
127    }
128    #[doc = "Bit 17 - Continuously assert the most recent OUT/SET to the pins"]
129    #[inline(always)]
130    pub fn out_sticky(&self) -> OUT_STICKY_R {
131        OUT_STICKY_R::new(((self.bits >> 17) & 1) != 0)
132    }
133    #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable  
134 When used in conjunction with OUT_STICKY, writes with an enable of 0 will  
135 deassert the latest pin write. This can create useful masking/override behaviour  
136 due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
137    #[inline(always)]
138    pub fn inline_out_en(&self) -> INLINE_OUT_EN_R {
139        INLINE_OUT_EN_R::new(((self.bits >> 18) & 1) != 0)
140    }
141    #[doc = "Bits 19:23 - Which data bit to use for inline OUT enable"]
142    #[inline(always)]
143    pub fn out_en_sel(&self) -> OUT_EN_SEL_R {
144        OUT_EN_SEL_R::new(((self.bits >> 19) & 0x1f) as u8)
145    }
146    #[doc = "Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
147    #[inline(always)]
148    pub fn jmp_pin(&self) -> JMP_PIN_R {
149        JMP_PIN_R::new(((self.bits >> 24) & 0x1f) as u8)
150    }
151    #[doc = "Bit 29 - If 1, side-set data is asserted to pin directions, instead of pin values"]
152    #[inline(always)]
153    pub fn side_pindir(&self) -> SIDE_PINDIR_R {
154        SIDE_PINDIR_R::new(((self.bits >> 29) & 1) != 0)
155    }
156    #[doc = "Bit 30 - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
157    #[inline(always)]
158    pub fn side_en(&self) -> SIDE_EN_R {
159        SIDE_EN_R::new(((self.bits >> 30) & 1) != 0)
160    }
161    #[doc = "Bit 31 - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."]
162    #[inline(always)]
163    pub fn exec_stalled(&self) -> EXEC_STALLED_R {
164        EXEC_STALLED_R::new(((self.bits >> 31) & 1) != 0)
165    }
166}
167impl W {
168    #[doc = "Bits 0:3 - Comparison level for the MOV x, STATUS instruction"]
169    #[inline(always)]
170    #[must_use]
171    pub fn status_n(&mut self) -> STATUS_N_W<SM_EXECCTRL_SPEC> {
172        STATUS_N_W::new(self, 0)
173    }
174    #[doc = "Bit 4 - Comparison used for the MOV x, STATUS instruction."]
175    #[inline(always)]
176    #[must_use]
177    pub fn status_sel(&mut self) -> STATUS_SEL_W<SM_EXECCTRL_SPEC> {
178        STATUS_SEL_W::new(self, 4)
179    }
180    #[doc = "Bits 7:11 - After reaching wrap_top, execution is wrapped to this address."]
181    #[inline(always)]
182    #[must_use]
183    pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W<SM_EXECCTRL_SPEC> {
184        WRAP_BOTTOM_W::new(self, 7)
185    }
186    #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.  
187 If the instruction is a jump, and the jump condition is true, the jump takes priority."]
188    #[inline(always)]
189    #[must_use]
190    pub fn wrap_top(&mut self) -> WRAP_TOP_W<SM_EXECCTRL_SPEC> {
191        WRAP_TOP_W::new(self, 12)
192    }
193    #[doc = "Bit 17 - Continuously assert the most recent OUT/SET to the pins"]
194    #[inline(always)]
195    #[must_use]
196    pub fn out_sticky(&mut self) -> OUT_STICKY_W<SM_EXECCTRL_SPEC> {
197        OUT_STICKY_W::new(self, 17)
198    }
199    #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable  
200 When used in conjunction with OUT_STICKY, writes with an enable of 0 will  
201 deassert the latest pin write. This can create useful masking/override behaviour  
202 due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
203    #[inline(always)]
204    #[must_use]
205    pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W<SM_EXECCTRL_SPEC> {
206        INLINE_OUT_EN_W::new(self, 18)
207    }
208    #[doc = "Bits 19:23 - Which data bit to use for inline OUT enable"]
209    #[inline(always)]
210    #[must_use]
211    pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W<SM_EXECCTRL_SPEC> {
212        OUT_EN_SEL_W::new(self, 19)
213    }
214    #[doc = "Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
215    #[inline(always)]
216    #[must_use]
217    pub fn jmp_pin(&mut self) -> JMP_PIN_W<SM_EXECCTRL_SPEC> {
218        JMP_PIN_W::new(self, 24)
219    }
220    #[doc = "Bit 29 - If 1, side-set data is asserted to pin directions, instead of pin values"]
221    #[inline(always)]
222    #[must_use]
223    pub fn side_pindir(&mut self) -> SIDE_PINDIR_W<SM_EXECCTRL_SPEC> {
224        SIDE_PINDIR_W::new(self, 29)
225    }
226    #[doc = "Bit 30 - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
227    #[inline(always)]
228    #[must_use]
229    pub fn side_en(&mut self) -> SIDE_EN_W<SM_EXECCTRL_SPEC> {
230        SIDE_EN_W::new(self, 30)
231    }
232    #[doc = r" Writes raw bits to the register."]
233    #[doc = r""]
234    #[doc = r" # Safety"]
235    #[doc = r""]
236    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
237    #[inline(always)]
238    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
239        self.bits = bits;
240        self
241    }
242}
243#[doc = "Execution/behavioural settings for state machine 0  
244
245You can [`read`](crate::generic::Reg::read) this register and get [`sm_execctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_execctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
246pub struct SM_EXECCTRL_SPEC;
247impl crate::RegisterSpec for SM_EXECCTRL_SPEC {
248    type Ux = u32;
249}
250#[doc = "`read()` method returns [`sm_execctrl::R`](R) reader structure"]
251impl crate::Readable for SM_EXECCTRL_SPEC {}
252#[doc = "`write(|w| ..)` method takes [`sm_execctrl::W`](W) writer structure"]
253impl crate::Writable for SM_EXECCTRL_SPEC {
254    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
255    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
256}
257#[doc = "`reset()` method sets SM_EXECCTRL to value 0x0001_f000"]
258impl crate::Resettable for SM_EXECCTRL_SPEC {
259    const RESET_VALUE: u32 = 0x0001_f000;
260}
rp2040_pac/pio0/sm/sm_execctrl.rs

rp2040_pac/pio0/sm/
sm_execctrl.rs
