imxrt_ral/blocks/imxrt1011/
lpspi.rs
1#[doc = "LPSPI"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Version ID Register"]
5 pub VERID: crate::RORegister<u32>,
6 #[doc = "Parameter Register"]
7 pub PARAM: crate::RORegister<u32>,
8 _reserved0: [u8; 0x08],
9 #[doc = "Control Register"]
10 pub CR: crate::RWRegister<u32>,
11 #[doc = "Status Register"]
12 pub SR: crate::RWRegister<u32>,
13 #[doc = "Interrupt Enable Register"]
14 pub IER: crate::RWRegister<u32>,
15 #[doc = "DMA Enable Register"]
16 pub DER: crate::RWRegister<u32>,
17 #[doc = "Configuration Register 0"]
18 pub CFGR0: crate::RWRegister<u32>,
19 #[doc = "Configuration Register 1"]
20 pub CFGR1: crate::RWRegister<u32>,
21 _reserved1: [u8; 0x08],
22 #[doc = "Data Match Register 0"]
23 pub DMR0: crate::RWRegister<u32>,
24 #[doc = "Data Match Register 1"]
25 pub DMR1: crate::RWRegister<u32>,
26 _reserved2: [u8; 0x08],
27 #[doc = "Clock Configuration Register"]
28 pub CCR: crate::RWRegister<u32>,
29 _reserved3: [u8; 0x14],
30 #[doc = "FIFO Control Register"]
31 pub FCR: crate::RWRegister<u32>,
32 #[doc = "FIFO Status Register"]
33 pub FSR: crate::RORegister<u32>,
34 #[doc = "Transmit Command Register"]
35 pub TCR: crate::RWRegister<u32>,
36 #[doc = "Transmit Data Register"]
37 pub TDR: crate::WORegister<u32>,
38 _reserved4: [u8; 0x08],
39 #[doc = "Receive Status Register"]
40 pub RSR: crate::RORegister<u32>,
41 #[doc = "Receive Data Register"]
42 pub RDR: crate::RORegister<u32>,
43}
44#[doc = "Version ID Register"]
45pub mod VERID {
46 #[doc = "Module Identification Number"]
47 pub mod FEATURE {
48 pub const offset: u32 = 0;
49 pub const mask: u32 = 0xffff << offset;
50 pub mod R {}
51 pub mod W {}
52 pub mod RW {
53 #[doc = "Standard feature set supporting a 32-bit shift register."]
54 pub const FEATURE_4: u32 = 0x04;
55 }
56 }
57 #[doc = "Minor Version Number"]
58 pub mod MINOR {
59 pub const offset: u32 = 16;
60 pub const mask: u32 = 0xff << offset;
61 pub mod R {}
62 pub mod W {}
63 pub mod RW {}
64 }
65 #[doc = "Major Version Number"]
66 pub mod MAJOR {
67 pub const offset: u32 = 24;
68 pub const mask: u32 = 0xff << offset;
69 pub mod R {}
70 pub mod W {}
71 pub mod RW {}
72 }
73}
74#[doc = "Parameter Register"]
75pub mod PARAM {
76 #[doc = "Transmit FIFO Size"]
77 pub mod TXFIFO {
78 pub const offset: u32 = 0;
79 pub const mask: u32 = 0xff << offset;
80 pub mod R {}
81 pub mod W {}
82 pub mod RW {}
83 }
84 #[doc = "Receive FIFO Size"]
85 pub mod RXFIFO {
86 pub const offset: u32 = 8;
87 pub const mask: u32 = 0xff << offset;
88 pub mod R {}
89 pub mod W {}
90 pub mod RW {}
91 }
92 #[doc = "PCS Number"]
93 pub mod PCSNUM {
94 pub const offset: u32 = 16;
95 pub const mask: u32 = 0xff << offset;
96 pub mod R {}
97 pub mod W {}
98 pub mod RW {}
99 }
100}
101#[doc = "Control Register"]
102pub mod CR {
103 #[doc = "Module Enable"]
104 pub mod MEN {
105 pub const offset: u32 = 0;
106 pub const mask: u32 = 0x01 << offset;
107 pub mod R {}
108 pub mod W {}
109 pub mod RW {
110 #[doc = "Module is disabled"]
111 pub const MEN_0: u32 = 0;
112 #[doc = "Module is enabled"]
113 pub const MEN_1: u32 = 0x01;
114 }
115 }
116 #[doc = "Software Reset"]
117 pub mod RST {
118 pub const offset: u32 = 1;
119 pub const mask: u32 = 0x01 << offset;
120 pub mod R {}
121 pub mod W {}
122 pub mod RW {
123 #[doc = "Module is not reset"]
124 pub const RST_0: u32 = 0;
125 #[doc = "Module is reset"]
126 pub const RST_1: u32 = 0x01;
127 }
128 }
129 #[doc = "Doze Mode Enable"]
130 pub mod DOZEN {
131 pub const offset: u32 = 2;
132 pub const mask: u32 = 0x01 << offset;
133 pub mod R {}
134 pub mod W {}
135 pub mod RW {
136 #[doc = "LPSPI module is enabled in Doze mode"]
137 pub const DOZEN_0: u32 = 0;
138 #[doc = "LPSPI module is disabled in Doze mode"]
139 pub const DOZEN_1: u32 = 0x01;
140 }
141 }
142 #[doc = "Debug Enable"]
143 pub mod DBGEN {
144 pub const offset: u32 = 3;
145 pub const mask: u32 = 0x01 << offset;
146 pub mod R {}
147 pub mod W {}
148 pub mod RW {
149 #[doc = "LPSPI module is disabled in debug mode"]
150 pub const DBGEN_0: u32 = 0;
151 #[doc = "LPSPI module is enabled in debug mode"]
152 pub const DBGEN_1: u32 = 0x01;
153 }
154 }
155 #[doc = "Reset Transmit FIFO"]
156 pub mod RTF {
157 pub const offset: u32 = 8;
158 pub const mask: u32 = 0x01 << offset;
159 pub mod R {}
160 pub mod W {}
161 pub mod RW {
162 #[doc = "No effect"]
163 pub const RTF_0: u32 = 0;
164 #[doc = "Transmit FIFO is reset"]
165 pub const RTF_1: u32 = 0x01;
166 }
167 }
168 #[doc = "Reset Receive FIFO"]
169 pub mod RRF {
170 pub const offset: u32 = 9;
171 pub const mask: u32 = 0x01 << offset;
172 pub mod R {}
173 pub mod W {}
174 pub mod RW {
175 #[doc = "No effect"]
176 pub const RRF_0: u32 = 0;
177 #[doc = "Receive FIFO is reset"]
178 pub const RRF_1: u32 = 0x01;
179 }
180 }
181}
182#[doc = "Status Register"]
183pub mod SR {
184 #[doc = "Transmit Data Flag"]
185 pub mod TDF {
186 pub const offset: u32 = 0;
187 pub const mask: u32 = 0x01 << offset;
188 pub mod R {}
189 pub mod W {}
190 pub mod RW {
191 #[doc = "Transmit data not requested"]
192 pub const TDF_0: u32 = 0;
193 #[doc = "Transmit data is requested"]
194 pub const TDF_1: u32 = 0x01;
195 }
196 }
197 #[doc = "Receive Data Flag"]
198 pub mod RDF {
199 pub const offset: u32 = 1;
200 pub const mask: u32 = 0x01 << offset;
201 pub mod R {}
202 pub mod W {}
203 pub mod RW {
204 #[doc = "Receive Data is not ready"]
205 pub const RDF_0: u32 = 0;
206 #[doc = "Receive data is ready"]
207 pub const RDF_1: u32 = 0x01;
208 }
209 }
210 #[doc = "Word Complete Flag"]
211 pub mod WCF {
212 pub const offset: u32 = 8;
213 pub const mask: u32 = 0x01 << offset;
214 pub mod R {}
215 pub mod W {}
216 pub mod RW {
217 #[doc = "Transfer of a received word has not yet completed"]
218 pub const WCF_0: u32 = 0;
219 #[doc = "Transfer of a received word has completed"]
220 pub const WCF_1: u32 = 0x01;
221 }
222 }
223 #[doc = "Frame Complete Flag"]
224 pub mod FCF {
225 pub const offset: u32 = 9;
226 pub const mask: u32 = 0x01 << offset;
227 pub mod R {}
228 pub mod W {}
229 pub mod RW {
230 #[doc = "Frame transfer has not completed"]
231 pub const FCF_0: u32 = 0;
232 #[doc = "Frame transfer has completed"]
233 pub const FCF_1: u32 = 0x01;
234 }
235 }
236 #[doc = "Transfer Complete Flag"]
237 pub mod TCF {
238 pub const offset: u32 = 10;
239 pub const mask: u32 = 0x01 << offset;
240 pub mod R {}
241 pub mod W {}
242 pub mod RW {
243 #[doc = "All transfers have not completed"]
244 pub const TCF_0: u32 = 0;
245 #[doc = "All transfers have completed"]
246 pub const TCF_1: u32 = 0x01;
247 }
248 }
249 #[doc = "Transmit Error Flag"]
250 pub mod TEF {
251 pub const offset: u32 = 11;
252 pub const mask: u32 = 0x01 << offset;
253 pub mod R {}
254 pub mod W {}
255 pub mod RW {
256 #[doc = "Transmit FIFO underrun has not occurred"]
257 pub const TEF_0: u32 = 0;
258 #[doc = "Transmit FIFO underrun has occurred"]
259 pub const TEF_1: u32 = 0x01;
260 }
261 }
262 #[doc = "Receive Error Flag"]
263 pub mod REF {
264 pub const offset: u32 = 12;
265 pub const mask: u32 = 0x01 << offset;
266 pub mod R {}
267 pub mod W {}
268 pub mod RW {
269 #[doc = "Receive FIFO has not overflowed"]
270 pub const REF_0: u32 = 0;
271 #[doc = "Receive FIFO has overflowed"]
272 pub const REF_1: u32 = 0x01;
273 }
274 }
275 #[doc = "Data Match Flag"]
276 pub mod DMF {
277 pub const offset: u32 = 13;
278 pub const mask: u32 = 0x01 << offset;
279 pub mod R {}
280 pub mod W {}
281 pub mod RW {
282 #[doc = "Have not received matching data"]
283 pub const DMF_0: u32 = 0;
284 #[doc = "Have received matching data"]
285 pub const DMF_1: u32 = 0x01;
286 }
287 }
288 #[doc = "Module Busy Flag"]
289 pub mod MBF {
290 pub const offset: u32 = 24;
291 pub const mask: u32 = 0x01 << offset;
292 pub mod R {}
293 pub mod W {}
294 pub mod RW {
295 #[doc = "LPSPI is idle"]
296 pub const MBF_0: u32 = 0;
297 #[doc = "LPSPI is busy"]
298 pub const MBF_1: u32 = 0x01;
299 }
300 }
301}
302#[doc = "Interrupt Enable Register"]
303pub mod IER {
304 #[doc = "Transmit Data Interrupt Enable"]
305 pub mod TDIE {
306 pub const offset: u32 = 0;
307 pub const mask: u32 = 0x01 << offset;
308 pub mod R {}
309 pub mod W {}
310 pub mod RW {
311 #[doc = "Disabled"]
312 pub const TDIE_0: u32 = 0;
313 #[doc = "Enabled"]
314 pub const TDIE_1: u32 = 0x01;
315 }
316 }
317 #[doc = "Receive Data Interrupt Enable"]
318 pub mod RDIE {
319 pub const offset: u32 = 1;
320 pub const mask: u32 = 0x01 << offset;
321 pub mod R {}
322 pub mod W {}
323 pub mod RW {
324 #[doc = "Disabled"]
325 pub const RDIE_0: u32 = 0;
326 #[doc = "Enabled"]
327 pub const RDIE_1: u32 = 0x01;
328 }
329 }
330 #[doc = "Word Complete Interrupt Enable"]
331 pub mod WCIE {
332 pub const offset: u32 = 8;
333 pub const mask: u32 = 0x01 << offset;
334 pub mod R {}
335 pub mod W {}
336 pub mod RW {
337 #[doc = "Disabled"]
338 pub const WCIE_0: u32 = 0;
339 #[doc = "Enabled"]
340 pub const WCIE_1: u32 = 0x01;
341 }
342 }
343 #[doc = "Frame Complete Interrupt Enable"]
344 pub mod FCIE {
345 pub const offset: u32 = 9;
346 pub const mask: u32 = 0x01 << offset;
347 pub mod R {}
348 pub mod W {}
349 pub mod RW {
350 #[doc = "Disabled"]
351 pub const FCIE_0: u32 = 0;
352 #[doc = "Enabled"]
353 pub const FCIE_1: u32 = 0x01;
354 }
355 }
356 #[doc = "Transfer Complete Interrupt Enable"]
357 pub mod TCIE {
358 pub const offset: u32 = 10;
359 pub const mask: u32 = 0x01 << offset;
360 pub mod R {}
361 pub mod W {}
362 pub mod RW {
363 #[doc = "Disabled"]
364 pub const TCIE_0: u32 = 0;
365 #[doc = "Enabled"]
366 pub const TCIE_1: u32 = 0x01;
367 }
368 }
369 #[doc = "Transmit Error Interrupt Enable"]
370 pub mod TEIE {
371 pub const offset: u32 = 11;
372 pub const mask: u32 = 0x01 << offset;
373 pub mod R {}
374 pub mod W {}
375 pub mod RW {
376 #[doc = "Disabled"]
377 pub const TEIE_0: u32 = 0;
378 #[doc = "Enabled"]
379 pub const TEIE_1: u32 = 0x01;
380 }
381 }
382 #[doc = "Receive Error Interrupt Enable"]
383 pub mod REIE {
384 pub const offset: u32 = 12;
385 pub const mask: u32 = 0x01 << offset;
386 pub mod R {}
387 pub mod W {}
388 pub mod RW {
389 #[doc = "Disabled"]
390 pub const REIE_0: u32 = 0;
391 #[doc = "Enabled"]
392 pub const REIE_1: u32 = 0x01;
393 }
394 }
395 #[doc = "Data Match Interrupt Enable"]
396 pub mod DMIE {
397 pub const offset: u32 = 13;
398 pub const mask: u32 = 0x01 << offset;
399 pub mod R {}
400 pub mod W {}
401 pub mod RW {
402 #[doc = "Disabled"]
403 pub const DMIE_0: u32 = 0;
404 #[doc = "Enabled"]
405 pub const DMIE_1: u32 = 0x01;
406 }
407 }
408}
409#[doc = "DMA Enable Register"]
410pub mod DER {
411 #[doc = "Transmit Data DMA Enable"]
412 pub mod TDDE {
413 pub const offset: u32 = 0;
414 pub const mask: u32 = 0x01 << offset;
415 pub mod R {}
416 pub mod W {}
417 pub mod RW {
418 #[doc = "DMA request is disabled"]
419 pub const TDDE_0: u32 = 0;
420 #[doc = "DMA request is enabled"]
421 pub const TDDE_1: u32 = 0x01;
422 }
423 }
424 #[doc = "Receive Data DMA Enable"]
425 pub mod RDDE {
426 pub const offset: u32 = 1;
427 pub const mask: u32 = 0x01 << offset;
428 pub mod R {}
429 pub mod W {}
430 pub mod RW {
431 #[doc = "DMA request is disabled"]
432 pub const RDDE_0: u32 = 0;
433 #[doc = "DMA request is enabled"]
434 pub const RDDE_1: u32 = 0x01;
435 }
436 }
437}
438#[doc = "Configuration Register 0"]
439pub mod CFGR0 {
440 #[doc = "Host Request Enable"]
441 pub mod HREN {
442 pub const offset: u32 = 0;
443 pub const mask: u32 = 0x01 << offset;
444 pub mod R {}
445 pub mod W {}
446 pub mod RW {}
447 }
448 #[doc = "Host Request Polarity"]
449 pub mod HRPOL {
450 pub const offset: u32 = 1;
451 pub const mask: u32 = 0x01 << offset;
452 pub mod R {}
453 pub mod W {}
454 pub mod RW {}
455 }
456 #[doc = "Host Request Select"]
457 pub mod HRSEL {
458 pub const offset: u32 = 2;
459 pub const mask: u32 = 0x01 << offset;
460 pub mod R {}
461 pub mod W {}
462 pub mod RW {}
463 }
464 #[doc = "Circular FIFO Enable"]
465 pub mod CIRFIFO {
466 pub const offset: u32 = 8;
467 pub const mask: u32 = 0x01 << offset;
468 pub mod R {}
469 pub mod W {}
470 pub mod RW {
471 #[doc = "Circular FIFO is disabled"]
472 pub const CIRFIFO_0: u32 = 0;
473 #[doc = "Circular FIFO is enabled"]
474 pub const CIRFIFO_1: u32 = 0x01;
475 }
476 }
477 #[doc = "Receive Data Match Only"]
478 pub mod RDMO {
479 pub const offset: u32 = 9;
480 pub const mask: u32 = 0x01 << offset;
481 pub mod R {}
482 pub mod W {}
483 pub mod RW {
484 #[doc = "Received data is stored in the receive FIFO as in normal operations"]
485 pub const RDMO_0: u32 = 0;
486 #[doc = "Received data is discarded unless the Data Match Flag (DMF) is set"]
487 pub const RDMO_1: u32 = 0x01;
488 }
489 }
490}
491#[doc = "Configuration Register 1"]
492pub mod CFGR1 {
493 #[doc = "Master Mode"]
494 pub mod MASTER {
495 pub const offset: u32 = 0;
496 pub const mask: u32 = 0x01 << offset;
497 pub mod R {}
498 pub mod W {}
499 pub mod RW {
500 #[doc = "Slave mode"]
501 pub const MASTER_0: u32 = 0;
502 #[doc = "Master mode"]
503 pub const MASTER_1: u32 = 0x01;
504 }
505 }
506 #[doc = "Sample Point"]
507 pub mod SAMPLE {
508 pub const offset: u32 = 1;
509 pub const mask: u32 = 0x01 << offset;
510 pub mod R {}
511 pub mod W {}
512 pub mod RW {
513 #[doc = "Input data is sampled on SCK edge"]
514 pub const SAMPLE_0: u32 = 0;
515 #[doc = "Input data is sampled on delayed SCK edge"]
516 pub const SAMPLE_1: u32 = 0x01;
517 }
518 }
519 #[doc = "Automatic PCS"]
520 pub mod AUTOPCS {
521 pub const offset: u32 = 2;
522 pub const mask: u32 = 0x01 << offset;
523 pub mod R {}
524 pub mod W {}
525 pub mod RW {
526 #[doc = "Automatic PCS generation is disabled"]
527 pub const AUTOPCS_0: u32 = 0;
528 #[doc = "Automatic PCS generation is enabled"]
529 pub const AUTOPCS_1: u32 = 0x01;
530 }
531 }
532 #[doc = "No Stall"]
533 pub mod NOSTALL {
534 pub const offset: u32 = 3;
535 pub const mask: u32 = 0x01 << offset;
536 pub mod R {}
537 pub mod W {}
538 pub mod RW {
539 #[doc = "Transfers will stall when the transmit FIFO is empty or the receive FIFO is full"]
540 pub const NOSTALL_0: u32 = 0;
541 #[doc = "Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur"]
542 pub const NOSTALL_1: u32 = 0x01;
543 }
544 }
545 #[doc = "Peripheral Chip Select Polarity"]
546 pub mod PCSPOL {
547 pub const offset: u32 = 8;
548 pub const mask: u32 = 0x0f << offset;
549 pub mod R {}
550 pub mod W {}
551 pub mod RW {}
552 }
553 #[doc = "Match Configuration"]
554 pub mod MATCFG {
555 pub const offset: u32 = 16;
556 pub const mask: u32 = 0x07 << offset;
557 pub mod R {}
558 pub mod W {}
559 pub mod RW {
560 #[doc = "Match is disabled"]
561 pub const MATCFG_0: u32 = 0;
562 #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"]
563 pub const MATCFG_2: u32 = 0x02;
564 #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"]
565 pub const MATCFG_3: u32 = 0x03;
566 #[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., \\[(1st data word = MATCH0) * (2nd data word = MATCH1)\\]"]
567 pub const MATCFG_4: u32 = 0x04;
568 #[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., \\[(any data word = MATCH0) * (next data word = MATCH1)\\]"]
569 pub const MATCFG_5: u32 = 0x05;
570 #[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(1st data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
571 pub const MATCFG_6: u32 = 0x06;
572 #[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(any data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
573 pub const MATCFG_7: u32 = 0x07;
574 }
575 }
576 #[doc = "Pin Configuration"]
577 pub mod PINCFG {
578 pub const offset: u32 = 24;
579 pub const mask: u32 = 0x03 << offset;
580 pub mod R {}
581 pub mod W {}
582 pub mod RW {
583 #[doc = "SIN is used for input data and SOUT is used for output data"]
584 pub const PINCFG_0: u32 = 0;
585 #[doc = "SIN is used for both input and output data"]
586 pub const PINCFG_1: u32 = 0x01;
587 #[doc = "SOUT is used for both input and output data"]
588 pub const PINCFG_2: u32 = 0x02;
589 #[doc = "SOUT is used for input data and SIN is used for output data"]
590 pub const PINCFG_3: u32 = 0x03;
591 }
592 }
593 #[doc = "Output Config"]
594 pub mod OUTCFG {
595 pub const offset: u32 = 26;
596 pub const mask: u32 = 0x01 << offset;
597 pub mod R {}
598 pub mod W {}
599 pub mod RW {
600 #[doc = "Output data retains last value when chip select is negated"]
601 pub const OUTCFG_0: u32 = 0;
602 #[doc = "Output data is tristated when chip select is negated"]
603 pub const OUTCFG_1: u32 = 0x01;
604 }
605 }
606 #[doc = "Peripheral Chip Select Configuration"]
607 pub mod PCSCFG {
608 pub const offset: u32 = 27;
609 pub const mask: u32 = 0x01 << offset;
610 pub mod R {}
611 pub mod W {}
612 pub mod RW {
613 #[doc = "PCS\\[3:2\\] are enabled"]
614 pub const PCSCFG_0: u32 = 0;
615 #[doc = "PCS\\[3:2\\] are disabled"]
616 pub const PCSCFG_1: u32 = 0x01;
617 }
618 }
619}
620#[doc = "Data Match Register 0"]
621pub mod DMR0 {
622 #[doc = "Match 0 Value"]
623 pub mod MATCH0 {
624 pub const offset: u32 = 0;
625 pub const mask: u32 = 0xffff_ffff << offset;
626 pub mod R {}
627 pub mod W {}
628 pub mod RW {}
629 }
630}
631#[doc = "Data Match Register 1"]
632pub mod DMR1 {
633 #[doc = "Match 1 Value"]
634 pub mod MATCH1 {
635 pub const offset: u32 = 0;
636 pub const mask: u32 = 0xffff_ffff << offset;
637 pub mod R {}
638 pub mod W {}
639 pub mod RW {}
640 }
641}
642#[doc = "Clock Configuration Register"]
643pub mod CCR {
644 #[doc = "SCK Divider"]
645 pub mod SCKDIV {
646 pub const offset: u32 = 0;
647 pub const mask: u32 = 0xff << offset;
648 pub mod R {}
649 pub mod W {}
650 pub mod RW {}
651 }
652 #[doc = "Delay Between Transfers"]
653 pub mod DBT {
654 pub const offset: u32 = 8;
655 pub const mask: u32 = 0xff << offset;
656 pub mod R {}
657 pub mod W {}
658 pub mod RW {}
659 }
660 #[doc = "PCS-to-SCK Delay"]
661 pub mod PCSSCK {
662 pub const offset: u32 = 16;
663 pub const mask: u32 = 0xff << offset;
664 pub mod R {}
665 pub mod W {}
666 pub mod RW {}
667 }
668 #[doc = "SCK-to-PCS Delay"]
669 pub mod SCKPCS {
670 pub const offset: u32 = 24;
671 pub const mask: u32 = 0xff << offset;
672 pub mod R {}
673 pub mod W {}
674 pub mod RW {}
675 }
676}
677#[doc = "FIFO Control Register"]
678pub mod FCR {
679 #[doc = "Transmit FIFO Watermark"]
680 pub mod TXWATER {
681 pub const offset: u32 = 0;
682 pub const mask: u32 = 0x0f << offset;
683 pub mod R {}
684 pub mod W {}
685 pub mod RW {}
686 }
687 #[doc = "Receive FIFO Watermark"]
688 pub mod RXWATER {
689 pub const offset: u32 = 16;
690 pub const mask: u32 = 0x0f << offset;
691 pub mod R {}
692 pub mod W {}
693 pub mod RW {}
694 }
695}
696#[doc = "FIFO Status Register"]
697pub mod FSR {
698 #[doc = "Transmit FIFO Count"]
699 pub mod TXCOUNT {
700 pub const offset: u32 = 0;
701 pub const mask: u32 = 0x1f << offset;
702 pub mod R {}
703 pub mod W {}
704 pub mod RW {}
705 }
706 #[doc = "Receive FIFO Count"]
707 pub mod RXCOUNT {
708 pub const offset: u32 = 16;
709 pub const mask: u32 = 0x1f << offset;
710 pub mod R {}
711 pub mod W {}
712 pub mod RW {}
713 }
714}
715#[doc = "Transmit Command Register"]
716pub mod TCR {
717 #[doc = "Frame Size"]
718 pub mod FRAMESZ {
719 pub const offset: u32 = 0;
720 pub const mask: u32 = 0x0fff << offset;
721 pub mod R {}
722 pub mod W {}
723 pub mod RW {}
724 }
725 #[doc = "Transfer Width"]
726 pub mod WIDTH {
727 pub const offset: u32 = 16;
728 pub const mask: u32 = 0x03 << offset;
729 pub mod R {}
730 pub mod W {}
731 pub mod RW {
732 #[doc = "1 bit transfer"]
733 pub const WIDTH_0: u32 = 0;
734 #[doc = "2 bit transfer"]
735 pub const WIDTH_1: u32 = 0x01;
736 #[doc = "4 bit transfer"]
737 pub const WIDTH_2: u32 = 0x02;
738 }
739 }
740 #[doc = "Transmit Data Mask"]
741 pub mod TXMSK {
742 pub const offset: u32 = 18;
743 pub const mask: u32 = 0x01 << offset;
744 pub mod R {}
745 pub mod W {}
746 pub mod RW {
747 #[doc = "Normal transfer"]
748 pub const TXMSK_0: u32 = 0;
749 #[doc = "Mask transmit data"]
750 pub const TXMSK_1: u32 = 0x01;
751 }
752 }
753 #[doc = "Receive Data Mask"]
754 pub mod RXMSK {
755 pub const offset: u32 = 19;
756 pub const mask: u32 = 0x01 << offset;
757 pub mod R {}
758 pub mod W {}
759 pub mod RW {
760 #[doc = "Normal transfer"]
761 pub const RXMSK_0: u32 = 0;
762 #[doc = "Receive data is masked"]
763 pub const RXMSK_1: u32 = 0x01;
764 }
765 }
766 #[doc = "Continuing Command"]
767 pub mod CONTC {
768 pub const offset: u32 = 20;
769 pub const mask: u32 = 0x01 << offset;
770 pub mod R {}
771 pub mod W {}
772 pub mod RW {
773 #[doc = "Command word for start of new transfer"]
774 pub const CONTC_0: u32 = 0;
775 #[doc = "Command word for continuing transfer"]
776 pub const CONTC_1: u32 = 0x01;
777 }
778 }
779 #[doc = "Continuous Transfer"]
780 pub mod CONT {
781 pub const offset: u32 = 21;
782 pub const mask: u32 = 0x01 << offset;
783 pub mod R {}
784 pub mod W {}
785 pub mod RW {
786 #[doc = "Continuous transfer is disabled"]
787 pub const CONT_0: u32 = 0;
788 #[doc = "Continuous transfer is enabled"]
789 pub const CONT_1: u32 = 0x01;
790 }
791 }
792 #[doc = "Byte Swap"]
793 pub mod BYSW {
794 pub const offset: u32 = 22;
795 pub const mask: u32 = 0x01 << offset;
796 pub mod R {}
797 pub mod W {}
798 pub mod RW {
799 #[doc = "Byte swap is disabled"]
800 pub const BYSW_0: u32 = 0;
801 #[doc = "Byte swap is enabled"]
802 pub const BYSW_1: u32 = 0x01;
803 }
804 }
805 #[doc = "LSB First"]
806 pub mod LSBF {
807 pub const offset: u32 = 23;
808 pub const mask: u32 = 0x01 << offset;
809 pub mod R {}
810 pub mod W {}
811 pub mod RW {
812 #[doc = "Data is transferred MSB first"]
813 pub const LSBF_0: u32 = 0;
814 #[doc = "Data is transferred LSB first"]
815 pub const LSBF_1: u32 = 0x01;
816 }
817 }
818 #[doc = "Peripheral Chip Select"]
819 pub mod PCS {
820 pub const offset: u32 = 24;
821 pub const mask: u32 = 0x03 << offset;
822 pub mod R {}
823 pub mod W {}
824 pub mod RW {
825 #[doc = "Transfer using LPSPI_PCS\\[0\\]"]
826 pub const PCS_0: u32 = 0;
827 #[doc = "Transfer using LPSPI_PCS\\[1\\]"]
828 pub const PCS_1: u32 = 0x01;
829 #[doc = "Transfer using LPSPI_PCS\\[2\\]"]
830 pub const PCS_2: u32 = 0x02;
831 #[doc = "Transfer using LPSPI_PCS\\[3\\]"]
832 pub const PCS_3: u32 = 0x03;
833 }
834 }
835 #[doc = "Prescaler Value"]
836 pub mod PRESCALE {
837 pub const offset: u32 = 27;
838 pub const mask: u32 = 0x07 << offset;
839 pub mod R {}
840 pub mod W {}
841 pub mod RW {
842 #[doc = "Divide by 1"]
843 pub const PRESCALE_0: u32 = 0;
844 #[doc = "Divide by 2"]
845 pub const PRESCALE_1: u32 = 0x01;
846 #[doc = "Divide by 4"]
847 pub const PRESCALE_2: u32 = 0x02;
848 #[doc = "Divide by 8"]
849 pub const PRESCALE_3: u32 = 0x03;
850 #[doc = "Divide by 16"]
851 pub const PRESCALE_4: u32 = 0x04;
852 #[doc = "Divide by 32"]
853 pub const PRESCALE_5: u32 = 0x05;
854 #[doc = "Divide by 64"]
855 pub const PRESCALE_6: u32 = 0x06;
856 #[doc = "Divide by 128"]
857 pub const PRESCALE_7: u32 = 0x07;
858 }
859 }
860 #[doc = "Clock Phase"]
861 pub mod CPHA {
862 pub const offset: u32 = 30;
863 pub const mask: u32 = 0x01 << offset;
864 pub mod R {}
865 pub mod W {}
866 pub mod RW {
867 #[doc = "Data is captured on the leading edge of SCK and changed on the following edge of SCK"]
868 pub const CPHA_0: u32 = 0;
869 #[doc = "Data is changed on the leading edge of SCK and captured on the following edge of SCK"]
870 pub const CPHA_1: u32 = 0x01;
871 }
872 }
873 #[doc = "Clock Polarity"]
874 pub mod CPOL {
875 pub const offset: u32 = 31;
876 pub const mask: u32 = 0x01 << offset;
877 pub mod R {}
878 pub mod W {}
879 pub mod RW {
880 #[doc = "The inactive state value of SCK is low"]
881 pub const CPOL_0: u32 = 0;
882 #[doc = "The inactive state value of SCK is high"]
883 pub const CPOL_1: u32 = 0x01;
884 }
885 }
886}
887#[doc = "Transmit Data Register"]
888pub mod TDR {
889 #[doc = "Transmit Data"]
890 pub mod DATA {
891 pub const offset: u32 = 0;
892 pub const mask: u32 = 0xffff_ffff << offset;
893 pub mod R {}
894 pub mod W {}
895 pub mod RW {}
896 }
897}
898#[doc = "Receive Status Register"]
899pub mod RSR {
900 #[doc = "Start Of Frame"]
901 pub mod SOF {
902 pub const offset: u32 = 0;
903 pub const mask: u32 = 0x01 << offset;
904 pub mod R {}
905 pub mod W {}
906 pub mod RW {
907 #[doc = "Subsequent data word received after LPSPI_PCS assertion"]
908 pub const SOF_0: u32 = 0;
909 #[doc = "First data word received after LPSPI_PCS assertion"]
910 pub const SOF_1: u32 = 0x01;
911 }
912 }
913 #[doc = "RX FIFO Empty"]
914 pub mod RXEMPTY {
915 pub const offset: u32 = 1;
916 pub const mask: u32 = 0x01 << offset;
917 pub mod R {}
918 pub mod W {}
919 pub mod RW {
920 #[doc = "RX FIFO is not empty"]
921 pub const RXEMPTY_0: u32 = 0;
922 #[doc = "RX FIFO is empty"]
923 pub const RXEMPTY_1: u32 = 0x01;
924 }
925 }
926}
927#[doc = "Receive Data Register"]
928pub mod RDR {
929 #[doc = "Receive Data"]
930 pub mod DATA {
931 pub const offset: u32 = 0;
932 pub const mask: u32 = 0xffff_ffff << offset;
933 pub mod R {}
934 pub mod W {}
935 pub mod RW {}
936 }
937}