rp2040_pac/pads_qspi/
gpio_qspi_sclk.rs

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1#[doc = "Register `GPIO_QSPI_SCLK` reader"]
2pub type R = crate::R<GPIO_QSPI_SCLK_SPEC>;
3#[doc = "Register `GPIO_QSPI_SCLK` writer"]
4pub type W = crate::W<GPIO_QSPI_SCLK_SPEC>;
5#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"]
6pub type SLEWFAST_R = crate::BitReader;
7#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"]
8pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"]
10pub type SCHMITT_R = crate::BitReader;
11#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"]
12pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PDE` reader - Pull down enable"]
14pub type PDE_R = crate::BitReader;
15#[doc = "Field `PDE` writer - Pull down enable"]
16pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PUE` reader - Pull up enable"]
18pub type PUE_R = crate::BitReader;
19#[doc = "Field `PUE` writer - Pull up enable"]
20pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DRIVE` reader - Drive strength."]
22pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
23#[doc = "Drive strength.  
24
25Value on reset: 1"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27#[repr(u8)]
28pub enum DRIVE_A {
29    #[doc = "0: `0`"]
30    _2M_A = 0,
31    #[doc = "1: `1`"]
32    _4M_A = 1,
33    #[doc = "2: `10`"]
34    _8M_A = 2,
35    #[doc = "3: `11`"]
36    _12M_A = 3,
37}
38impl From<DRIVE_A> for u8 {
39    #[inline(always)]
40    fn from(variant: DRIVE_A) -> Self {
41        variant as _
42    }
43}
44impl crate::FieldSpec for DRIVE_A {
45    type Ux = u8;
46}
47impl DRIVE_R {
48    #[doc = "Get enumerated values variant"]
49    #[inline(always)]
50    pub const fn variant(&self) -> DRIVE_A {
51        match self.bits {
52            0 => DRIVE_A::_2M_A,
53            1 => DRIVE_A::_4M_A,
54            2 => DRIVE_A::_8M_A,
55            3 => DRIVE_A::_12M_A,
56            _ => unreachable!(),
57        }
58    }
59    #[doc = "`0`"]
60    #[inline(always)]
61    pub fn is_2m_a(&self) -> bool {
62        *self == DRIVE_A::_2M_A
63    }
64    #[doc = "`1`"]
65    #[inline(always)]
66    pub fn is_4m_a(&self) -> bool {
67        *self == DRIVE_A::_4M_A
68    }
69    #[doc = "`10`"]
70    #[inline(always)]
71    pub fn is_8m_a(&self) -> bool {
72        *self == DRIVE_A::_8M_A
73    }
74    #[doc = "`11`"]
75    #[inline(always)]
76    pub fn is_12m_a(&self) -> bool {
77        *self == DRIVE_A::_12M_A
78    }
79}
80#[doc = "Field `DRIVE` writer - Drive strength."]
81pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
82impl<'a, REG> DRIVE_W<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn _2m_a(self) -> &'a mut crate::W<REG> {
90        self.variant(DRIVE_A::_2M_A)
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn _4m_a(self) -> &'a mut crate::W<REG> {
95        self.variant(DRIVE_A::_4M_A)
96    }
97    #[doc = "`10`"]
98    #[inline(always)]
99    pub fn _8m_a(self) -> &'a mut crate::W<REG> {
100        self.variant(DRIVE_A::_8M_A)
101    }
102    #[doc = "`11`"]
103    #[inline(always)]
104    pub fn _12m_a(self) -> &'a mut crate::W<REG> {
105        self.variant(DRIVE_A::_12M_A)
106    }
107}
108#[doc = "Field `IE` reader - Input enable"]
109pub type IE_R = crate::BitReader;
110#[doc = "Field `IE` writer - Input enable"]
111pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>;
112#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"]
113pub type OD_R = crate::BitReader;
114#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"]
115pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>;
116impl R {
117    #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
118    #[inline(always)]
119    pub fn slewfast(&self) -> SLEWFAST_R {
120        SLEWFAST_R::new((self.bits & 1) != 0)
121    }
122    #[doc = "Bit 1 - Enable schmitt trigger"]
123    #[inline(always)]
124    pub fn schmitt(&self) -> SCHMITT_R {
125        SCHMITT_R::new(((self.bits >> 1) & 1) != 0)
126    }
127    #[doc = "Bit 2 - Pull down enable"]
128    #[inline(always)]
129    pub fn pde(&self) -> PDE_R {
130        PDE_R::new(((self.bits >> 2) & 1) != 0)
131    }
132    #[doc = "Bit 3 - Pull up enable"]
133    #[inline(always)]
134    pub fn pue(&self) -> PUE_R {
135        PUE_R::new(((self.bits >> 3) & 1) != 0)
136    }
137    #[doc = "Bits 4:5 - Drive strength."]
138    #[inline(always)]
139    pub fn drive(&self) -> DRIVE_R {
140        DRIVE_R::new(((self.bits >> 4) & 3) as u8)
141    }
142    #[doc = "Bit 6 - Input enable"]
143    #[inline(always)]
144    pub fn ie(&self) -> IE_R {
145        IE_R::new(((self.bits >> 6) & 1) != 0)
146    }
147    #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
148    #[inline(always)]
149    pub fn od(&self) -> OD_R {
150        OD_R::new(((self.bits >> 7) & 1) != 0)
151    }
152}
153impl W {
154    #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
155    #[inline(always)]
156    #[must_use]
157    pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_QSPI_SCLK_SPEC> {
158        SLEWFAST_W::new(self, 0)
159    }
160    #[doc = "Bit 1 - Enable schmitt trigger"]
161    #[inline(always)]
162    #[must_use]
163    pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_QSPI_SCLK_SPEC> {
164        SCHMITT_W::new(self, 1)
165    }
166    #[doc = "Bit 2 - Pull down enable"]
167    #[inline(always)]
168    #[must_use]
169    pub fn pde(&mut self) -> PDE_W<GPIO_QSPI_SCLK_SPEC> {
170        PDE_W::new(self, 2)
171    }
172    #[doc = "Bit 3 - Pull up enable"]
173    #[inline(always)]
174    #[must_use]
175    pub fn pue(&mut self) -> PUE_W<GPIO_QSPI_SCLK_SPEC> {
176        PUE_W::new(self, 3)
177    }
178    #[doc = "Bits 4:5 - Drive strength."]
179    #[inline(always)]
180    #[must_use]
181    pub fn drive(&mut self) -> DRIVE_W<GPIO_QSPI_SCLK_SPEC> {
182        DRIVE_W::new(self, 4)
183    }
184    #[doc = "Bit 6 - Input enable"]
185    #[inline(always)]
186    #[must_use]
187    pub fn ie(&mut self) -> IE_W<GPIO_QSPI_SCLK_SPEC> {
188        IE_W::new(self, 6)
189    }
190    #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
191    #[inline(always)]
192    #[must_use]
193    pub fn od(&mut self) -> OD_W<GPIO_QSPI_SCLK_SPEC> {
194        OD_W::new(self, 7)
195    }
196    #[doc = r" Writes raw bits to the register."]
197    #[doc = r""]
198    #[doc = r" # Safety"]
199    #[doc = r""]
200    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
201    #[inline(always)]
202    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
203        self.bits = bits;
204        self
205    }
206}
207#[doc = "Pad control register  
208
209You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sclk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
210pub struct GPIO_QSPI_SCLK_SPEC;
211impl crate::RegisterSpec for GPIO_QSPI_SCLK_SPEC {
212    type Ux = u32;
213}
214#[doc = "`read()` method returns [`gpio_qspi_sclk::R`](R) reader structure"]
215impl crate::Readable for GPIO_QSPI_SCLK_SPEC {}
216#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sclk::W`](W) writer structure"]
217impl crate::Writable for GPIO_QSPI_SCLK_SPEC {
218    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
219    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
220}
221#[doc = "`reset()` method sets GPIO_QSPI_SCLK to value 0x56"]
222impl crate::Resettable for GPIO_QSPI_SCLK_SPEC {
223    const RESET_VALUE: u32 = 0x56;
224}
rp2040_pac/pads_qspi/gpio_qspi_sclk.rs

rp2040_pac/pads_qspi/
gpio_qspi_sclk.rs
