rp2040_pac/usbctrl_regs/
sie_ctrl.rs
1#[doc = "Register `SIE_CTRL` reader"]
2pub type R = crate::R<SIE_CTRL_SPEC>;
3#[doc = "Register `SIE_CTRL` writer"]
4pub type W = crate::W<SIE_CTRL_SPEC>;
5#[doc = "Field `START_TRANS` reader - Host: Start transaction"]
6pub type START_TRANS_R = crate::BitReader;
7#[doc = "Field `START_TRANS` writer - Host: Start transaction"]
8pub type START_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SEND_SETUP` reader - Host: Send Setup packet"]
10pub type SEND_SETUP_R = crate::BitReader;
11#[doc = "Field `SEND_SETUP` writer - Host: Send Setup packet"]
12pub type SEND_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SEND_DATA` reader - Host: Send transaction (OUT from host)"]
14pub type SEND_DATA_R = crate::BitReader;
15#[doc = "Field `SEND_DATA` writer - Host: Send transaction (OUT from host)"]
16pub type SEND_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RECEIVE_DATA` reader - Host: Receive transaction (IN to host)"]
18pub type RECEIVE_DATA_R = crate::BitReader;
19#[doc = "Field `RECEIVE_DATA` writer - Host: Receive transaction (IN to host)"]
20pub type RECEIVE_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `STOP_TRANS` reader - Host: Stop transaction"]
22pub type STOP_TRANS_R = crate::BitReader;
23#[doc = "Field `STOP_TRANS` writer - Host: Stop transaction"]
24pub type STOP_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PREAMBLE_EN` reader - Host: Preable enable for LS device on FS hub"]
26pub type PREAMBLE_EN_R = crate::BitReader;
27#[doc = "Field `PREAMBLE_EN` writer - Host: Preable enable for LS device on FS hub"]
28pub type PREAMBLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SOF_SYNC` reader - Host: Delay packet(s) until after SOF"]
30pub type SOF_SYNC_R = crate::BitReader;
31#[doc = "Field `SOF_SYNC` writer - Host: Delay packet(s) until after SOF"]
32pub type SOF_SYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SOF_EN` reader - Host: Enable SOF generation (for full speed bus)"]
34pub type SOF_EN_R = crate::BitReader;
35#[doc = "Field `SOF_EN` writer - Host: Enable SOF generation (for full speed bus)"]
36pub type SOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `KEEP_ALIVE_EN` reader - Host: Enable keep alive packet (for low speed bus)"]
38pub type KEEP_ALIVE_EN_R = crate::BitReader;
39#[doc = "Field `KEEP_ALIVE_EN` writer - Host: Enable keep alive packet (for low speed bus)"]
40pub type KEEP_ALIVE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `VBUS_EN` reader - Host: Enable VBUS"]
42pub type VBUS_EN_R = crate::BitReader;
43#[doc = "Field `VBUS_EN` writer - Host: Enable VBUS"]
44pub type VBUS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `RESUME` reader - Device: Remote wakeup. Device can initiate its own resume after suspend."]
46pub type RESUME_R = crate::BitReader;
47#[doc = "Field `RESUME` writer - Device: Remote wakeup. Device can initiate its own resume after suspend."]
48pub type RESUME_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RESET_BUS` reader - Host: Reset bus"]
50pub type RESET_BUS_R = crate::BitReader;
51#[doc = "Field `RESET_BUS` writer - Host: Reset bus"]
52pub type RESET_BUS_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `PULLDOWN_EN` reader - Host: Enable pull down resistors"]
54pub type PULLDOWN_EN_R = crate::BitReader;
55#[doc = "Field `PULLDOWN_EN` writer - Host: Enable pull down resistors"]
56pub type PULLDOWN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `PULLUP_EN` reader - Device: Enable pull up resistor"]
58pub type PULLUP_EN_R = crate::BitReader;
59#[doc = "Field `PULLUP_EN` writer - Device: Enable pull up resistor"]
60pub type PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `RPU_OPT` reader - Device: Pull-up strength (0=1K2, 1=2k3)"]
62pub type RPU_OPT_R = crate::BitReader;
63#[doc = "Field `RPU_OPT` writer - Device: Pull-up strength (0=1K2, 1=2k3)"]
64pub type RPU_OPT_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `TRANSCEIVER_PD` reader - Power down bus transceiver"]
66pub type TRANSCEIVER_PD_R = crate::BitReader;
67#[doc = "Field `TRANSCEIVER_PD` writer - Power down bus transceiver"]
68pub type TRANSCEIVER_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `DIRECT_DM` reader - Direct control of DM"]
70pub type DIRECT_DM_R = crate::BitReader;
71#[doc = "Field `DIRECT_DM` writer - Direct control of DM"]
72pub type DIRECT_DM_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `DIRECT_DP` reader - Direct control of DP"]
74pub type DIRECT_DP_R = crate::BitReader;
75#[doc = "Field `DIRECT_DP` writer - Direct control of DP"]
76pub type DIRECT_DP_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `DIRECT_EN` reader - Direct bus drive enable"]
78pub type DIRECT_EN_R = crate::BitReader;
79#[doc = "Field `DIRECT_EN` writer - Direct bus drive enable"]
80pub type DIRECT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `EP0_INT_NAK` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"]
82pub type EP0_INT_NAK_R = crate::BitReader;
83#[doc = "Field `EP0_INT_NAK` writer - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"]
84pub type EP0_INT_NAK_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `EP0_INT_2BUF` reader - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"]
86pub type EP0_INT_2BUF_R = crate::BitReader;
87#[doc = "Field `EP0_INT_2BUF` writer - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"]
88pub type EP0_INT_2BUF_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `EP0_INT_1BUF` reader - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"]
90pub type EP0_INT_1BUF_R = crate::BitReader;
91#[doc = "Field `EP0_INT_1BUF` writer - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"]
92pub type EP0_INT_1BUF_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `EP0_DOUBLE_BUF` reader - Device: EP0 single buffered = 0, double buffered = 1"]
94pub type EP0_DOUBLE_BUF_R = crate::BitReader;
95#[doc = "Field `EP0_DOUBLE_BUF` writer - Device: EP0 single buffered = 0, double buffered = 1"]
96pub type EP0_DOUBLE_BUF_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `EP0_INT_STALL` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"]
98pub type EP0_INT_STALL_R = crate::BitReader;
99#[doc = "Field `EP0_INT_STALL` writer - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"]
100pub type EP0_INT_STALL_W<'a, REG> = crate::BitWriter<'a, REG>;
101impl R {
102 #[doc = "Bit 0 - Host: Start transaction"]
103 #[inline(always)]
104 pub fn start_trans(&self) -> START_TRANS_R {
105 START_TRANS_R::new((self.bits & 1) != 0)
106 }
107 #[doc = "Bit 1 - Host: Send Setup packet"]
108 #[inline(always)]
109 pub fn send_setup(&self) -> SEND_SETUP_R {
110 SEND_SETUP_R::new(((self.bits >> 1) & 1) != 0)
111 }
112 #[doc = "Bit 2 - Host: Send transaction (OUT from host)"]
113 #[inline(always)]
114 pub fn send_data(&self) -> SEND_DATA_R {
115 SEND_DATA_R::new(((self.bits >> 2) & 1) != 0)
116 }
117 #[doc = "Bit 3 - Host: Receive transaction (IN to host)"]
118 #[inline(always)]
119 pub fn receive_data(&self) -> RECEIVE_DATA_R {
120 RECEIVE_DATA_R::new(((self.bits >> 3) & 1) != 0)
121 }
122 #[doc = "Bit 4 - Host: Stop transaction"]
123 #[inline(always)]
124 pub fn stop_trans(&self) -> STOP_TRANS_R {
125 STOP_TRANS_R::new(((self.bits >> 4) & 1) != 0)
126 }
127 #[doc = "Bit 6 - Host: Preable enable for LS device on FS hub"]
128 #[inline(always)]
129 pub fn preamble_en(&self) -> PREAMBLE_EN_R {
130 PREAMBLE_EN_R::new(((self.bits >> 6) & 1) != 0)
131 }
132 #[doc = "Bit 8 - Host: Delay packet(s) until after SOF"]
133 #[inline(always)]
134 pub fn sof_sync(&self) -> SOF_SYNC_R {
135 SOF_SYNC_R::new(((self.bits >> 8) & 1) != 0)
136 }
137 #[doc = "Bit 9 - Host: Enable SOF generation (for full speed bus)"]
138 #[inline(always)]
139 pub fn sof_en(&self) -> SOF_EN_R {
140 SOF_EN_R::new(((self.bits >> 9) & 1) != 0)
141 }
142 #[doc = "Bit 10 - Host: Enable keep alive packet (for low speed bus)"]
143 #[inline(always)]
144 pub fn keep_alive_en(&self) -> KEEP_ALIVE_EN_R {
145 KEEP_ALIVE_EN_R::new(((self.bits >> 10) & 1) != 0)
146 }
147 #[doc = "Bit 11 - Host: Enable VBUS"]
148 #[inline(always)]
149 pub fn vbus_en(&self) -> VBUS_EN_R {
150 VBUS_EN_R::new(((self.bits >> 11) & 1) != 0)
151 }
152 #[doc = "Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend."]
153 #[inline(always)]
154 pub fn resume(&self) -> RESUME_R {
155 RESUME_R::new(((self.bits >> 12) & 1) != 0)
156 }
157 #[doc = "Bit 13 - Host: Reset bus"]
158 #[inline(always)]
159 pub fn reset_bus(&self) -> RESET_BUS_R {
160 RESET_BUS_R::new(((self.bits >> 13) & 1) != 0)
161 }
162 #[doc = "Bit 15 - Host: Enable pull down resistors"]
163 #[inline(always)]
164 pub fn pulldown_en(&self) -> PULLDOWN_EN_R {
165 PULLDOWN_EN_R::new(((self.bits >> 15) & 1) != 0)
166 }
167 #[doc = "Bit 16 - Device: Enable pull up resistor"]
168 #[inline(always)]
169 pub fn pullup_en(&self) -> PULLUP_EN_R {
170 PULLUP_EN_R::new(((self.bits >> 16) & 1) != 0)
171 }
172 #[doc = "Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)"]
173 #[inline(always)]
174 pub fn rpu_opt(&self) -> RPU_OPT_R {
175 RPU_OPT_R::new(((self.bits >> 17) & 1) != 0)
176 }
177 #[doc = "Bit 18 - Power down bus transceiver"]
178 #[inline(always)]
179 pub fn transceiver_pd(&self) -> TRANSCEIVER_PD_R {
180 TRANSCEIVER_PD_R::new(((self.bits >> 18) & 1) != 0)
181 }
182 #[doc = "Bit 24 - Direct control of DM"]
183 #[inline(always)]
184 pub fn direct_dm(&self) -> DIRECT_DM_R {
185 DIRECT_DM_R::new(((self.bits >> 24) & 1) != 0)
186 }
187 #[doc = "Bit 25 - Direct control of DP"]
188 #[inline(always)]
189 pub fn direct_dp(&self) -> DIRECT_DP_R {
190 DIRECT_DP_R::new(((self.bits >> 25) & 1) != 0)
191 }
192 #[doc = "Bit 26 - Direct bus drive enable"]
193 #[inline(always)]
194 pub fn direct_en(&self) -> DIRECT_EN_R {
195 DIRECT_EN_R::new(((self.bits >> 26) & 1) != 0)
196 }
197 #[doc = "Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"]
198 #[inline(always)]
199 pub fn ep0_int_nak(&self) -> EP0_INT_NAK_R {
200 EP0_INT_NAK_R::new(((self.bits >> 27) & 1) != 0)
201 }
202 #[doc = "Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"]
203 #[inline(always)]
204 pub fn ep0_int_2buf(&self) -> EP0_INT_2BUF_R {
205 EP0_INT_2BUF_R::new(((self.bits >> 28) & 1) != 0)
206 }
207 #[doc = "Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"]
208 #[inline(always)]
209 pub fn ep0_int_1buf(&self) -> EP0_INT_1BUF_R {
210 EP0_INT_1BUF_R::new(((self.bits >> 29) & 1) != 0)
211 }
212 #[doc = "Bit 30 - Device: EP0 single buffered = 0, double buffered = 1"]
213 #[inline(always)]
214 pub fn ep0_double_buf(&self) -> EP0_DOUBLE_BUF_R {
215 EP0_DOUBLE_BUF_R::new(((self.bits >> 30) & 1) != 0)
216 }
217 #[doc = "Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"]
218 #[inline(always)]
219 pub fn ep0_int_stall(&self) -> EP0_INT_STALL_R {
220 EP0_INT_STALL_R::new(((self.bits >> 31) & 1) != 0)
221 }
222}
223impl W {
224 #[doc = "Bit 0 - Host: Start transaction"]
225 #[inline(always)]
226 #[must_use]
227 pub fn start_trans(&mut self) -> START_TRANS_W<SIE_CTRL_SPEC> {
228 START_TRANS_W::new(self, 0)
229 }
230 #[doc = "Bit 1 - Host: Send Setup packet"]
231 #[inline(always)]
232 #[must_use]
233 pub fn send_setup(&mut self) -> SEND_SETUP_W<SIE_CTRL_SPEC> {
234 SEND_SETUP_W::new(self, 1)
235 }
236 #[doc = "Bit 2 - Host: Send transaction (OUT from host)"]
237 #[inline(always)]
238 #[must_use]
239 pub fn send_data(&mut self) -> SEND_DATA_W<SIE_CTRL_SPEC> {
240 SEND_DATA_W::new(self, 2)
241 }
242 #[doc = "Bit 3 - Host: Receive transaction (IN to host)"]
243 #[inline(always)]
244 #[must_use]
245 pub fn receive_data(&mut self) -> RECEIVE_DATA_W<SIE_CTRL_SPEC> {
246 RECEIVE_DATA_W::new(self, 3)
247 }
248 #[doc = "Bit 4 - Host: Stop transaction"]
249 #[inline(always)]
250 #[must_use]
251 pub fn stop_trans(&mut self) -> STOP_TRANS_W<SIE_CTRL_SPEC> {
252 STOP_TRANS_W::new(self, 4)
253 }
254 #[doc = "Bit 6 - Host: Preable enable for LS device on FS hub"]
255 #[inline(always)]
256 #[must_use]
257 pub fn preamble_en(&mut self) -> PREAMBLE_EN_W<SIE_CTRL_SPEC> {
258 PREAMBLE_EN_W::new(self, 6)
259 }
260 #[doc = "Bit 8 - Host: Delay packet(s) until after SOF"]
261 #[inline(always)]
262 #[must_use]
263 pub fn sof_sync(&mut self) -> SOF_SYNC_W<SIE_CTRL_SPEC> {
264 SOF_SYNC_W::new(self, 8)
265 }
266 #[doc = "Bit 9 - Host: Enable SOF generation (for full speed bus)"]
267 #[inline(always)]
268 #[must_use]
269 pub fn sof_en(&mut self) -> SOF_EN_W<SIE_CTRL_SPEC> {
270 SOF_EN_W::new(self, 9)
271 }
272 #[doc = "Bit 10 - Host: Enable keep alive packet (for low speed bus)"]
273 #[inline(always)]
274 #[must_use]
275 pub fn keep_alive_en(&mut self) -> KEEP_ALIVE_EN_W<SIE_CTRL_SPEC> {
276 KEEP_ALIVE_EN_W::new(self, 10)
277 }
278 #[doc = "Bit 11 - Host: Enable VBUS"]
279 #[inline(always)]
280 #[must_use]
281 pub fn vbus_en(&mut self) -> VBUS_EN_W<SIE_CTRL_SPEC> {
282 VBUS_EN_W::new(self, 11)
283 }
284 #[doc = "Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend."]
285 #[inline(always)]
286 #[must_use]
287 pub fn resume(&mut self) -> RESUME_W<SIE_CTRL_SPEC> {
288 RESUME_W::new(self, 12)
289 }
290 #[doc = "Bit 13 - Host: Reset bus"]
291 #[inline(always)]
292 #[must_use]
293 pub fn reset_bus(&mut self) -> RESET_BUS_W<SIE_CTRL_SPEC> {
294 RESET_BUS_W::new(self, 13)
295 }
296 #[doc = "Bit 15 - Host: Enable pull down resistors"]
297 #[inline(always)]
298 #[must_use]
299 pub fn pulldown_en(&mut self) -> PULLDOWN_EN_W<SIE_CTRL_SPEC> {
300 PULLDOWN_EN_W::new(self, 15)
301 }
302 #[doc = "Bit 16 - Device: Enable pull up resistor"]
303 #[inline(always)]
304 #[must_use]
305 pub fn pullup_en(&mut self) -> PULLUP_EN_W<SIE_CTRL_SPEC> {
306 PULLUP_EN_W::new(self, 16)
307 }
308 #[doc = "Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)"]
309 #[inline(always)]
310 #[must_use]
311 pub fn rpu_opt(&mut self) -> RPU_OPT_W<SIE_CTRL_SPEC> {
312 RPU_OPT_W::new(self, 17)
313 }
314 #[doc = "Bit 18 - Power down bus transceiver"]
315 #[inline(always)]
316 #[must_use]
317 pub fn transceiver_pd(&mut self) -> TRANSCEIVER_PD_W<SIE_CTRL_SPEC> {
318 TRANSCEIVER_PD_W::new(self, 18)
319 }
320 #[doc = "Bit 24 - Direct control of DM"]
321 #[inline(always)]
322 #[must_use]
323 pub fn direct_dm(&mut self) -> DIRECT_DM_W<SIE_CTRL_SPEC> {
324 DIRECT_DM_W::new(self, 24)
325 }
326 #[doc = "Bit 25 - Direct control of DP"]
327 #[inline(always)]
328 #[must_use]
329 pub fn direct_dp(&mut self) -> DIRECT_DP_W<SIE_CTRL_SPEC> {
330 DIRECT_DP_W::new(self, 25)
331 }
332 #[doc = "Bit 26 - Direct bus drive enable"]
333 #[inline(always)]
334 #[must_use]
335 pub fn direct_en(&mut self) -> DIRECT_EN_W<SIE_CTRL_SPEC> {
336 DIRECT_EN_W::new(self, 26)
337 }
338 #[doc = "Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"]
339 #[inline(always)]
340 #[must_use]
341 pub fn ep0_int_nak(&mut self) -> EP0_INT_NAK_W<SIE_CTRL_SPEC> {
342 EP0_INT_NAK_W::new(self, 27)
343 }
344 #[doc = "Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"]
345 #[inline(always)]
346 #[must_use]
347 pub fn ep0_int_2buf(&mut self) -> EP0_INT_2BUF_W<SIE_CTRL_SPEC> {
348 EP0_INT_2BUF_W::new(self, 28)
349 }
350 #[doc = "Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"]
351 #[inline(always)]
352 #[must_use]
353 pub fn ep0_int_1buf(&mut self) -> EP0_INT_1BUF_W<SIE_CTRL_SPEC> {
354 EP0_INT_1BUF_W::new(self, 29)
355 }
356 #[doc = "Bit 30 - Device: EP0 single buffered = 0, double buffered = 1"]
357 #[inline(always)]
358 #[must_use]
359 pub fn ep0_double_buf(&mut self) -> EP0_DOUBLE_BUF_W<SIE_CTRL_SPEC> {
360 EP0_DOUBLE_BUF_W::new(self, 30)
361 }
362 #[doc = "Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"]
363 #[inline(always)]
364 #[must_use]
365 pub fn ep0_int_stall(&mut self) -> EP0_INT_STALL_W<SIE_CTRL_SPEC> {
366 EP0_INT_STALL_W::new(self, 31)
367 }
368 #[doc = r" Writes raw bits to the register."]
369 #[doc = r""]
370 #[doc = r" # Safety"]
371 #[doc = r""]
372 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
373 #[inline(always)]
374 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
375 self.bits = bits;
376 self
377 }
378}
379#[doc = "SIE control register
380
381You can [`read`](crate::generic::Reg::read) this register and get [`sie_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
382pub struct SIE_CTRL_SPEC;
383impl crate::RegisterSpec for SIE_CTRL_SPEC {
384 type Ux = u32;
385}
386#[doc = "`read()` method returns [`sie_ctrl::R`](R) reader structure"]
387impl crate::Readable for SIE_CTRL_SPEC {}
388#[doc = "`write(|w| ..)` method takes [`sie_ctrl::W`](W) writer structure"]
389impl crate::Writable for SIE_CTRL_SPEC {
390 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
391 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
392}
393#[doc = "`reset()` method sets SIE_CTRL to value 0"]
394impl crate::Resettable for SIE_CTRL_SPEC {
395 const RESET_VALUE: u32 = 0;
396}