rp2040_pac/vreg_and_chip_reset/
vreg.rs

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1#[doc = "Register `VREG` reader"]
2pub type R = crate::R<VREG_SPEC>;
3#[doc = "Register `VREG` writer"]
4pub type W = crate::W<VREG_SPEC>;
5#[doc = "Field `EN` reader - enable  
6 0=not enabled, 1=enabled"]
7pub type EN_R = crate::BitReader;
8#[doc = "Field `EN` writer - enable  
9 0=not enabled, 1=enabled"]
10pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `HIZ` reader - high impedance mode select  
12 0=not in high impedance mode, 1=in high impedance mode"]
13pub type HIZ_R = crate::BitReader;
14#[doc = "Field `HIZ` writer - high impedance mode select  
15 0=not in high impedance mode, 1=in high impedance mode"]
16pub type HIZ_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `VSEL` reader - Output voltage select for on-chip voltage regulator."]
18pub type VSEL_R = crate::FieldReader<VSEL_A>;
19#[doc = "Output voltage select for on-chip voltage regulator.  
20
21Value on reset: 11"]
22#[derive(Clone, Copy, Debug, PartialEq, Eq)]
23#[repr(u8)]
24pub enum VSEL_A {
25    #[doc = "5: 0.80V"]
26    VOLTAGE0_80 = 5,
27    #[doc = "6: 0.85V"]
28    VOLTAGE0_85 = 6,
29    #[doc = "7: 0.90V"]
30    VOLTAGE0_90 = 7,
31    #[doc = "8: 0.95V"]
32    VOLTAGE0_95 = 8,
33    #[doc = "9: 1.00V"]
34    VOLTAGE1_00 = 9,
35    #[doc = "10: 1.05V"]
36    VOLTAGE1_05 = 10,
37    #[doc = "11: 1.10V (default)"]
38    VOLTAGE1_10 = 11,
39    #[doc = "12: 1.15V"]
40    VOLTAGE1_15 = 12,
41    #[doc = "13: 1.20V"]
42    VOLTAGE1_20 = 13,
43    #[doc = "14: 1.25V"]
44    VOLTAGE1_25 = 14,
45    #[doc = "15: 1.30V"]
46    VOLTAGE1_30 = 15,
47}
48impl From<VSEL_A> for u8 {
49    #[inline(always)]
50    fn from(variant: VSEL_A) -> Self {
51        variant as _
52    }
53}
54impl crate::FieldSpec for VSEL_A {
55    type Ux = u8;
56}
57impl VSEL_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub const fn variant(&self) -> Option<VSEL_A> {
61        match self.bits {
62            5 => Some(VSEL_A::VOLTAGE0_80),
63            6 => Some(VSEL_A::VOLTAGE0_85),
64            7 => Some(VSEL_A::VOLTAGE0_90),
65            8 => Some(VSEL_A::VOLTAGE0_95),
66            9 => Some(VSEL_A::VOLTAGE1_00),
67            10 => Some(VSEL_A::VOLTAGE1_05),
68            11 => Some(VSEL_A::VOLTAGE1_10),
69            12 => Some(VSEL_A::VOLTAGE1_15),
70            13 => Some(VSEL_A::VOLTAGE1_20),
71            14 => Some(VSEL_A::VOLTAGE1_25),
72            15 => Some(VSEL_A::VOLTAGE1_30),
73            _ => None,
74        }
75    }
76    #[doc = "0.80V"]
77    #[inline(always)]
78    pub fn is_voltage0_80(&self) -> bool {
79        *self == VSEL_A::VOLTAGE0_80
80    }
81    #[doc = "0.85V"]
82    #[inline(always)]
83    pub fn is_voltage0_85(&self) -> bool {
84        *self == VSEL_A::VOLTAGE0_85
85    }
86    #[doc = "0.90V"]
87    #[inline(always)]
88    pub fn is_voltage0_90(&self) -> bool {
89        *self == VSEL_A::VOLTAGE0_90
90    }
91    #[doc = "0.95V"]
92    #[inline(always)]
93    pub fn is_voltage0_95(&self) -> bool {
94        *self == VSEL_A::VOLTAGE0_95
95    }
96    #[doc = "1.00V"]
97    #[inline(always)]
98    pub fn is_voltage1_00(&self) -> bool {
99        *self == VSEL_A::VOLTAGE1_00
100    }
101    #[doc = "1.05V"]
102    #[inline(always)]
103    pub fn is_voltage1_05(&self) -> bool {
104        *self == VSEL_A::VOLTAGE1_05
105    }
106    #[doc = "1.10V (default)"]
107    #[inline(always)]
108    pub fn is_voltage1_10(&self) -> bool {
109        *self == VSEL_A::VOLTAGE1_10
110    }
111    #[doc = "1.15V"]
112    #[inline(always)]
113    pub fn is_voltage1_15(&self) -> bool {
114        *self == VSEL_A::VOLTAGE1_15
115    }
116    #[doc = "1.20V"]
117    #[inline(always)]
118    pub fn is_voltage1_20(&self) -> bool {
119        *self == VSEL_A::VOLTAGE1_20
120    }
121    #[doc = "1.25V"]
122    #[inline(always)]
123    pub fn is_voltage1_25(&self) -> bool {
124        *self == VSEL_A::VOLTAGE1_25
125    }
126    #[doc = "1.30V"]
127    #[inline(always)]
128    pub fn is_voltage1_30(&self) -> bool {
129        *self == VSEL_A::VOLTAGE1_30
130    }
131}
132#[doc = "Field `VSEL` writer - Output voltage select for on-chip voltage regulator."]
133pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, VSEL_A>;
134impl<'a, REG> VSEL_W<'a, REG>
135where
136    REG: crate::Writable + crate::RegisterSpec,
137    REG::Ux: From<u8>,
138{
139    #[doc = "0.80V"]
140    #[inline(always)]
141    pub fn voltage0_80(self) -> &'a mut crate::W<REG> {
142        self.variant(VSEL_A::VOLTAGE0_80)
143    }
144    #[doc = "0.85V"]
145    #[inline(always)]
146    pub fn voltage0_85(self) -> &'a mut crate::W<REG> {
147        self.variant(VSEL_A::VOLTAGE0_85)
148    }
149    #[doc = "0.90V"]
150    #[inline(always)]
151    pub fn voltage0_90(self) -> &'a mut crate::W<REG> {
152        self.variant(VSEL_A::VOLTAGE0_90)
153    }
154    #[doc = "0.95V"]
155    #[inline(always)]
156    pub fn voltage0_95(self) -> &'a mut crate::W<REG> {
157        self.variant(VSEL_A::VOLTAGE0_95)
158    }
159    #[doc = "1.00V"]
160    #[inline(always)]
161    pub fn voltage1_00(self) -> &'a mut crate::W<REG> {
162        self.variant(VSEL_A::VOLTAGE1_00)
163    }
164    #[doc = "1.05V"]
165    #[inline(always)]
166    pub fn voltage1_05(self) -> &'a mut crate::W<REG> {
167        self.variant(VSEL_A::VOLTAGE1_05)
168    }
169    #[doc = "1.10V (default)"]
170    #[inline(always)]
171    pub fn voltage1_10(self) -> &'a mut crate::W<REG> {
172        self.variant(VSEL_A::VOLTAGE1_10)
173    }
174    #[doc = "1.15V"]
175    #[inline(always)]
176    pub fn voltage1_15(self) -> &'a mut crate::W<REG> {
177        self.variant(VSEL_A::VOLTAGE1_15)
178    }
179    #[doc = "1.20V"]
180    #[inline(always)]
181    pub fn voltage1_20(self) -> &'a mut crate::W<REG> {
182        self.variant(VSEL_A::VOLTAGE1_20)
183    }
184    #[doc = "1.25V"]
185    #[inline(always)]
186    pub fn voltage1_25(self) -> &'a mut crate::W<REG> {
187        self.variant(VSEL_A::VOLTAGE1_25)
188    }
189    #[doc = "1.30V"]
190    #[inline(always)]
191    pub fn voltage1_30(self) -> &'a mut crate::W<REG> {
192        self.variant(VSEL_A::VOLTAGE1_30)
193    }
194}
195#[doc = "Field `ROK` reader - regulation status  
196 0=not in regulation, 1=in regulation"]
197pub type ROK_R = crate::BitReader;
198impl R {
199    #[doc = "Bit 0 - enable  
200 0=not enabled, 1=enabled"]
201    #[inline(always)]
202    pub fn en(&self) -> EN_R {
203        EN_R::new((self.bits & 1) != 0)
204    }
205    #[doc = "Bit 1 - high impedance mode select  
206 0=not in high impedance mode, 1=in high impedance mode"]
207    #[inline(always)]
208    pub fn hiz(&self) -> HIZ_R {
209        HIZ_R::new(((self.bits >> 1) & 1) != 0)
210    }
211    #[doc = "Bits 4:7 - Output voltage select for on-chip voltage regulator."]
212    #[inline(always)]
213    pub fn vsel(&self) -> VSEL_R {
214        VSEL_R::new(((self.bits >> 4) & 0x0f) as u8)
215    }
216    #[doc = "Bit 12 - regulation status  
217 0=not in regulation, 1=in regulation"]
218    #[inline(always)]
219    pub fn rok(&self) -> ROK_R {
220        ROK_R::new(((self.bits >> 12) & 1) != 0)
221    }
222}
223impl W {
224    #[doc = "Bit 0 - enable  
225 0=not enabled, 1=enabled"]
226    #[inline(always)]
227    #[must_use]
228    pub fn en(&mut self) -> EN_W<VREG_SPEC> {
229        EN_W::new(self, 0)
230    }
231    #[doc = "Bit 1 - high impedance mode select  
232 0=not in high impedance mode, 1=in high impedance mode"]
233    #[inline(always)]
234    #[must_use]
235    pub fn hiz(&mut self) -> HIZ_W<VREG_SPEC> {
236        HIZ_W::new(self, 1)
237    }
238    #[doc = "Bits 4:7 - Output voltage select for on-chip voltage regulator."]
239    #[inline(always)]
240    #[must_use]
241    pub fn vsel(&mut self) -> VSEL_W<VREG_SPEC> {
242        VSEL_W::new(self, 4)
243    }
244    #[doc = r" Writes raw bits to the register."]
245    #[doc = r""]
246    #[doc = r" # Safety"]
247    #[doc = r""]
248    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
249    #[inline(always)]
250    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
251        self.bits = bits;
252        self
253    }
254}
255#[doc = "Voltage regulator control and status  
256
257You can [`read`](crate::generic::Reg::read) this register and get [`vreg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vreg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
258pub struct VREG_SPEC;
259impl crate::RegisterSpec for VREG_SPEC {
260    type Ux = u32;
261}
262#[doc = "`read()` method returns [`vreg::R`](R) reader structure"]
263impl crate::Readable for VREG_SPEC {}
264#[doc = "`write(|w| ..)` method takes [`vreg::W`](W) writer structure"]
265impl crate::Writable for VREG_SPEC {
266    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
267    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
268}
269#[doc = "`reset()` method sets VREG to value 0xb1"]
270impl crate::Resettable for VREG_SPEC {
271    const RESET_VALUE: u32 = 0xb1;
272}
rp2040_pac/vreg_and_chip_reset/vreg.rs

rp2040_pac/vreg_and_chip_reset/
vreg.rs
