rp2040_pac/clocks/
fc0_delay.rs

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1#[doc = "Register `FC0_DELAY` reader"]
2pub type R = crate::R<FC0_DELAY_SPEC>;
3#[doc = "Register `FC0_DELAY` writer"]
4pub type W = crate::W<FC0_DELAY_SPEC>;
5#[doc = "Field `FC0_DELAY` reader - "]
6pub type FC0_DELAY_R = crate::FieldReader;
7#[doc = "Field `FC0_DELAY` writer - "]
8pub type FC0_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9impl R {
10    #[doc = "Bits 0:2"]
11    #[inline(always)]
12    pub fn fc0_delay(&self) -> FC0_DELAY_R {
13        FC0_DELAY_R::new((self.bits & 7) as u8)
14    }
15}
16impl W {
17    #[doc = "Bits 0:2"]
18    #[inline(always)]
19    #[must_use]
20    pub fn fc0_delay(&mut self) -> FC0_DELAY_W<FC0_DELAY_SPEC> {
21        FC0_DELAY_W::new(self, 0)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "Delays the start of frequency counting to allow the mux to settle  
35 Delay is measured in multiples of the reference clock period  
36
37You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
38pub struct FC0_DELAY_SPEC;
39impl crate::RegisterSpec for FC0_DELAY_SPEC {
40    type Ux = u32;
41}
42#[doc = "`read()` method returns [`fc0_delay::R`](R) reader structure"]
43impl crate::Readable for FC0_DELAY_SPEC {}
44#[doc = "`write(|w| ..)` method takes [`fc0_delay::W`](W) writer structure"]
45impl crate::Writable for FC0_DELAY_SPEC {
46    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
47    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
48}
49#[doc = "`reset()` method sets FC0_DELAY to value 0x01"]
50impl crate::Resettable for FC0_DELAY_SPEC {
51    const RESET_VALUE: u32 = 0x01;
52}
rp2040_pac/clocks/fc0_delay.rs

rp2040_pac/clocks/
fc0_delay.rs
