rp2040_pac/uart0/
uartrsr.rs

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1#[doc = "Register `UARTRSR` reader"]
2pub type R = crate::R<UARTRSR_SPEC>;
3#[doc = "Register `UARTRSR` writer"]
4pub type W = crate::W<UARTRSR_SPEC>;
5#[doc = "Field `FE` reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
6pub type FE_R = crate::BitReader;
7#[doc = "Field `FE` writer - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
8pub type FE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `PE` reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
10pub type PE_R = crate::BitReader;
11#[doc = "Field `PE` writer - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
12pub type PE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `BE` reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
14pub type BE_R = crate::BitReader;
15#[doc = "Field `BE` writer - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
16pub type BE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `OE` reader - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."]
18pub type OE_R = crate::BitReader;
19#[doc = "Field `OE` writer - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."]
20pub type OE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
23    #[inline(always)]
24    pub fn fe(&self) -> FE_R {
25        FE_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
28    #[inline(always)]
29    pub fn pe(&self) -> PE_R {
30        PE_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
33    #[inline(always)]
34    pub fn be(&self) -> BE_R {
35        BE_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."]
38    #[inline(always)]
39    pub fn oe(&self) -> OE_R {
40        OE_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
45    #[inline(always)]
46    #[must_use]
47    pub fn fe(&mut self) -> FE_W<UARTRSR_SPEC> {
48        FE_W::new(self, 0)
49    }
50    #[doc = "Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
51    #[inline(always)]
52    #[must_use]
53    pub fn pe(&mut self) -> PE_W<UARTRSR_SPEC> {
54        PE_W::new(self, 1)
55    }
56    #[doc = "Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
57    #[inline(always)]
58    #[must_use]
59    pub fn be(&mut self) -> BE_W<UARTRSR_SPEC> {
60        BE_W::new(self, 2)
61    }
62    #[doc = "Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."]
63    #[inline(always)]
64    #[must_use]
65    pub fn oe(&mut self) -> OE_W<UARTRSR_SPEC> {
66        OE_W::new(self, 3)
67    }
68    #[doc = r" Writes raw bits to the register."]
69    #[doc = r""]
70    #[doc = r" # Safety"]
71    #[doc = r""]
72    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.bits = bits;
76        self
77    }
78}
79#[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR  
80
81You can [`read`](crate::generic::Reg::read) this register and get [`uartrsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartrsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
82pub struct UARTRSR_SPEC;
83impl crate::RegisterSpec for UARTRSR_SPEC {
84    type Ux = u32;
85}
86#[doc = "`read()` method returns [`uartrsr::R`](R) reader structure"]
87impl crate::Readable for UARTRSR_SPEC {}
88#[doc = "`write(|w| ..)` method takes [`uartrsr::W`](W) writer structure"]
89impl crate::Writable for UARTRSR_SPEC {
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f;
92}
93#[doc = "`reset()` method sets UARTRSR to value 0"]
94impl crate::Resettable for UARTRSR_SPEC {
95    const RESET_VALUE: u32 = 0;
96}
rp2040_pac/uart0/uartrsr.rs

rp2040_pac/uart0/
uartrsr.rs
