rp2040_pac/clocks/
clk_peri_ctrl.rs

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1#[doc = "Register `CLK_PERI_CTRL` reader"]
2pub type R = crate::R<CLK_PERI_CTRL_SPEC>;
3#[doc = "Register `CLK_PERI_CTRL` writer"]
4pub type W = crate::W<CLK_PERI_CTRL_SPEC>;
5#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
6pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
7#[doc = "Selects the auxiliary clock source, will glitch when switching  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum AUXSRC_A {
13    #[doc = "0: `0`"]
14    CLK_SYS = 0,
15    #[doc = "1: `1`"]
16    CLKSRC_PLL_SYS = 1,
17    #[doc = "2: `10`"]
18    CLKSRC_PLL_USB = 2,
19    #[doc = "3: `11`"]
20    ROSC_CLKSRC_PH = 3,
21    #[doc = "4: `100`"]
22    XOSC_CLKSRC = 4,
23    #[doc = "5: `101`"]
24    CLKSRC_GPIN0 = 5,
25    #[doc = "6: `110`"]
26    CLKSRC_GPIN1 = 6,
27}
28impl From<AUXSRC_A> for u8 {
29    #[inline(always)]
30    fn from(variant: AUXSRC_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for AUXSRC_A {
35    type Ux = u8;
36}
37impl AUXSRC_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<AUXSRC_A> {
41        match self.bits {
42            0 => Some(AUXSRC_A::CLK_SYS),
43            1 => Some(AUXSRC_A::CLKSRC_PLL_SYS),
44            2 => Some(AUXSRC_A::CLKSRC_PLL_USB),
45            3 => Some(AUXSRC_A::ROSC_CLKSRC_PH),
46            4 => Some(AUXSRC_A::XOSC_CLKSRC),
47            5 => Some(AUXSRC_A::CLKSRC_GPIN0),
48            6 => Some(AUXSRC_A::CLKSRC_GPIN1),
49            _ => None,
50        }
51    }
52    #[doc = "`0`"]
53    #[inline(always)]
54    pub fn is_clk_sys(&self) -> bool {
55        *self == AUXSRC_A::CLK_SYS
56    }
57    #[doc = "`1`"]
58    #[inline(always)]
59    pub fn is_clksrc_pll_sys(&self) -> bool {
60        *self == AUXSRC_A::CLKSRC_PLL_SYS
61    }
62    #[doc = "`10`"]
63    #[inline(always)]
64    pub fn is_clksrc_pll_usb(&self) -> bool {
65        *self == AUXSRC_A::CLKSRC_PLL_USB
66    }
67    #[doc = "`11`"]
68    #[inline(always)]
69    pub fn is_rosc_clksrc_ph(&self) -> bool {
70        *self == AUXSRC_A::ROSC_CLKSRC_PH
71    }
72    #[doc = "`100`"]
73    #[inline(always)]
74    pub fn is_xosc_clksrc(&self) -> bool {
75        *self == AUXSRC_A::XOSC_CLKSRC
76    }
77    #[doc = "`101`"]
78    #[inline(always)]
79    pub fn is_clksrc_gpin0(&self) -> bool {
80        *self == AUXSRC_A::CLKSRC_GPIN0
81    }
82    #[doc = "`110`"]
83    #[inline(always)]
84    pub fn is_clksrc_gpin1(&self) -> bool {
85        *self == AUXSRC_A::CLKSRC_GPIN1
86    }
87}
88#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"]
89pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>;
90impl<'a, REG> AUXSRC_W<'a, REG>
91where
92    REG: crate::Writable + crate::RegisterSpec,
93    REG::Ux: From<u8>,
94{
95    #[doc = "`0`"]
96    #[inline(always)]
97    pub fn clk_sys(self) -> &'a mut crate::W<REG> {
98        self.variant(AUXSRC_A::CLK_SYS)
99    }
100    #[doc = "`1`"]
101    #[inline(always)]
102    pub fn clksrc_pll_sys(self) -> &'a mut crate::W<REG> {
103        self.variant(AUXSRC_A::CLKSRC_PLL_SYS)
104    }
105    #[doc = "`10`"]
106    #[inline(always)]
107    pub fn clksrc_pll_usb(self) -> &'a mut crate::W<REG> {
108        self.variant(AUXSRC_A::CLKSRC_PLL_USB)
109    }
110    #[doc = "`11`"]
111    #[inline(always)]
112    pub fn rosc_clksrc_ph(self) -> &'a mut crate::W<REG> {
113        self.variant(AUXSRC_A::ROSC_CLKSRC_PH)
114    }
115    #[doc = "`100`"]
116    #[inline(always)]
117    pub fn xosc_clksrc(self) -> &'a mut crate::W<REG> {
118        self.variant(AUXSRC_A::XOSC_CLKSRC)
119    }
120    #[doc = "`101`"]
121    #[inline(always)]
122    pub fn clksrc_gpin0(self) -> &'a mut crate::W<REG> {
123        self.variant(AUXSRC_A::CLKSRC_GPIN0)
124    }
125    #[doc = "`110`"]
126    #[inline(always)]
127    pub fn clksrc_gpin1(self) -> &'a mut crate::W<REG> {
128        self.variant(AUXSRC_A::CLKSRC_GPIN1)
129    }
130}
131#[doc = "Field `KILL` reader - Asynchronously kills the clock generator"]
132pub type KILL_R = crate::BitReader;
133#[doc = "Field `KILL` writer - Asynchronously kills the clock generator"]
134pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>;
135#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"]
136pub type ENABLE_R = crate::BitReader;
137#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"]
138pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
139impl R {
140    #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
141    #[inline(always)]
142    pub fn auxsrc(&self) -> AUXSRC_R {
143        AUXSRC_R::new(((self.bits >> 5) & 7) as u8)
144    }
145    #[doc = "Bit 10 - Asynchronously kills the clock generator"]
146    #[inline(always)]
147    pub fn kill(&self) -> KILL_R {
148        KILL_R::new(((self.bits >> 10) & 1) != 0)
149    }
150    #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
151    #[inline(always)]
152    pub fn enable(&self) -> ENABLE_R {
153        ENABLE_R::new(((self.bits >> 11) & 1) != 0)
154    }
155}
156impl W {
157    #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
158    #[inline(always)]
159    #[must_use]
160    pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_PERI_CTRL_SPEC> {
161        AUXSRC_W::new(self, 5)
162    }
163    #[doc = "Bit 10 - Asynchronously kills the clock generator"]
164    #[inline(always)]
165    #[must_use]
166    pub fn kill(&mut self) -> KILL_W<CLK_PERI_CTRL_SPEC> {
167        KILL_W::new(self, 10)
168    }
169    #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
170    #[inline(always)]
171    #[must_use]
172    pub fn enable(&mut self) -> ENABLE_W<CLK_PERI_CTRL_SPEC> {
173        ENABLE_W::new(self, 11)
174    }
175    #[doc = r" Writes raw bits to the register."]
176    #[doc = r""]
177    #[doc = r" # Safety"]
178    #[doc = r""]
179    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
180    #[inline(always)]
181    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
182        self.bits = bits;
183        self
184    }
185}
186#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
187
188You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
189pub struct CLK_PERI_CTRL_SPEC;
190impl crate::RegisterSpec for CLK_PERI_CTRL_SPEC {
191    type Ux = u32;
192}
193#[doc = "`read()` method returns [`clk_peri_ctrl::R`](R) reader structure"]
194impl crate::Readable for CLK_PERI_CTRL_SPEC {}
195#[doc = "`write(|w| ..)` method takes [`clk_peri_ctrl::W`](W) writer structure"]
196impl crate::Writable for CLK_PERI_CTRL_SPEC {
197    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
198    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
199}
200#[doc = "`reset()` method sets CLK_PERI_CTRL to value 0"]
201impl crate::Resettable for CLK_PERI_CTRL_SPEC {
202    const RESET_VALUE: u32 = 0;
203}
rp2040_pac/clocks/clk_peri_ctrl.rs

rp2040_pac/clocks/
clk_peri_ctrl.rs
