imxrt_ral/blocks/imxrt1011/
snvs.rs

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1#[doc = "SNVS"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "SNVS_HP Lock Register"]
5    pub HPLR: crate::RWRegister<u32>,
6    #[doc = "SNVS_HP Command Register"]
7    pub HPCOMR: crate::RWRegister<u32>,
8    #[doc = "SNVS_HP Control Register"]
9    pub HPCR: crate::RWRegister<u32>,
10    #[doc = "SNVS_HP Security Interrupt Control Register"]
11    pub HPSICR: crate::RWRegister<u32>,
12    #[doc = "SNVS_HP Security Violation Control Register"]
13    pub HPSVCR: crate::RWRegister<u32>,
14    #[doc = "SNVS_HP Status Register"]
15    pub HPSR: crate::RWRegister<u32>,
16    #[doc = "SNVS_HP Security Violation Status Register"]
17    pub HPSVSR: crate::RWRegister<u32>,
18    #[doc = "SNVS_HP High Assurance Counter IV Register"]
19    pub HPHACIVR: crate::RWRegister<u32>,
20    #[doc = "SNVS_HP High Assurance Counter Register"]
21    pub HPHACR: crate::RORegister<u32>,
22    #[doc = "SNVS_HP Real Time Counter MSB Register"]
23    pub HPRTCMR: crate::RWRegister<u32>,
24    #[doc = "SNVS_HP Real Time Counter LSB Register"]
25    pub HPRTCLR: crate::RWRegister<u32>,
26    #[doc = "SNVS_HP Time Alarm MSB Register"]
27    pub HPTAMR: crate::RWRegister<u32>,
28    #[doc = "SNVS_HP Time Alarm LSB Register"]
29    pub HPTALR: crate::RWRegister<u32>,
30    #[doc = "SNVS_LP Lock Register"]
31    pub LPLR: crate::RWRegister<u32>,
32    #[doc = "SNVS_LP Control Register"]
33    pub LPCR: crate::RWRegister<u32>,
34    #[doc = "SNVS_LP Master Key Control Register"]
35    pub LPMKCR: crate::RWRegister<u32>,
36    #[doc = "SNVS_LP Security Violation Control Register"]
37    pub LPSVCR: crate::RWRegister<u32>,
38    _reserved0: [u8; 0x04],
39    #[doc = "SNVS_LP Tamper Detectors Configuration Register"]
40    pub LPTDCR: crate::RWRegister<u32>,
41    #[doc = "SNVS_LP Status Register"]
42    pub LPSR: crate::RWRegister<u32>,
43    #[doc = "SNVS_LP Secure Real Time Counter MSB Register"]
44    pub LPSRTCMR: crate::RWRegister<u32>,
45    #[doc = "SNVS_LP Secure Real Time Counter LSB Register"]
46    pub LPSRTCLR: crate::RWRegister<u32>,
47    #[doc = "SNVS_LP Time Alarm Register"]
48    pub LPTAR: crate::RWRegister<u32>,
49    #[doc = "SNVS_LP Secure Monotonic Counter MSB Register"]
50    pub LPSMCMR: crate::RORegister<u32>,
51    #[doc = "SNVS_LP Secure Monotonic Counter LSB Register"]
52    pub LPSMCLR: crate::RORegister<u32>,
53    #[doc = "SNVS_LP Power Glitch Detector Register"]
54    pub LPPGDR: crate::RWRegister<u32>,
55    #[doc = "SNVS_LP General Purpose Register 0 (legacy alias)"]
56    pub LPGPR0_LEGACY_ALIAS: crate::RWRegister<u32>,
57    #[doc = "SNVS_LP Zeroizable Master Key Register"]
58    pub LPZMKR: [crate::RWRegister<u32>; 8usize],
59    _reserved1: [u8; 0x04],
60    #[doc = "SNVS_LP General Purpose Registers 0 .. 3"]
61    pub LPGPR_ALIAS: [crate::RWRegister<u32>; 4usize],
62    _reserved2: [u8; 0x60],
63    #[doc = "SNVS_LP General Purpose Registers 0 .. 3"]
64    pub LPGPR: [crate::RWRegister<u32>; 4usize],
65    _reserved3: [u8; 0x0ae8],
66    #[doc = "SNVS_HP Version ID Register 1"]
67    pub HPVIDR1: crate::RORegister<u32>,
68    #[doc = "SNVS_HP Version ID Register 2"]
69    pub HPVIDR2: crate::RORegister<u32>,
70}
71#[doc = "SNVS_HP Lock Register"]
72pub mod HPLR {
73    #[doc = "Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR"]
74    pub mod ZMK_WSL {
75        pub const offset: u32 = 0;
76        pub const mask: u32 = 0x01 << offset;
77        pub mod R {}
78        pub mod W {}
79        pub mod RW {
80            #[doc = "Write access is allowed"]
81            pub const ZMK_WSL_0: u32 = 0;
82            #[doc = "Write access is not allowed"]
83            pub const ZMK_WSL_1: u32 = 0x01;
84        }
85    }
86    #[doc = "Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR"]
87    pub mod ZMK_RSL {
88        pub const offset: u32 = 1;
89        pub const mask: u32 = 0x01 << offset;
90        pub mod R {}
91        pub mod W {}
92        pub mod RW {
93            #[doc = "Read access is allowed (only in software Programming mode)"]
94            pub const ZMK_RSL_0: u32 = 0;
95            #[doc = "Read access is not allowed"]
96            pub const ZMK_RSL_1: u32 = 0x01;
97        }
98    }
99    #[doc = "Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits"]
100    pub mod SRTC_SL {
101        pub const offset: u32 = 2;
102        pub const mask: u32 = 0x01 << offset;
103        pub mod R {}
104        pub mod W {}
105        pub mod RW {
106            #[doc = "Write access is allowed"]
107            pub const SRTC_SL_0: u32 = 0;
108            #[doc = "Write access is not allowed"]
109            pub const SRTC_SL_1: u32 = 0x01;
110        }
111    }
112    #[doc = "LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)"]
113    pub mod LPCALB_SL {
114        pub const offset: u32 = 3;
115        pub const mask: u32 = 0x01 << offset;
116        pub mod R {}
117        pub mod W {}
118        pub mod RW {
119            #[doc = "Write access is allowed"]
120            pub const LPCALB_SL_0: u32 = 0;
121            #[doc = "Write access is not allowed"]
122            pub const LPCALB_SL_1: u32 = 0x01;
123        }
124    }
125    #[doc = "Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit"]
126    pub mod MC_SL {
127        pub const offset: u32 = 4;
128        pub const mask: u32 = 0x01 << offset;
129        pub mod R {}
130        pub mod W {}
131        pub mod RW {
132            #[doc = "Write access (increment) is allowed"]
133            pub const MC_SL_0: u32 = 0;
134            #[doc = "Write access (increment) is not allowed"]
135            pub const MC_SL_1: u32 = 0x01;
136        }
137    }
138    #[doc = "General Purpose Register Soft Lock When set, prevents any writes to the GPR"]
139    pub mod GPR_SL {
140        pub const offset: u32 = 5;
141        pub const mask: u32 = 0x01 << offset;
142        pub mod R {}
143        pub mod W {}
144        pub mod RW {
145            #[doc = "Write access is allowed"]
146            pub const GPR_SL_0: u32 = 0;
147            #[doc = "Write access is not allowed"]
148            pub const GPR_SL_1: u32 = 0x01;
149        }
150    }
151    #[doc = "LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR"]
152    pub mod LPSVCR_SL {
153        pub const offset: u32 = 6;
154        pub const mask: u32 = 0x01 << offset;
155        pub mod R {}
156        pub mod W {}
157        pub mod RW {
158            #[doc = "Write access is allowed"]
159            pub const LPSVCR_SL_0: u32 = 0;
160            #[doc = "Write access is not allowed"]
161            pub const LPSVCR_SL_1: u32 = 0x01;
162        }
163    }
164    #[doc = "LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR"]
165    pub mod LPTDCR_SL {
166        pub const offset: u32 = 8;
167        pub const mask: u32 = 0x01 << offset;
168        pub mod R {}
169        pub mod W {}
170        pub mod RW {
171            #[doc = "Write access is allowed"]
172            pub const LPTDCR_SL_0: u32 = 0;
173            #[doc = "Write access is not allowed"]
174            pub const LPTDCR_SL_1: u32 = 0x01;
175        }
176    }
177    #[doc = "Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR"]
178    pub mod MKS_SL {
179        pub const offset: u32 = 9;
180        pub const mask: u32 = 0x01 << offset;
181        pub mod R {}
182        pub mod W {}
183        pub mod RW {
184            #[doc = "Write access is allowed"]
185            pub const MKS_SL_0: u32 = 0;
186            #[doc = "Write access is not allowed"]
187            pub const MKS_SL_1: u32 = 0x01;
188        }
189    }
190    #[doc = "HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR"]
191    pub mod HPSVCR_L {
192        pub const offset: u32 = 16;
193        pub const mask: u32 = 0x01 << offset;
194        pub mod R {}
195        pub mod W {}
196        pub mod RW {
197            #[doc = "Write access is allowed"]
198            pub const HPSVCR_L_0: u32 = 0;
199            #[doc = "Write access is not allowed"]
200            pub const HPSVCR_L_1: u32 = 0x01;
201        }
202    }
203    #[doc = "HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR"]
204    pub mod HPSICR_L {
205        pub const offset: u32 = 17;
206        pub const mask: u32 = 0x01 << offset;
207        pub mod R {}
208        pub mod W {}
209        pub mod RW {
210            #[doc = "Write access is allowed"]
211            pub const HPSICR_L_0: u32 = 0;
212            #[doc = "Write access is not allowed"]
213            pub const HPSICR_L_1: u32 = 0x01;
214        }
215    }
216    #[doc = "High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR"]
217    pub mod HAC_L {
218        pub const offset: u32 = 18;
219        pub const mask: u32 = 0x01 << offset;
220        pub mod R {}
221        pub mod W {}
222        pub mod RW {
223            #[doc = "Write access is allowed"]
224            pub const HAC_L_0: u32 = 0;
225            #[doc = "Write access is not allowed"]
226            pub const HAC_L_1: u32 = 0x01;
227        }
228    }
229}
230#[doc = "SNVS_HP Command Register"]
231pub mod HPCOMR {
232    #[doc = "SSM State Transition Transition state of the system security monitor"]
233    pub mod SSM_ST {
234        pub const offset: u32 = 0;
235        pub const mask: u32 = 0x01 << offset;
236        pub mod R {}
237        pub mod W {}
238        pub mod RW {}
239    }
240    #[doc = "SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state"]
241    pub mod SSM_ST_DIS {
242        pub const offset: u32 = 1;
243        pub const mask: u32 = 0x01 << offset;
244        pub mod R {}
245        pub mod W {}
246        pub mod RW {
247            #[doc = "Secure to Trusted State transition is enabled"]
248            pub const SSM_ST_DIS_0: u32 = 0;
249            #[doc = "Secure to Trusted State transition is disabled"]
250            pub const SSM_ST_DIS_1: u32 = 0x01;
251        }
252    }
253    #[doc = "SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state"]
254    pub mod SSM_SFNS_DIS {
255        pub const offset: u32 = 2;
256        pub const mask: u32 = 0x01 << offset;
257        pub mod R {}
258        pub mod W {}
259        pub mod RW {
260            #[doc = "Soft Fail to Non-Secure State transition is enabled"]
261            pub const SSM_SFNS_DIS_0: u32 = 0;
262            #[doc = "Soft Fail to Non-Secure State transition is disabled"]
263            pub const SSM_SFNS_DIS_1: u32 = 0x01;
264        }
265    }
266    #[doc = "LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set"]
267    pub mod LP_SWR {
268        pub const offset: u32 = 4;
269        pub const mask: u32 = 0x01 << offset;
270        pub mod R {}
271        pub mod W {}
272        pub mod RW {
273            #[doc = "No Action"]
274            pub const LP_SWR_0: u32 = 0;
275            #[doc = "Reset LP section"]
276            pub const LP_SWR_1: u32 = 0x01;
277        }
278    }
279    #[doc = "LP Software Reset Disable When set, disables the LP software reset"]
280    pub mod LP_SWR_DIS {
281        pub const offset: u32 = 5;
282        pub const mask: u32 = 0x01 << offset;
283        pub mod R {}
284        pub mod W {}
285        pub mod RW {
286            #[doc = "LP software reset is enabled"]
287            pub const LP_SWR_DIS_0: u32 = 0;
288            #[doc = "LP software reset is disabled"]
289            pub const LP_SWR_DIS_1: u32 = 0x01;
290        }
291    }
292    #[doc = "Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation"]
293    pub mod SW_SV {
294        pub const offset: u32 = 8;
295        pub const mask: u32 = 0x01 << offset;
296        pub mod R {}
297        pub mod W {}
298        pub mod RW {}
299    }
300    #[doc = "Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation"]
301    pub mod SW_FSV {
302        pub const offset: u32 = 9;
303        pub const mask: u32 = 0x01 << offset;
304        pub mod R {}
305        pub mod W {}
306        pub mod RW {}
307    }
308    #[doc = "LP Software Security Violation When set, SNVS_LP treats this bit as a security violation"]
309    pub mod SW_LPSV {
310        pub const offset: u32 = 10;
311        pub const mask: u32 = 0x01 << offset;
312        pub mod R {}
313        pub mod W {}
314        pub mod RW {}
315    }
316    #[doc = "Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism"]
317    pub mod PROG_ZMK {
318        pub const offset: u32 = 12;
319        pub const mask: u32 = 0x01 << offset;
320        pub mod R {}
321        pub mod W {}
322        pub mod RW {
323            #[doc = "No Action"]
324            pub const PROG_ZMK_0: u32 = 0;
325            #[doc = "Activate hardware key programming mechanism"]
326            pub const PROG_ZMK_1: u32 = 0x01;
327        }
328    }
329    #[doc = "Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default"]
330    pub mod MKS_EN {
331        pub const offset: u32 = 13;
332        pub const mask: u32 = 0x01 << offset;
333        pub mod R {}
334        pub mod W {}
335        pub mod RW {
336            #[doc = "OTP master key is selected as an SNVS master key"]
337            pub const MKS_EN_0: u32 = 0;
338            #[doc = "SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR"]
339            pub const MKS_EN_1: u32 = 0x01;
340        }
341    }
342    #[doc = "High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state"]
343    pub mod HAC_EN {
344        pub const offset: u32 = 16;
345        pub const mask: u32 = 0x01 << offset;
346        pub mod R {}
347        pub mod W {}
348        pub mod RW {
349            #[doc = "High Assurance Counter is disabled"]
350            pub const HAC_EN_0: u32 = 0;
351            #[doc = "High Assurance Counter is enabled"]
352            pub const HAC_EN_1: u32 = 0x01;
353        }
354    }
355    #[doc = "High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register"]
356    pub mod HAC_LOAD {
357        pub const offset: u32 = 17;
358        pub const mask: u32 = 0x01 << offset;
359        pub mod R {}
360        pub mod W {}
361        pub mod RW {
362            #[doc = "No Action"]
363            pub const HAC_LOAD_0: u32 = 0;
364            #[doc = "Load the HAC"]
365            pub const HAC_LOAD_1: u32 = 0x01;
366        }
367    }
368    #[doc = "High Assurance Counter Clear When set, it clears the High Assurance Counter Register"]
369    pub mod HAC_CLEAR {
370        pub const offset: u32 = 18;
371        pub const mask: u32 = 0x01 << offset;
372        pub mod R {}
373        pub mod W {}
374        pub mod RW {
375            #[doc = "No Action"]
376            pub const HAC_CLEAR_0: u32 = 0;
377            #[doc = "Clear the HAC"]
378            pub const HAC_CLEAR_1: u32 = 0x01;
379        }
380    }
381    #[doc = "High Assurance Counter Stop This bit can be set only when SSM is in soft fail state"]
382    pub mod HAC_STOP {
383        pub const offset: u32 = 19;
384        pub const mask: u32 = 0x01 << offset;
385        pub mod R {}
386        pub mod W {}
387        pub mod RW {}
388    }
389    #[doc = "Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only"]
390    pub mod NPSWA_EN {
391        pub const offset: u32 = 31;
392        pub const mask: u32 = 0x01 << offset;
393        pub mod R {}
394        pub mod W {}
395        pub mod RW {}
396    }
397}
398#[doc = "SNVS_HP Control Register"]
399pub mod HPCR {
400    #[doc = "HP Real Time Counter Enable"]
401    pub mod RTC_EN {
402        pub const offset: u32 = 0;
403        pub const mask: u32 = 0x01 << offset;
404        pub mod R {}
405        pub mod W {}
406        pub mod RW {
407            #[doc = "RTC is disabled"]
408            pub const RTC_EN_0: u32 = 0;
409            #[doc = "RTC is enabled"]
410            pub const RTC_EN_1: u32 = 0x01;
411        }
412    }
413    #[doc = "HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter"]
414    pub mod HPTA_EN {
415        pub const offset: u32 = 1;
416        pub const mask: u32 = 0x01 << offset;
417        pub mod R {}
418        pub mod W {}
419        pub mod RW {
420            #[doc = "HP Time Alarm Interrupt is disabled"]
421            pub const HPTA_EN_0: u32 = 0;
422            #[doc = "HP Time Alarm Interrupt is enabled"]
423            pub const HPTA_EN_1: u32 = 0x01;
424        }
425    }
426    #[doc = "Disable periodic interrupt in the functional interrupt"]
427    pub mod DIS_PI {
428        pub const offset: u32 = 2;
429        pub const mask: u32 = 0x01 << offset;
430        pub mod R {}
431        pub mod W {}
432        pub mod RW {
433            #[doc = "Periodic interrupt will trigger a functional interrupt"]
434            pub const DIS_PI_0: u32 = 0;
435            #[doc = "Disable periodic interrupt in the function interrupt"]
436            pub const DIS_PI_1: u32 = 0x01;
437        }
438    }
439    #[doc = "HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled"]
440    pub mod PI_EN {
441        pub const offset: u32 = 3;
442        pub const mask: u32 = 0x01 << offset;
443        pub mod R {}
444        pub mod W {}
445        pub mod RW {
446            #[doc = "HP Periodic Interrupt is disabled"]
447            pub const PI_EN_0: u32 = 0;
448            #[doc = "HP Periodic Interrupt is enabled"]
449            pub const PI_EN_1: u32 = 0x01;
450        }
451    }
452    #[doc = "Periodic Interrupt Frequency Defines frequency of the periodic interrupt"]
453    pub mod PI_FREQ {
454        pub const offset: u32 = 4;
455        pub const mask: u32 = 0x0f << offset;
456        pub mod R {}
457        pub mod W {}
458        pub mod RW {
459            #[doc = "- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt"]
460            pub const PI_FREQ_0: u32 = 0;
461            #[doc = "- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt"]
462            pub const PI_FREQ_1: u32 = 0x01;
463            #[doc = "- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt"]
464            pub const PI_FREQ_2: u32 = 0x02;
465            #[doc = "- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt"]
466            pub const PI_FREQ_3: u32 = 0x03;
467            #[doc = "- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt"]
468            pub const PI_FREQ_4: u32 = 0x04;
469            #[doc = "- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt"]
470            pub const PI_FREQ_5: u32 = 0x05;
471            #[doc = "- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt"]
472            pub const PI_FREQ_6: u32 = 0x06;
473            #[doc = "- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt"]
474            pub const PI_FREQ_7: u32 = 0x07;
475            #[doc = "- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt"]
476            pub const PI_FREQ_8: u32 = 0x08;
477            #[doc = "- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt"]
478            pub const PI_FREQ_9: u32 = 0x09;
479            #[doc = "- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt"]
480            pub const PI_FREQ_10: u32 = 0x0a;
481            #[doc = "- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt"]
482            pub const PI_FREQ_11: u32 = 0x0b;
483            #[doc = "- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt"]
484            pub const PI_FREQ_12: u32 = 0x0c;
485            #[doc = "- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt"]
486            pub const PI_FREQ_13: u32 = 0x0d;
487            #[doc = "- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt"]
488            pub const PI_FREQ_14: u32 = 0x0e;
489            #[doc = "- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt"]
490            pub const PI_FREQ_15: u32 = 0x0f;
491        }
492    }
493    #[doc = "HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled."]
494    pub mod HPCALB_EN {
495        pub const offset: u32 = 8;
496        pub const mask: u32 = 0x01 << offset;
497        pub mod R {}
498        pub mod W {}
499        pub mod RW {
500            #[doc = "HP Timer calibration disabled"]
501            pub const HPCALB_EN_0: u32 = 0;
502            #[doc = "HP Timer calibration enabled"]
503            pub const HPCALB_EN_1: u32 = 0x01;
504        }
505    }
506    #[doc = "HP Calibration Value Defines signed calibration value for the HP Real Time Counter"]
507    pub mod HPCALB_VAL {
508        pub const offset: u32 = 10;
509        pub const mask: u32 = 0x1f << offset;
510        pub mod R {}
511        pub mod W {}
512        pub mod RW {
513            #[doc = "+0 counts per each 32768 ticks of the counter"]
514            pub const HPCALB_VAL_0: u32 = 0;
515            #[doc = "+1 counts per each 32768 ticks of the counter"]
516            pub const HPCALB_VAL_1: u32 = 0x01;
517            #[doc = "+2 counts per each 32768 ticks of the counter"]
518            pub const HPCALB_VAL_2: u32 = 0x02;
519            #[doc = "+15 counts per each 32768 ticks of the counter"]
520            pub const HPCALB_VAL_15: u32 = 0x0f;
521            #[doc = "-16 counts per each 32768 ticks of the counter"]
522            pub const HPCALB_VAL_16: u32 = 0x10;
523            #[doc = "-15 counts per each 32768 ticks of the counter"]
524            pub const HPCALB_VAL_17: u32 = 0x11;
525            #[doc = "-2 counts per each 32768 ticks of the counter"]
526            pub const HPCALB_VAL_30: u32 = 0x1e;
527            #[doc = "-1 counts per each 32768 ticks of the counter"]
528            pub const HPCALB_VAL_31: u32 = 0x1f;
529        }
530    }
531    #[doc = "HP Time Synchronize"]
532    pub mod HP_TS {
533        pub const offset: u32 = 16;
534        pub const mask: u32 = 0x01 << offset;
535        pub mod R {}
536        pub mod W {}
537        pub mod RW {
538            #[doc = "No Action"]
539            pub const HP_TS_0: u32 = 0;
540            #[doc = "Synchronize the HP Time Counter to the LP Time Counter"]
541            pub const HP_TS_1: u32 = 0x01;
542        }
543    }
544    #[doc = "Button Configuration"]
545    pub mod BTN_CONFIG {
546        pub const offset: u32 = 24;
547        pub const mask: u32 = 0x07 << offset;
548        pub mod R {}
549        pub mod W {}
550        pub mod RW {}
551    }
552    #[doc = "Button interrupt mask"]
553    pub mod BTN_MASK {
554        pub const offset: u32 = 27;
555        pub const mask: u32 = 0x01 << offset;
556        pub mod R {}
557        pub mod W {}
558        pub mod RW {}
559    }
560}
561#[doc = "SNVS_HP Security Interrupt Control Register"]
562pub mod HPSICR {
563    #[doc = "Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation"]
564    pub mod SV0_EN {
565        pub const offset: u32 = 0;
566        pub const mask: u32 = 0x01 << offset;
567        pub mod R {}
568        pub mod W {}
569        pub mod RW {
570            #[doc = "Security Violation 0 Interrupt is Disabled"]
571            pub const SV0_EN_0: u32 = 0;
572            #[doc = "Security Violation 0 Interrupt is Enabled"]
573            pub const SV0_EN_1: u32 = 0x01;
574        }
575    }
576    #[doc = "Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation"]
577    pub mod SV1_EN {
578        pub const offset: u32 = 1;
579        pub const mask: u32 = 0x01 << offset;
580        pub mod R {}
581        pub mod W {}
582        pub mod RW {
583            #[doc = "Security Violation 1 Interrupt is Disabled"]
584            pub const SV1_EN_0: u32 = 0;
585            #[doc = "Security Violation 1 Interrupt is Enabled"]
586            pub const SV1_EN_1: u32 = 0x01;
587        }
588    }
589    #[doc = "Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation"]
590    pub mod SV2_EN {
591        pub const offset: u32 = 2;
592        pub const mask: u32 = 0x01 << offset;
593        pub mod R {}
594        pub mod W {}
595        pub mod RW {
596            #[doc = "Security Violation 2 Interrupt is Disabled"]
597            pub const SV2_EN_0: u32 = 0;
598            #[doc = "Security Violation 2 Interrupt is Enabled"]
599            pub const SV2_EN_1: u32 = 0x01;
600        }
601    }
602    #[doc = "Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation"]
603    pub mod SV3_EN {
604        pub const offset: u32 = 3;
605        pub const mask: u32 = 0x01 << offset;
606        pub mod R {}
607        pub mod W {}
608        pub mod RW {
609            #[doc = "Security Violation 3 Interrupt is Disabled"]
610            pub const SV3_EN_0: u32 = 0;
611            #[doc = "Security Violation 3 Interrupt is Enabled"]
612            pub const SV3_EN_1: u32 = 0x01;
613        }
614    }
615    #[doc = "Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation"]
616    pub mod SV4_EN {
617        pub const offset: u32 = 4;
618        pub const mask: u32 = 0x01 << offset;
619        pub mod R {}
620        pub mod W {}
621        pub mod RW {
622            #[doc = "Security Violation 4 Interrupt is Disabled"]
623            pub const SV4_EN_0: u32 = 0;
624            #[doc = "Security Violation 4 Interrupt is Enabled"]
625            pub const SV4_EN_1: u32 = 0x01;
626        }
627    }
628    #[doc = "Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation"]
629    pub mod SV5_EN {
630        pub const offset: u32 = 5;
631        pub const mask: u32 = 0x01 << offset;
632        pub mod R {}
633        pub mod W {}
634        pub mod RW {
635            #[doc = "Security Violation 5 Interrupt is Disabled"]
636            pub const SV5_EN_0: u32 = 0;
637            #[doc = "Security Violation 5 Interrupt is Enabled"]
638            pub const SV5_EN_1: u32 = 0x01;
639        }
640    }
641    #[doc = "LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section"]
642    pub mod LPSVI_EN {
643        pub const offset: u32 = 31;
644        pub const mask: u32 = 0x01 << offset;
645        pub mod R {}
646        pub mod W {}
647        pub mod RW {
648            #[doc = "LP Security Violation Interrupt is Disabled"]
649            pub const LPSVI_EN_0: u32 = 0;
650            #[doc = "LP Security Violation Interrupt is Enabled"]
651            pub const LPSVI_EN_1: u32 = 0x01;
652        }
653    }
654}
655#[doc = "SNVS_HP Security Violation Control Register"]
656pub mod HPSVCR {
657    #[doc = "Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input"]
658    pub mod SV0_CFG {
659        pub const offset: u32 = 0;
660        pub const mask: u32 = 0x01 << offset;
661        pub mod R {}
662        pub mod W {}
663        pub mod RW {
664            #[doc = "Security Violation 0 is a non-fatal violation"]
665            pub const SV0_CFG_0: u32 = 0;
666            #[doc = "Security Violation 0 is a fatal violation"]
667            pub const SV0_CFG_1: u32 = 0x01;
668        }
669    }
670    #[doc = "Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input"]
671    pub mod SV1_CFG {
672        pub const offset: u32 = 1;
673        pub const mask: u32 = 0x01 << offset;
674        pub mod R {}
675        pub mod W {}
676        pub mod RW {
677            #[doc = "Security Violation 1 is a non-fatal violation"]
678            pub const SV1_CFG_0: u32 = 0;
679            #[doc = "Security Violation 1 is a fatal violation"]
680            pub const SV1_CFG_1: u32 = 0x01;
681        }
682    }
683    #[doc = "Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input"]
684    pub mod SV2_CFG {
685        pub const offset: u32 = 2;
686        pub const mask: u32 = 0x01 << offset;
687        pub mod R {}
688        pub mod W {}
689        pub mod RW {
690            #[doc = "Security Violation 2 is a non-fatal violation"]
691            pub const SV2_CFG_0: u32 = 0;
692            #[doc = "Security Violation 2 is a fatal violation"]
693            pub const SV2_CFG_1: u32 = 0x01;
694        }
695    }
696    #[doc = "Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input"]
697    pub mod SV3_CFG {
698        pub const offset: u32 = 3;
699        pub const mask: u32 = 0x01 << offset;
700        pub mod R {}
701        pub mod W {}
702        pub mod RW {
703            #[doc = "Security Violation 3 is a non-fatal violation"]
704            pub const SV3_CFG_0: u32 = 0;
705            #[doc = "Security Violation 3 is a fatal violation"]
706            pub const SV3_CFG_1: u32 = 0x01;
707        }
708    }
709    #[doc = "Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input"]
710    pub mod SV4_CFG {
711        pub const offset: u32 = 4;
712        pub const mask: u32 = 0x01 << offset;
713        pub mod R {}
714        pub mod W {}
715        pub mod RW {
716            #[doc = "Security Violation 4 is a non-fatal violation"]
717            pub const SV4_CFG_0: u32 = 0;
718            #[doc = "Security Violation 4 is a fatal violation"]
719            pub const SV4_CFG_1: u32 = 0x01;
720        }
721    }
722    #[doc = "Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input"]
723    pub mod SV5_CFG {
724        pub const offset: u32 = 5;
725        pub const mask: u32 = 0x03 << offset;
726        pub mod R {}
727        pub mod W {}
728        pub mod RW {
729            #[doc = "Security Violation 5 is disabled"]
730            pub const SV5_CFG_0: u32 = 0;
731            #[doc = "Security Violation 5 is a non-fatal violation"]
732            pub const SV5_CFG_1: u32 = 0x01;
733            #[doc = "Security Violation 5 is a fatal violation"]
734            pub const SV5_CFG_2: u32 = 0x02;
735        }
736    }
737    #[doc = "LP Security Violation Configuration This field configures the LP security violation source."]
738    pub mod LPSV_CFG {
739        pub const offset: u32 = 30;
740        pub const mask: u32 = 0x03 << offset;
741        pub mod R {}
742        pub mod W {}
743        pub mod RW {
744            #[doc = "LP security violation is disabled"]
745            pub const LPSV_CFG_0: u32 = 0;
746            #[doc = "LP security violation is a non-fatal violation"]
747            pub const LPSV_CFG_1: u32 = 0x01;
748            #[doc = "LP security violation is a fatal violation"]
749            pub const LPSV_CFG_2: u32 = 0x02;
750        }
751    }
752}
753#[doc = "SNVS_HP Status Register"]
754pub mod HPSR {
755    #[doc = "HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared."]
756    pub mod HPTA {
757        pub const offset: u32 = 0;
758        pub const mask: u32 = 0x01 << offset;
759        pub mod R {}
760        pub mod W {}
761        pub mod RW {
762            #[doc = "No time alarm interrupt occurred."]
763            pub const HPTA_0: u32 = 0;
764            #[doc = "A time alarm interrupt occurred."]
765            pub const HPTA_1: u32 = 0x01;
766        }
767    }
768    #[doc = "Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared."]
769    pub mod PI {
770        pub const offset: u32 = 1;
771        pub const mask: u32 = 0x01 << offset;
772        pub mod R {}
773        pub mod W {}
774        pub mod RW {
775            #[doc = "No periodic interrupt occurred."]
776            pub const PI_0: u32 = 0;
777            #[doc = "A periodic interrupt occurred."]
778            pub const PI_1: u32 = 0x01;
779        }
780    }
781    #[doc = "Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS"]
782    pub mod LPDIS {
783        pub const offset: u32 = 4;
784        pub const mask: u32 = 0x01 << offset;
785        pub mod R {}
786        pub mod W {}
787        pub mod RW {}
788    }
789    #[doc = "Button Value of the BTN input"]
790    pub mod BTN {
791        pub const offset: u32 = 6;
792        pub const mask: u32 = 0x01 << offset;
793        pub mod R {}
794        pub mod W {}
795        pub mod RW {}
796    }
797    #[doc = "Button Interrupt Signal ipi_snvs_btn_int_b was asserted."]
798    pub mod BI {
799        pub const offset: u32 = 7;
800        pub const mask: u32 = 0x01 << offset;
801        pub mod R {}
802        pub mod W {}
803        pub mod RW {}
804    }
805    #[doc = "System Security Monitor State This field contains the encoded state of the SSM's state machine"]
806    pub mod SSM_STATE {
807        pub const offset: u32 = 8;
808        pub const mask: u32 = 0x0f << offset;
809        pub mod R {}
810        pub mod W {}
811        pub mod RW {
812            #[doc = "Init"]
813            pub const SSM_STATE_0: u32 = 0;
814            #[doc = "Hard Fail"]
815            pub const SSM_STATE_1: u32 = 0x01;
816            #[doc = "Soft Fail"]
817            pub const SSM_STATE_3: u32 = 0x03;
818            #[doc = "Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)"]
819            pub const SSM_STATE_8: u32 = 0x08;
820            #[doc = "Check"]
821            pub const SSM_STATE_9: u32 = 0x09;
822            #[doc = "Non-Secure"]
823            pub const SSM_STATE_11: u32 = 0x0b;
824            #[doc = "Trusted"]
825            pub const SSM_STATE_13: u32 = 0x0d;
826            #[doc = "Secure"]
827            pub const SSM_STATE_15: u32 = 0x0f;
828        }
829    }
830    #[doc = "Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS"]
831    pub mod SECURITY_CONFIG {
832        pub const offset: u32 = 12;
833        pub const mask: u32 = 0x0f << offset;
834        pub mod R {
835            #[doc = "FAB Configuration"]
836            pub const FAB_CONFIG: u32 = 0;
837            #[doc = "OPEN Configuration"]
838            pub const OPEN_CONFIG: u32 = 0x01;
839            #[doc = "CLOSED Configuration"]
840            pub const CLOSED_CONFIG: u32 = 0x09;
841        }
842        pub mod W {}
843        pub mod RW {}
844    }
845    #[doc = "One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location"]
846    pub mod OTPMK_SYNDROME {
847        pub const offset: u32 = 16;
848        pub const mask: u32 = 0x01ff << offset;
849        pub mod R {}
850        pub mod W {}
851        pub mod RW {}
852    }
853    #[doc = "One Time Programmable Master Key is Equal to Zero"]
854    pub mod OTPMK_ZERO {
855        pub const offset: u32 = 27;
856        pub const mask: u32 = 0x01 << offset;
857        pub mod R {}
858        pub mod W {}
859        pub mod RW {
860            #[doc = "The OTPMK is not zero."]
861            pub const OTPMK_ZERO_0: u32 = 0;
862            #[doc = "The OTPMK is zero."]
863            pub const OTPMK_ZERO_1: u32 = 0x01;
864        }
865    }
866    #[doc = "Zeroizable Master Key is Equal to Zero"]
867    pub mod ZMK_ZERO {
868        pub const offset: u32 = 31;
869        pub const mask: u32 = 0x01 << offset;
870        pub mod R {}
871        pub mod W {}
872        pub mod RW {
873            #[doc = "The ZMK is not zero."]
874            pub const ZMK_ZERO_0: u32 = 0;
875            #[doc = "The ZMK is zero."]
876            pub const ZMK_ZERO_1: u32 = 0x01;
877        }
878    }
879}
880#[doc = "SNVS_HP Security Violation Status Register"]
881pub mod HPSVSR {
882    #[doc = "Security Violation 0 security violation was detected."]
883    pub mod SV0 {
884        pub const offset: u32 = 0;
885        pub const mask: u32 = 0x01 << offset;
886        pub mod R {}
887        pub mod W {}
888        pub mod RW {
889            #[doc = "No Security Violation 0 security violation was detected."]
890            pub const SV0_0: u32 = 0;
891            #[doc = "Security Violation 0 security violation was detected."]
892            pub const SV0_1: u32 = 0x01;
893        }
894    }
895    #[doc = "Security Violation 1 security violation was detected."]
896    pub mod SV1 {
897        pub const offset: u32 = 1;
898        pub const mask: u32 = 0x01 << offset;
899        pub mod R {}
900        pub mod W {}
901        pub mod RW {
902            #[doc = "No Security Violation 1 security violation was detected."]
903            pub const SV1_0: u32 = 0;
904            #[doc = "Security Violation 1 security violation was detected."]
905            pub const SV1_1: u32 = 0x01;
906        }
907    }
908    #[doc = "Security Violation 2 security violation was detected."]
909    pub mod SV2 {
910        pub const offset: u32 = 2;
911        pub const mask: u32 = 0x01 << offset;
912        pub mod R {}
913        pub mod W {}
914        pub mod RW {
915            #[doc = "No Security Violation 2 security violation was detected."]
916            pub const SV2_0: u32 = 0;
917            #[doc = "Security Violation 2 security violation was detected."]
918            pub const SV2_1: u32 = 0x01;
919        }
920    }
921    #[doc = "Security Violation 3 security violation was detected."]
922    pub mod SV3 {
923        pub const offset: u32 = 3;
924        pub const mask: u32 = 0x01 << offset;
925        pub mod R {}
926        pub mod W {}
927        pub mod RW {
928            #[doc = "No Security Violation 3 security violation was detected."]
929            pub const SV3_0: u32 = 0;
930            #[doc = "Security Violation 3 security violation was detected."]
931            pub const SV3_1: u32 = 0x01;
932        }
933    }
934    #[doc = "Security Violation 4 security violation was detected."]
935    pub mod SV4 {
936        pub const offset: u32 = 4;
937        pub const mask: u32 = 0x01 << offset;
938        pub mod R {}
939        pub mod W {}
940        pub mod RW {
941            #[doc = "No Security Violation 4 security violation was detected."]
942            pub const SV4_0: u32 = 0;
943            #[doc = "Security Violation 4 security violation was detected."]
944            pub const SV4_1: u32 = 0x01;
945        }
946    }
947    #[doc = "Security Violation 5 security violation was detected."]
948    pub mod SV5 {
949        pub const offset: u32 = 5;
950        pub const mask: u32 = 0x01 << offset;
951        pub mod R {}
952        pub mod W {}
953        pub mod RW {
954            #[doc = "No Security Violation 5 security violation was detected."]
955            pub const SV5_0: u32 = 0;
956            #[doc = "Security Violation 5 security violation was detected."]
957            pub const SV5_1: u32 = 0x01;
958        }
959    }
960    #[doc = "Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register"]
961    pub mod SW_SV {
962        pub const offset: u32 = 13;
963        pub const mask: u32 = 0x01 << offset;
964        pub mod R {}
965        pub mod W {}
966        pub mod RW {}
967    }
968    #[doc = "Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register"]
969    pub mod SW_FSV {
970        pub const offset: u32 = 14;
971        pub const mask: u32 = 0x01 << offset;
972        pub mod R {}
973        pub mod W {}
974        pub mod RW {}
975    }
976    #[doc = "LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register"]
977    pub mod SW_LPSV {
978        pub const offset: u32 = 15;
979        pub const mask: u32 = 0x01 << offset;
980        pub mod R {}
981        pub mod W {}
982        pub mod RW {}
983    }
984    #[doc = "Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register"]
985    pub mod ZMK_SYNDROME {
986        pub const offset: u32 = 16;
987        pub const mask: u32 = 0x01ff << offset;
988        pub mod R {}
989        pub mod W {}
990        pub mod RW {}
991    }
992    #[doc = "Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data"]
993    pub mod ZMK_ECC_FAIL {
994        pub const offset: u32 = 27;
995        pub const mask: u32 = 0x01 << offset;
996        pub mod R {}
997        pub mod W {}
998        pub mod RW {
999            #[doc = "ZMK ECC Failure was not detected."]
1000            pub const ZMK_ECC_FAIL_0: u32 = 0;
1001            #[doc = "ZMK ECC Failure was detected."]
1002            pub const ZMK_ECC_FAIL_1: u32 = 0x01;
1003        }
1004    }
1005    #[doc = "LP Security Violation A security volation was detected in the SNVS low power section."]
1006    pub mod LP_SEC_VIO {
1007        pub const offset: u32 = 31;
1008        pub const mask: u32 = 0x01 << offset;
1009        pub mod R {}
1010        pub mod W {}
1011        pub mod RW {}
1012    }
1013}
1014#[doc = "SNVS_HP High Assurance Counter IV Register"]
1015pub mod HPHACIVR {
1016    #[doc = "High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter"]
1017    pub mod HAC_COUNTER_IV {
1018        pub const offset: u32 = 0;
1019        pub const mask: u32 = 0xffff_ffff << offset;
1020        pub mod R {}
1021        pub mod W {}
1022        pub mod RW {}
1023    }
1024}
1025#[doc = "SNVS_HP High Assurance Counter Register"]
1026pub mod HPHACR {
1027    #[doc = "High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock"]
1028    pub mod HAC_COUNTER {
1029        pub const offset: u32 = 0;
1030        pub const mask: u32 = 0xffff_ffff << offset;
1031        pub mod R {}
1032        pub mod W {}
1033        pub mod RW {}
1034    }
1035}
1036#[doc = "SNVS_HP Real Time Counter MSB Register"]
1037pub mod HPRTCMR {
1038    #[doc = "HP Real Time Counter The most-significant 15 bits of the RTC"]
1039    pub mod RTC {
1040        pub const offset: u32 = 0;
1041        pub const mask: u32 = 0x7fff << offset;
1042        pub mod R {}
1043        pub mod W {}
1044        pub mod RW {}
1045    }
1046}
1047#[doc = "SNVS_HP Real Time Counter LSB Register"]
1048pub mod HPRTCLR {
1049    #[doc = "HP Real Time Counter least-significant 32 bits"]
1050    pub mod RTC {
1051        pub const offset: u32 = 0;
1052        pub const mask: u32 = 0xffff_ffff << offset;
1053        pub mod R {}
1054        pub mod W {}
1055        pub mod RW {}
1056    }
1057}
1058#[doc = "SNVS_HP Time Alarm MSB Register"]
1059pub mod HPTAMR {
1060    #[doc = "HP Time Alarm, most-significant 15 bits"]
1061    pub mod HPTA_MS {
1062        pub const offset: u32 = 0;
1063        pub const mask: u32 = 0x7fff << offset;
1064        pub mod R {}
1065        pub mod W {}
1066        pub mod RW {}
1067    }
1068}
1069#[doc = "SNVS_HP Time Alarm LSB Register"]
1070pub mod HPTALR {
1071    #[doc = "HP Time Alarm, 32 least-significant bits"]
1072    pub mod HPTA_LS {
1073        pub const offset: u32 = 0;
1074        pub const mask: u32 = 0xffff_ffff << offset;
1075        pub mod R {}
1076        pub mod W {}
1077        pub mod RW {}
1078    }
1079}
1080#[doc = "SNVS_LP Lock Register"]
1081pub mod LPLR {
1082    #[doc = "Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR"]
1083    pub mod ZMK_WHL {
1084        pub const offset: u32 = 0;
1085        pub const mask: u32 = 0x01 << offset;
1086        pub mod R {}
1087        pub mod W {}
1088        pub mod RW {
1089            #[doc = "Write access is allowed."]
1090            pub const ZMK_WHL_0: u32 = 0;
1091            #[doc = "Write access is not allowed."]
1092            pub const ZMK_WHL_1: u32 = 0x01;
1093        }
1094    }
1095    #[doc = "Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR"]
1096    pub mod ZMK_RHL {
1097        pub const offset: u32 = 1;
1098        pub const mask: u32 = 0x01 << offset;
1099        pub mod R {}
1100        pub mod W {}
1101        pub mod RW {
1102            #[doc = "Read access is allowed (only in software programming mode)."]
1103            pub const ZMK_RHL_0: u32 = 0;
1104            #[doc = "Read access is not allowed."]
1105            pub const ZMK_RHL_1: u32 = 0x01;
1106        }
1107    }
1108    #[doc = "Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits"]
1109    pub mod SRTC_HL {
1110        pub const offset: u32 = 2;
1111        pub const mask: u32 = 0x01 << offset;
1112        pub mod R {}
1113        pub mod W {}
1114        pub mod RW {
1115            #[doc = "Write access is allowed."]
1116            pub const SRTC_HL_0: u32 = 0;
1117            #[doc = "Write access is not allowed."]
1118            pub const SRTC_HL_1: u32 = 0x01;
1119        }
1120    }
1121    #[doc = "LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)"]
1122    pub mod LPCALB_HL {
1123        pub const offset: u32 = 3;
1124        pub const mask: u32 = 0x01 << offset;
1125        pub mod R {}
1126        pub mod W {}
1127        pub mod RW {
1128            #[doc = "Write access is allowed."]
1129            pub const LPCALB_HL_0: u32 = 0;
1130            #[doc = "Write access is not allowed."]
1131            pub const LPCALB_HL_1: u32 = 0x01;
1132        }
1133    }
1134    #[doc = "Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit"]
1135    pub mod MC_HL {
1136        pub const offset: u32 = 4;
1137        pub const mask: u32 = 0x01 << offset;
1138        pub mod R {}
1139        pub mod W {}
1140        pub mod RW {
1141            #[doc = "Write access (increment) is allowed."]
1142            pub const MC_HL_0: u32 = 0;
1143            #[doc = "Write access (increment) is not allowed."]
1144            pub const MC_HL_1: u32 = 0x01;
1145        }
1146    }
1147    #[doc = "General Purpose Register Hard Lock When set, prevents any writes to the GPR"]
1148    pub mod GPR_HL {
1149        pub const offset: u32 = 5;
1150        pub const mask: u32 = 0x01 << offset;
1151        pub mod R {}
1152        pub mod W {}
1153        pub mod RW {
1154            #[doc = "Write access is allowed."]
1155            pub const GPR_HL_0: u32 = 0;
1156            #[doc = "Write access is not allowed."]
1157            pub const GPR_HL_1: u32 = 0x01;
1158        }
1159    }
1160    #[doc = "LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR"]
1161    pub mod LPSVCR_HL {
1162        pub const offset: u32 = 6;
1163        pub const mask: u32 = 0x01 << offset;
1164        pub mod R {}
1165        pub mod W {}
1166        pub mod RW {
1167            #[doc = "Write access is allowed."]
1168            pub const LPSVCR_HL_0: u32 = 0;
1169            #[doc = "Write access is not allowed."]
1170            pub const LPSVCR_HL_1: u32 = 0x01;
1171        }
1172    }
1173    #[doc = "LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR"]
1174    pub mod LPTDCR_HL {
1175        pub const offset: u32 = 8;
1176        pub const mask: u32 = 0x01 << offset;
1177        pub mod R {}
1178        pub mod W {}
1179        pub mod RW {
1180            #[doc = "Write access is allowed."]
1181            pub const LPTDCR_HL_0: u32 = 0;
1182            #[doc = "Write access is not allowed."]
1183            pub const LPTDCR_HL_1: u32 = 0x01;
1184        }
1185    }
1186    #[doc = "Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register"]
1187    pub mod MKS_HL {
1188        pub const offset: u32 = 9;
1189        pub const mask: u32 = 0x01 << offset;
1190        pub mod R {}
1191        pub mod W {}
1192        pub mod RW {
1193            #[doc = "Write access is allowed."]
1194            pub const MKS_HL_0: u32 = 0;
1195            #[doc = "Write access is not allowed."]
1196            pub const MKS_HL_1: u32 = 0x01;
1197        }
1198    }
1199}
1200#[doc = "SNVS_LP Control Register"]
1201pub mod LPCR {
1202    #[doc = "Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational"]
1203    pub mod SRTC_ENV {
1204        pub const offset: u32 = 0;
1205        pub const mask: u32 = 0x01 << offset;
1206        pub mod R {}
1207        pub mod W {}
1208        pub mod RW {
1209            #[doc = "SRTC is disabled or invalid."]
1210            pub const SRTC_ENV_0: u32 = 0;
1211            #[doc = "SRTC is enabled and valid."]
1212            pub const SRTC_ENV_1: u32 = 0x01;
1213        }
1214    }
1215    #[doc = "LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter"]
1216    pub mod LPTA_EN {
1217        pub const offset: u32 = 1;
1218        pub const mask: u32 = 0x01 << offset;
1219        pub mod R {}
1220        pub mod W {}
1221        pub mod RW {
1222            #[doc = "LP time alarm interrupt is disabled."]
1223            pub const LPTA_EN_0: u32 = 0;
1224            #[doc = "LP time alarm interrupt is enabled."]
1225            pub const LPTA_EN_1: u32 = 0x01;
1226        }
1227    }
1228    #[doc = "Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)"]
1229    pub mod MC_ENV {
1230        pub const offset: u32 = 2;
1231        pub const mask: u32 = 0x01 << offset;
1232        pub mod R {}
1233        pub mod W {}
1234        pub mod RW {
1235            #[doc = "MC is disabled or invalid."]
1236            pub const MC_ENV_0: u32 = 0;
1237            #[doc = "MC is enabled and valid."]
1238            pub const MC_ENV_1: u32 = 0x01;
1239        }
1240    }
1241    #[doc = "LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm )"]
1242    pub mod LPWUI_EN {
1243        pub const offset: u32 = 3;
1244        pub const mask: u32 = 0x01 << offset;
1245        pub mod R {}
1246        pub mod W {}
1247        pub mod RW {}
1248    }
1249    #[doc = "If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared)"]
1250    pub mod SRTC_INV_EN {
1251        pub const offset: u32 = 4;
1252        pub const mask: u32 = 0x01 << offset;
1253        pub mod R {}
1254        pub mod W {}
1255        pub mod RW {
1256            #[doc = "SRTC stays valid in the case of security violation."]
1257            pub const SRTC_INV_EN_0: u32 = 0;
1258            #[doc = "SRTC is invalidated in the case of security violation."]
1259            pub const SRTC_INV_EN_1: u32 = 0x01;
1260        }
1261    }
1262    #[doc = "Dumb PMIC Enabled When set, software can control the system power"]
1263    pub mod DP_EN {
1264        pub const offset: u32 = 5;
1265        pub const mask: u32 = 0x01 << offset;
1266        pub mod R {}
1267        pub mod W {}
1268        pub mod RW {
1269            #[doc = "Smart PMIC enabled."]
1270            pub const DP_EN_0: u32 = 0;
1271            #[doc = "Dumb PMIC enabled."]
1272            pub const DP_EN_1: u32 = 0x01;
1273        }
1274    }
1275    #[doc = "Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power"]
1276    pub mod TOP {
1277        pub const offset: u32 = 6;
1278        pub const mask: u32 = 0x01 << offset;
1279        pub mod R {}
1280        pub mod W {}
1281        pub mod RW {
1282            #[doc = "Leave system power on."]
1283            pub const TOP_0: u32 = 0;
1284            #[doc = "Turn off system power."]
1285            pub const TOP_1: u32 = 0x01;
1286        }
1287    }
1288    #[doc = "Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted"]
1289    pub mod PWR_GLITCH_EN {
1290        pub const offset: u32 = 7;
1291        pub const mask: u32 = 0x01 << offset;
1292        pub mod R {}
1293        pub mod W {}
1294        pub mod RW {}
1295    }
1296    #[doc = "LP Calibration Enable When set, enables the SRTC calibration mechanism"]
1297    pub mod LPCALB_EN {
1298        pub const offset: u32 = 8;
1299        pub const mask: u32 = 0x01 << offset;
1300        pub mod R {}
1301        pub mod W {}
1302        pub mod RW {
1303            #[doc = "SRTC Time calibration is disabled."]
1304            pub const LPCALB_EN_0: u32 = 0;
1305            #[doc = "SRTC Time calibration is enabled."]
1306            pub const LPCALB_EN_1: u32 = 0x01;
1307        }
1308    }
1309    #[doc = "LP Calibration Value Defines signed calibration value for SRTC"]
1310    pub mod LPCALB_VAL {
1311        pub const offset: u32 = 10;
1312        pub const mask: u32 = 0x1f << offset;
1313        pub mod R {}
1314        pub mod W {}
1315        pub mod RW {
1316            #[doc = "+0 counts per each 32768 ticks of the counter clock"]
1317            pub const LPCALB_VAL_0: u32 = 0;
1318            #[doc = "+1 counts per each 32768 ticks of the counter clock"]
1319            pub const LPCALB_VAL_1: u32 = 0x01;
1320            #[doc = "+2 counts per each 32768 ticks of the counter clock"]
1321            pub const LPCALB_VAL_2: u32 = 0x02;
1322            #[doc = "+15 counts per each 32768 ticks of the counter clock"]
1323            pub const LPCALB_VAL_15: u32 = 0x0f;
1324            #[doc = "-16 counts per each 32768 ticks of the counter clock"]
1325            pub const LPCALB_VAL_16: u32 = 0x10;
1326            #[doc = "-15 counts per each 32768 ticks of the counter clock"]
1327            pub const LPCALB_VAL_17: u32 = 0x11;
1328            #[doc = "-2 counts per each 32768 ticks of the counter clock"]
1329            pub const LPCALB_VAL_30: u32 = 0x1e;
1330            #[doc = "-1 counts per each 32768 ticks of the counter clock"]
1331            pub const LPCALB_VAL_31: u32 = 0x1f;
1332        }
1333    }
1334    #[doc = "This field configures the button press time out values for the PMIC Logic"]
1335    pub mod BTN_PRESS_TIME {
1336        pub const offset: u32 = 16;
1337        pub const mask: u32 = 0x03 << offset;
1338        pub mod R {}
1339        pub mod W {}
1340        pub mod RW {}
1341    }
1342    #[doc = "This field configures the amount of debounce time for the BTN input signal"]
1343    pub mod DEBOUNCE {
1344        pub const offset: u32 = 18;
1345        pub const mask: u32 = 0x03 << offset;
1346        pub mod R {}
1347        pub mod W {}
1348        pub mod RW {}
1349    }
1350    #[doc = "The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power"]
1351    pub mod ON_TIME {
1352        pub const offset: u32 = 20;
1353        pub const mask: u32 = 0x03 << offset;
1354        pub mod R {}
1355        pub mod W {}
1356        pub mod RW {}
1357    }
1358    #[doc = "PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en"]
1359    pub mod PK_EN {
1360        pub const offset: u32 = 22;
1361        pub const mask: u32 = 0x01 << offset;
1362        pub mod R {}
1363        pub mod W {}
1364        pub mod RW {}
1365    }
1366    #[doc = "PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override"]
1367    pub mod PK_OVERRIDE {
1368        pub const offset: u32 = 23;
1369        pub const mask: u32 = 0x01 << offset;
1370        pub mod R {}
1371        pub mod W {}
1372        pub mod RW {}
1373    }
1374    #[doc = "General Purpose Registers Zeroization Disable"]
1375    pub mod GPR_Z_DIS {
1376        pub const offset: u32 = 24;
1377        pub const mask: u32 = 0x01 << offset;
1378        pub mod R {}
1379        pub mod W {}
1380        pub mod RW {}
1381    }
1382}
1383#[doc = "SNVS_LP Master Key Control Register"]
1384pub mod LPMKCR {
1385    #[doc = "Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR"]
1386    pub mod MASTER_KEY_SEL {
1387        pub const offset: u32 = 0;
1388        pub const mask: u32 = 0x03 << offset;
1389        pub mod R {}
1390        pub mod W {}
1391        pub mod RW {
1392            #[doc = "Select one time programmable master key."]
1393            pub const MASTER_KEY_SEL_0: u32 = 0;
1394            #[doc = "Select zeroizable master key when MKS_EN bit is set ."]
1395            pub const MASTER_KEY_SEL_2: u32 = 0x02;
1396            #[doc = "Select combined master key when MKS_EN bit is set ."]
1397            pub const MASTER_KEY_SEL_3: u32 = 0x03;
1398        }
1399    }
1400    #[doc = "Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it"]
1401    pub mod ZMK_HWP {
1402        pub const offset: u32 = 2;
1403        pub const mask: u32 = 0x01 << offset;
1404        pub mod R {}
1405        pub mod W {}
1406        pub mod RW {
1407            #[doc = "ZMK is in the software programming mode."]
1408            pub const ZMK_HWP_0: u32 = 0;
1409            #[doc = "ZMK is in the hardware programming mode."]
1410            pub const ZMK_HWP_1: u32 = 0x01;
1411        }
1412    }
1413    #[doc = "Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules"]
1414    pub mod ZMK_VAL {
1415        pub const offset: u32 = 3;
1416        pub const mask: u32 = 0x01 << offset;
1417        pub mod R {}
1418        pub mod W {}
1419        pub mod RW {
1420            #[doc = "ZMK is not valid."]
1421            pub const ZMK_VAL_0: u32 = 0;
1422            #[doc = "ZMK is valid."]
1423            pub const ZMK_VAL_1: u32 = 0x01;
1424        }
1425    }
1426    #[doc = "Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register"]
1427    pub mod ZMK_ECC_EN {
1428        pub const offset: u32 = 4;
1429        pub const mask: u32 = 0x01 << offset;
1430        pub mod R {}
1431        pub mod W {}
1432        pub mod RW {
1433            #[doc = "ZMK ECC check is disabled."]
1434            pub const ZMK_ECC_EN_0: u32 = 0;
1435            #[doc = "ZMK ECC check is enabled."]
1436            pub const ZMK_ECC_EN_1: u32 = 0x01;
1437        }
1438    }
1439    #[doc = "Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register"]
1440    pub mod ZMK_ECC_VALUE {
1441        pub const offset: u32 = 7;
1442        pub const mask: u32 = 0x01ff << offset;
1443        pub mod R {}
1444        pub mod W {}
1445        pub mod RW {}
1446    }
1447}
1448#[doc = "SNVS_LP Security Violation Control Register"]
1449pub mod LPSVCR {
1450    #[doc = "Security Violation 0 Enable This bit enables Security Violation 0 Input"]
1451    pub mod SV0_EN {
1452        pub const offset: u32 = 0;
1453        pub const mask: u32 = 0x01 << offset;
1454        pub mod R {}
1455        pub mod W {}
1456        pub mod RW {
1457            #[doc = "Security Violation 0 is disabled in the LP domain."]
1458            pub const SV0_EN_0: u32 = 0;
1459            #[doc = "Security Violation 0 is enabled in the LP domain."]
1460            pub const SV0_EN_1: u32 = 0x01;
1461        }
1462    }
1463    #[doc = "Security Violation 1 Enable This bit enables Security Violation 1 Input"]
1464    pub mod SV1_EN {
1465        pub const offset: u32 = 1;
1466        pub const mask: u32 = 0x01 << offset;
1467        pub mod R {}
1468        pub mod W {}
1469        pub mod RW {
1470            #[doc = "Security Violation 1 is disabled in the LP domain."]
1471            pub const SV1_EN_0: u32 = 0;
1472            #[doc = "Security Violation 1 is enabled in the LP domain."]
1473            pub const SV1_EN_1: u32 = 0x01;
1474        }
1475    }
1476    #[doc = "Security Violation 2 Enable This bit enables Security Violation 2 Input"]
1477    pub mod SV2_EN {
1478        pub const offset: u32 = 2;
1479        pub const mask: u32 = 0x01 << offset;
1480        pub mod R {}
1481        pub mod W {}
1482        pub mod RW {
1483            #[doc = "Security Violation 2 is disabled in the LP domain."]
1484            pub const SV2_EN_0: u32 = 0;
1485            #[doc = "Security Violation 2 is enabled in the LP domain."]
1486            pub const SV2_EN_1: u32 = 0x01;
1487        }
1488    }
1489    #[doc = "Security Violation 3 Enable This bit enables Security Violation 3 Input"]
1490    pub mod SV3_EN {
1491        pub const offset: u32 = 3;
1492        pub const mask: u32 = 0x01 << offset;
1493        pub mod R {}
1494        pub mod W {}
1495        pub mod RW {
1496            #[doc = "Security Violation 3 is disabled in the LP domain."]
1497            pub const SV3_EN_0: u32 = 0;
1498            #[doc = "Security Violation 3 is enabled in the LP domain."]
1499            pub const SV3_EN_1: u32 = 0x01;
1500        }
1501    }
1502    #[doc = "Security Violation 4 Enable This bit enables Security Violation 4 Input"]
1503    pub mod SV4_EN {
1504        pub const offset: u32 = 4;
1505        pub const mask: u32 = 0x01 << offset;
1506        pub mod R {}
1507        pub mod W {}
1508        pub mod RW {
1509            #[doc = "Security Violation 4 is disabled in the LP domain."]
1510            pub const SV4_EN_0: u32 = 0;
1511            #[doc = "Security Violation 4 is enabled in the LP domain."]
1512            pub const SV4_EN_1: u32 = 0x01;
1513        }
1514    }
1515    #[doc = "Security Violation 5 Enable This bit enables Security Violation 5 Input"]
1516    pub mod SV5_EN {
1517        pub const offset: u32 = 5;
1518        pub const mask: u32 = 0x01 << offset;
1519        pub mod R {}
1520        pub mod W {}
1521        pub mod RW {
1522            #[doc = "Security Violation 5 is disabled in the LP domain."]
1523            pub const SV5_EN_0: u32 = 0;
1524            #[doc = "Security Violation 5 is enabled in the LP domain."]
1525            pub const SV5_EN_1: u32 = 0x01;
1526        }
1527    }
1528}
1529#[doc = "SNVS_LP Tamper Detectors Configuration Register"]
1530pub mod LPTDCR {
1531    #[doc = "SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation."]
1532    pub mod SRTCR_EN {
1533        pub const offset: u32 = 1;
1534        pub const mask: u32 = 0x01 << offset;
1535        pub mod R {}
1536        pub mod W {}
1537        pub mod RW {
1538            #[doc = "SRTC rollover is disabled."]
1539            pub const SRTCR_EN_0: u32 = 0;
1540            #[doc = "SRTC rollover is enabled."]
1541            pub const SRTCR_EN_1: u32 = 0x01;
1542        }
1543    }
1544    #[doc = "MC Rollover Enable When set, an MC Rollover event generates an LP security violation."]
1545    pub mod MCR_EN {
1546        pub const offset: u32 = 2;
1547        pub const mask: u32 = 0x01 << offset;
1548        pub mod R {}
1549        pub mod W {}
1550        pub mod RW {
1551            #[doc = "MC rollover is disabled."]
1552            pub const MCR_EN_0: u32 = 0;
1553            #[doc = "MC rollover is enabled."]
1554            pub const MCR_EN_1: u32 = 0x01;
1555        }
1556    }
1557    #[doc = "External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation"]
1558    pub mod ET1_EN {
1559        pub const offset: u32 = 9;
1560        pub const mask: u32 = 0x01 << offset;
1561        pub mod R {}
1562        pub mod W {}
1563        pub mod RW {
1564            #[doc = "External tamper 1 is disabled."]
1565            pub const ET1_EN_0: u32 = 0;
1566            #[doc = "External tamper 1 is enabled."]
1567            pub const ET1_EN_1: u32 = 0x01;
1568        }
1569    }
1570    #[doc = "External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1."]
1571    pub mod ET1P {
1572        pub const offset: u32 = 11;
1573        pub const mask: u32 = 0x01 << offset;
1574        pub mod R {}
1575        pub mod W {}
1576        pub mod RW {
1577            #[doc = "External tamper 1 is active low."]
1578            pub const ET1P_0: u32 = 0;
1579            #[doc = "External tamper 1 is active high."]
1580            pub const ET1P_1: u32 = 0x01;
1581        }
1582    }
1583    #[doc = "System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block)"]
1584    pub mod PFD_OBSERV {
1585        pub const offset: u32 = 14;
1586        pub const mask: u32 = 0x01 << offset;
1587        pub mod R {}
1588        pub mod W {}
1589        pub mod RW {}
1590    }
1591    #[doc = "Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS"]
1592    pub mod POR_OBSERV {
1593        pub const offset: u32 = 15;
1594        pub const mask: u32 = 0x01 << offset;
1595        pub mod R {}
1596        pub mod W {}
1597        pub mod RW {}
1598    }
1599    #[doc = "Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted"]
1600    pub mod OSCB {
1601        pub const offset: u32 = 28;
1602        pub const mask: u32 = 0x01 << offset;
1603        pub mod R {}
1604        pub mod W {}
1605        pub mod RW {
1606            #[doc = "Normal SRTC clock oscillator not bypassed."]
1607            pub const OSCB_0: u32 = 0;
1608            #[doc = "Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source."]
1609            pub const OSCB_1: u32 = 0x01;
1610        }
1611    }
1612}
1613#[doc = "SNVS_LP Status Register"]
1614pub mod LPSR {
1615    #[doc = "LP Time Alarm"]
1616    pub mod LPTA {
1617        pub const offset: u32 = 0;
1618        pub const mask: u32 = 0x01 << offset;
1619        pub mod R {}
1620        pub mod W {}
1621        pub mod RW {
1622            #[doc = "No time alarm interrupt occurred."]
1623            pub const LPTA_0: u32 = 0;
1624            #[doc = "A time alarm interrupt occurred."]
1625            pub const LPTA_1: u32 = 0x01;
1626        }
1627    }
1628    #[doc = "Secure Real Time Counter Rollover"]
1629    pub mod SRTCR {
1630        pub const offset: u32 = 1;
1631        pub const mask: u32 = 0x01 << offset;
1632        pub mod R {}
1633        pub mod W {}
1634        pub mod RW {
1635            #[doc = "SRTC has not reached its maximum value."]
1636            pub const SRTCR_0: u32 = 0;
1637            #[doc = "SRTC has reached its maximum value."]
1638            pub const SRTCR_1: u32 = 0x01;
1639        }
1640    }
1641    #[doc = "Monotonic Counter Rollover"]
1642    pub mod MCR {
1643        pub const offset: u32 = 2;
1644        pub const mask: u32 = 0x01 << offset;
1645        pub mod R {}
1646        pub mod W {}
1647        pub mod RW {
1648            #[doc = "MC has not reached its maximum value."]
1649            pub const MCR_0: u32 = 0;
1650            #[doc = "MC has reached its maximum value."]
1651            pub const MCR_1: u32 = 0x01;
1652        }
1653    }
1654    #[doc = "Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected."]
1655    pub mod PGD {
1656        pub const offset: u32 = 3;
1657        pub const mask: u32 = 0x01 << offset;
1658        pub mod R {}
1659        pub mod W {}
1660        pub mod RW {}
1661    }
1662    #[doc = "External Tampering 1 Detected"]
1663    pub mod ET1D {
1664        pub const offset: u32 = 9;
1665        pub const mask: u32 = 0x01 << offset;
1666        pub mod R {}
1667        pub mod W {}
1668        pub mod RW {
1669            #[doc = "External tampering 1 not detected."]
1670            pub const ET1D_0: u32 = 0;
1671            #[doc = "External tampering 1 detected."]
1672            pub const ET1D_1: u32 = 0x01;
1673        }
1674    }
1675    #[doc = "External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports"]
1676    pub mod ESVD {
1677        pub const offset: u32 = 16;
1678        pub const mask: u32 = 0x01 << offset;
1679        pub mod R {}
1680        pub mod W {}
1681        pub mod RW {
1682            #[doc = "No external security violation."]
1683            pub const ESVD_0: u32 = 0;
1684            #[doc = "External security violation is detected."]
1685            pub const ESVD_1: u32 = 0x01;
1686        }
1687    }
1688    #[doc = "Emergency Off This bit is set when a power off is requested."]
1689    pub mod EO {
1690        pub const offset: u32 = 17;
1691        pub const mask: u32 = 0x01 << offset;
1692        pub mod R {}
1693        pub mod W {}
1694        pub mod RW {
1695            #[doc = "Emergency off was not detected."]
1696            pub const EO_0: u32 = 0;
1697            #[doc = "Emergency off was detected."]
1698            pub const EO_1: u32 = 0x01;
1699        }
1700    }
1701    #[doc = "Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time"]
1702    pub mod SPO {
1703        pub const offset: u32 = 18;
1704        pub const mask: u32 = 0x01 << offset;
1705        pub mod R {}
1706        pub mod W {}
1707        pub mod RW {
1708            #[doc = "Set Power Off was not detected."]
1709            pub const SPO_0: u32 = 0;
1710            #[doc = "Set Power Off was detected."]
1711            pub const SPO_1: u32 = 0x01;
1712        }
1713    }
1714    #[doc = "Scan Exit Detected"]
1715    pub mod SED {
1716        pub const offset: u32 = 20;
1717        pub const mask: u32 = 0x01 << offset;
1718        pub mod R {}
1719        pub mod W {}
1720        pub mod RW {
1721            #[doc = "Scan exit was not detected."]
1722            pub const SED_0: u32 = 0;
1723            #[doc = "Scan exit was detected."]
1724            pub const SED_1: u32 = 0x01;
1725        }
1726    }
1727    #[doc = "LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state"]
1728    pub mod LPNS {
1729        pub const offset: u32 = 30;
1730        pub const mask: u32 = 0x01 << offset;
1731        pub mod R {}
1732        pub mod W {}
1733        pub mod RW {
1734            #[doc = "LP section was not programmed in the non-secure state."]
1735            pub const LPNS_0: u32 = 0;
1736            #[doc = "LP section was programmed in the non-secure state."]
1737            pub const LPNS_1: u32 = 0x01;
1738        }
1739    }
1740    #[doc = "LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state"]
1741    pub mod LPS {
1742        pub const offset: u32 = 31;
1743        pub const mask: u32 = 0x01 << offset;
1744        pub mod R {}
1745        pub mod W {}
1746        pub mod RW {
1747            #[doc = "LP section was not programmed in secure or trusted state."]
1748            pub const LPS_0: u32 = 0;
1749            #[doc = "LP section was programmed in secure or trusted state."]
1750            pub const LPS_1: u32 = 0x01;
1751        }
1752    }
1753}
1754#[doc = "SNVS_LP Secure Real Time Counter MSB Register"]
1755pub mod LPSRTCMR {
1756    #[doc = "LP Secure Real Time Counter The most-significant 15 bits of the SRTC"]
1757    pub mod SRTC {
1758        pub const offset: u32 = 0;
1759        pub const mask: u32 = 0x7fff << offset;
1760        pub mod R {}
1761        pub mod W {}
1762        pub mod RW {}
1763    }
1764}
1765#[doc = "SNVS_LP Secure Real Time Counter LSB Register"]
1766pub mod LPSRTCLR {
1767    #[doc = "LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set"]
1768    pub mod SRTC {
1769        pub const offset: u32 = 0;
1770        pub const mask: u32 = 0xffff_ffff << offset;
1771        pub mod R {}
1772        pub mod W {}
1773        pub mod RW {}
1774    }
1775}
1776#[doc = "SNVS_LP Time Alarm Register"]
1777pub mod LPTAR {
1778    #[doc = "LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set)"]
1779    pub mod LPTA {
1780        pub const offset: u32 = 0;
1781        pub const mask: u32 = 0xffff_ffff << offset;
1782        pub mod R {}
1783        pub mod W {}
1784        pub mod RW {}
1785    }
1786}
1787#[doc = "SNVS_LP Secure Monotonic Counter MSB Register"]
1788pub mod LPSMCMR {
1789    #[doc = "Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected"]
1790    pub mod MON_COUNTER {
1791        pub const offset: u32 = 0;
1792        pub const mask: u32 = 0xffff << offset;
1793        pub mod R {}
1794        pub mod W {}
1795        pub mod RW {}
1796    }
1797    #[doc = "Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses"]
1798    pub mod MC_ERA_BITS {
1799        pub const offset: u32 = 16;
1800        pub const mask: u32 = 0xffff << offset;
1801        pub mod R {}
1802        pub mod W {}
1803        pub mod RW {}
1804    }
1805}
1806#[doc = "SNVS_LP Secure Monotonic Counter LSB Register"]
1807pub mod LPSMCLR {
1808    #[doc = "Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected"]
1809    pub mod MON_COUNTER {
1810        pub const offset: u32 = 0;
1811        pub const mask: u32 = 0xffff_ffff << offset;
1812        pub mod R {}
1813        pub mod W {}
1814        pub mod RW {}
1815    }
1816}
1817#[doc = "SNVS_LP Power Glitch Detector Register"]
1818pub mod LPPGDR {
1819    #[doc = "Power Glitch Detector Value"]
1820    pub mod PGD {
1821        pub const offset: u32 = 0;
1822        pub const mask: u32 = 0xffff_ffff << offset;
1823        pub mod R {}
1824        pub mod W {}
1825        pub mod RW {}
1826    }
1827}
1828#[doc = "SNVS_LP General Purpose Register 0 (legacy alias)"]
1829pub mod LPGPR0_LEGACY_ALIAS {
1830    #[doc = "General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed."]
1831    pub mod GPR {
1832        pub const offset: u32 = 0;
1833        pub const mask: u32 = 0xffff_ffff << offset;
1834        pub mod R {}
1835        pub mod W {}
1836        pub mod RW {}
1837    }
1838}
1839#[doc = "SNVS_LP Zeroizable Master Key Register"]
1840pub mod LPZMKR {
1841    #[doc = "Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value"]
1842    pub mod ZMK {
1843        pub const offset: u32 = 0;
1844        pub const mask: u32 = 0xffff_ffff << offset;
1845        pub mod R {}
1846        pub mod W {}
1847        pub mod RW {}
1848    }
1849}
1850#[doc = "SNVS_LP General Purpose Registers 0 .. 3"]
1851pub mod LPGPR_ALIAS {
1852    #[doc = "General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed."]
1853    pub mod GPR {
1854        pub const offset: u32 = 0;
1855        pub const mask: u32 = 0xffff_ffff << offset;
1856        pub mod R {}
1857        pub mod W {}
1858        pub mod RW {}
1859    }
1860}
1861#[doc = "SNVS_LP General Purpose Registers 0 .. 3"]
1862pub mod LPGPR {
1863    #[doc = "General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed."]
1864    pub mod GPR {
1865        pub const offset: u32 = 0;
1866        pub const mask: u32 = 0xffff_ffff << offset;
1867        pub mod R {}
1868        pub mod W {}
1869        pub mod RW {}
1870    }
1871}
1872#[doc = "SNVS_HP Version ID Register 1"]
1873pub mod HPVIDR1 {
1874    #[doc = "SNVS block minor version number"]
1875    pub mod MINOR_REV {
1876        pub const offset: u32 = 0;
1877        pub const mask: u32 = 0xff << offset;
1878        pub mod R {}
1879        pub mod W {}
1880        pub mod RW {}
1881    }
1882    #[doc = "SNVS block major version number"]
1883    pub mod MAJOR_REV {
1884        pub const offset: u32 = 8;
1885        pub const mask: u32 = 0xff << offset;
1886        pub mod R {}
1887        pub mod W {}
1888        pub mod RW {}
1889    }
1890    #[doc = "SNVS block ID"]
1891    pub mod IP_ID {
1892        pub const offset: u32 = 16;
1893        pub const mask: u32 = 0xffff << offset;
1894        pub mod R {}
1895        pub mod W {}
1896        pub mod RW {}
1897    }
1898}
1899#[doc = "SNVS_HP Version ID Register 2"]
1900pub mod HPVIDR2 {
1901    #[doc = "SNVS Configuration Options"]
1902    pub mod CONFIG_OPT {
1903        pub const offset: u32 = 0;
1904        pub const mask: u32 = 0xff << offset;
1905        pub mod R {}
1906        pub mod W {}
1907        pub mod RW {}
1908    }
1909    #[doc = "SNVS ECO Revision"]
1910    pub mod ECO_REV {
1911        pub const offset: u32 = 8;
1912        pub const mask: u32 = 0xff << offset;
1913        pub mod R {}
1914        pub mod W {}
1915        pub mod RW {}
1916    }
1917    #[doc = "SNVS Integration Options"]
1918    pub mod INTG_OPT {
1919        pub const offset: u32 = 16;
1920        pub const mask: u32 = 0xff << offset;
1921        pub mod R {}
1922        pub mod W {}
1923        pub mod RW {}
1924    }
1925    #[doc = "IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5"]
1926    pub mod IP_ERA {
1927        pub const offset: u32 = 24;
1928        pub const mask: u32 = 0xff << offset;
1929        pub mod R {}
1930        pub mod W {}
1931        pub mod RW {}
1932    }
1933}
imxrt_ral/blocks/imxrt1011/snvs.rs

imxrt_ral/blocks/imxrt1011/
snvs.rs
