rp2040_pac/adc/
cs.rs

Help
1#[doc = "Register `CS` reader"]
2pub type R = crate::R<CS_SPEC>;
3#[doc = "Register `CS` writer"]
4pub type W = crate::W<CS_SPEC>;
5#[doc = "Field `EN` reader - Power on ADC and enable its clock.  
6 1 - enabled. 0 - disabled."]
7pub type EN_R = crate::BitReader;
8#[doc = "Field `EN` writer - Power on ADC and enable its clock.  
9 1 - enabled. 0 - disabled."]
10pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."]
12pub type TS_EN_R = crate::BitReader;
13#[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."]
14pub type TS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
16pub type START_ONCE_R = crate::BitReader;
17#[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
18pub type START_ONCE_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
20pub type START_MANY_R = crate::BitReader;
21#[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
22pub type START_MANY_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.  
24 0 whilst conversion in progress."]
25pub type READY_R = crate::BitReader;
26#[doc = "Field `ERR` reader - The most recent ADC conversion encountered an error; result is undefined or noisy."]
27pub type ERR_R = crate::BitReader;
28#[doc = "Field `ERR_STICKY` reader - Some past ADC conversion encountered an error. Write 1 to clear."]
29pub type ERR_STICKY_R = crate::BitReader;
30#[doc = "Field `ERR_STICKY` writer - Some past ADC conversion encountered an error. Write 1 to clear."]
31pub type ERR_STICKY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
32#[doc = "Field `AINSEL` reader - Select analog mux input. Updated automatically in round-robin mode."]
33pub type AINSEL_R = crate::FieldReader;
34#[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode."]
35pub type AINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
36#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
37 Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
38 The first channel to be sampled will be the one currently indicated by AINSEL.  
39 AINSEL will be updated after each conversion with the newly-selected channel."]
40pub type RROBIN_R = crate::FieldReader;
41#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
42 Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
43 The first channel to be sampled will be the one currently indicated by AINSEL.  
44 AINSEL will be updated after each conversion with the newly-selected channel."]
45pub type RROBIN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
46impl R {
47    #[doc = "Bit 0 - Power on ADC and enable its clock.  
48 1 - enabled. 0 - disabled."]
49    #[inline(always)]
50    pub fn en(&self) -> EN_R {
51        EN_R::new((self.bits & 1) != 0)
52    }
53    #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."]
54    #[inline(always)]
55    pub fn ts_en(&self) -> TS_EN_R {
56        TS_EN_R::new(((self.bits >> 1) & 1) != 0)
57    }
58    #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
59    #[inline(always)]
60    pub fn start_once(&self) -> START_ONCE_R {
61        START_ONCE_R::new(((self.bits >> 2) & 1) != 0)
62    }
63    #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
64    #[inline(always)]
65    pub fn start_many(&self) -> START_MANY_R {
66        START_MANY_R::new(((self.bits >> 3) & 1) != 0)
67    }
68    #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.  
69 0 whilst conversion in progress."]
70    #[inline(always)]
71    pub fn ready(&self) -> READY_R {
72        READY_R::new(((self.bits >> 8) & 1) != 0)
73    }
74    #[doc = "Bit 9 - The most recent ADC conversion encountered an error; result is undefined or noisy."]
75    #[inline(always)]
76    pub fn err(&self) -> ERR_R {
77        ERR_R::new(((self.bits >> 9) & 1) != 0)
78    }
79    #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."]
80    #[inline(always)]
81    pub fn err_sticky(&self) -> ERR_STICKY_R {
82        ERR_STICKY_R::new(((self.bits >> 10) & 1) != 0)
83    }
84    #[doc = "Bits 12:14 - Select analog mux input. Updated automatically in round-robin mode."]
85    #[inline(always)]
86    pub fn ainsel(&self) -> AINSEL_R {
87        AINSEL_R::new(((self.bits >> 12) & 7) as u8)
88    }
89    #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
90 Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
91 The first channel to be sampled will be the one currently indicated by AINSEL.  
92 AINSEL will be updated after each conversion with the newly-selected channel."]
93    #[inline(always)]
94    pub fn rrobin(&self) -> RROBIN_R {
95        RROBIN_R::new(((self.bits >> 16) & 0x1f) as u8)
96    }
97}
98impl W {
99    #[doc = "Bit 0 - Power on ADC and enable its clock.  
100 1 - enabled. 0 - disabled."]
101    #[inline(always)]
102    #[must_use]
103    pub fn en(&mut self) -> EN_W<CS_SPEC> {
104        EN_W::new(self, 0)
105    }
106    #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."]
107    #[inline(always)]
108    #[must_use]
109    pub fn ts_en(&mut self) -> TS_EN_W<CS_SPEC> {
110        TS_EN_W::new(self, 1)
111    }
112    #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
113    #[inline(always)]
114    #[must_use]
115    pub fn start_once(&mut self) -> START_ONCE_W<CS_SPEC> {
116        START_ONCE_W::new(self, 2)
117    }
118    #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
119    #[inline(always)]
120    #[must_use]
121    pub fn start_many(&mut self) -> START_MANY_W<CS_SPEC> {
122        START_MANY_W::new(self, 3)
123    }
124    #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."]
125    #[inline(always)]
126    #[must_use]
127    pub fn err_sticky(&mut self) -> ERR_STICKY_W<CS_SPEC> {
128        ERR_STICKY_W::new(self, 10)
129    }
130    #[doc = "Bits 12:14 - Select analog mux input. Updated automatically in round-robin mode."]
131    #[inline(always)]
132    #[must_use]
133    pub fn ainsel(&mut self) -> AINSEL_W<CS_SPEC> {
134        AINSEL_W::new(self, 12)
135    }
136    #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
137 Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
138 The first channel to be sampled will be the one currently indicated by AINSEL.  
139 AINSEL will be updated after each conversion with the newly-selected channel."]
140    #[inline(always)]
141    #[must_use]
142    pub fn rrobin(&mut self) -> RROBIN_W<CS_SPEC> {
143        RROBIN_W::new(self, 16)
144    }
145    #[doc = r" Writes raw bits to the register."]
146    #[doc = r""]
147    #[doc = r" # Safety"]
148    #[doc = r""]
149    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
150    #[inline(always)]
151    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
152        self.bits = bits;
153        self
154    }
155}
156#[doc = "ADC Control and Status  
157
158You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
159pub struct CS_SPEC;
160impl crate::RegisterSpec for CS_SPEC {
161    type Ux = u32;
162}
163#[doc = "`read()` method returns [`cs::R`](R) reader structure"]
164impl crate::Readable for CS_SPEC {}
165#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"]
166impl crate::Writable for CS_SPEC {
167    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
168    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400;
169}
170#[doc = "`reset()` method sets CS to value 0"]
171impl crate::Resettable for CS_SPEC {
172    const RESET_VALUE: u32 = 0;
173}
rp2040_pac/adc/cs.rs

rp2040_pac/adc/
cs.rs
