rp2040_pac/clocks/
clk_sys_ctrl.rs

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1#[doc = "Register `CLK_SYS_CTRL` reader"]
2pub type R = crate::R<CLK_SYS_CTRL_SPEC>;
3#[doc = "Register `CLK_SYS_CTRL` writer"]
4pub type W = crate::W<CLK_SYS_CTRL_SPEC>;
5#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"]
6pub type SRC_R = crate::BitReader<SRC_A>;
7#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum SRC_A {
12    #[doc = "0: `0`"]
13    CLK_REF = 0,
14    #[doc = "1: `1`"]
15    CLKSRC_CLK_SYS_AUX = 1,
16}
17impl From<SRC_A> for bool {
18    #[inline(always)]
19    fn from(variant: SRC_A) -> Self {
20        variant as u8 != 0
21    }
22}
23impl SRC_R {
24    #[doc = "Get enumerated values variant"]
25    #[inline(always)]
26    pub const fn variant(&self) -> SRC_A {
27        match self.bits {
28            false => SRC_A::CLK_REF,
29            true => SRC_A::CLKSRC_CLK_SYS_AUX,
30        }
31    }
32    #[doc = "`0`"]
33    #[inline(always)]
34    pub fn is_clk_ref(&self) -> bool {
35        *self == SRC_A::CLK_REF
36    }
37    #[doc = "`1`"]
38    #[inline(always)]
39    pub fn is_clksrc_clk_sys_aux(&self) -> bool {
40        *self == SRC_A::CLKSRC_CLK_SYS_AUX
41    }
42}
43#[doc = "Field `SRC` writer - Selects the clock source glitchlessly, can be changed on-the-fly"]
44pub type SRC_W<'a, REG> = crate::BitWriter<'a, REG, SRC_A>;
45impl<'a, REG> SRC_W<'a, REG>
46where
47    REG: crate::Writable + crate::RegisterSpec,
48{
49    #[doc = "`0`"]
50    #[inline(always)]
51    pub fn clk_ref(self) -> &'a mut crate::W<REG> {
52        self.variant(SRC_A::CLK_REF)
53    }
54    #[doc = "`1`"]
55    #[inline(always)]
56    pub fn clksrc_clk_sys_aux(self) -> &'a mut crate::W<REG> {
57        self.variant(SRC_A::CLKSRC_CLK_SYS_AUX)
58    }
59}
60#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
61pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
62#[doc = "Selects the auxiliary clock source, will glitch when switching  
63
64Value on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum AUXSRC_A {
68    #[doc = "0: `0`"]
69    CLKSRC_PLL_SYS = 0,
70    #[doc = "1: `1`"]
71    CLKSRC_PLL_USB = 1,
72    #[doc = "2: `10`"]
73    ROSC_CLKSRC = 2,
74    #[doc = "3: `11`"]
75    XOSC_CLKSRC = 3,
76    #[doc = "4: `100`"]
77    CLKSRC_GPIN0 = 4,
78    #[doc = "5: `101`"]
79    CLKSRC_GPIN1 = 5,
80}
81impl From<AUXSRC_A> for u8 {
82    #[inline(always)]
83    fn from(variant: AUXSRC_A) -> Self {
84        variant as _
85    }
86}
87impl crate::FieldSpec for AUXSRC_A {
88    type Ux = u8;
89}
90impl AUXSRC_R {
91    #[doc = "Get enumerated values variant"]
92    #[inline(always)]
93    pub const fn variant(&self) -> Option<AUXSRC_A> {
94        match self.bits {
95            0 => Some(AUXSRC_A::CLKSRC_PLL_SYS),
96            1 => Some(AUXSRC_A::CLKSRC_PLL_USB),
97            2 => Some(AUXSRC_A::ROSC_CLKSRC),
98            3 => Some(AUXSRC_A::XOSC_CLKSRC),
99            4 => Some(AUXSRC_A::CLKSRC_GPIN0),
100            5 => Some(AUXSRC_A::CLKSRC_GPIN1),
101            _ => None,
102        }
103    }
104    #[doc = "`0`"]
105    #[inline(always)]
106    pub fn is_clksrc_pll_sys(&self) -> bool {
107        *self == AUXSRC_A::CLKSRC_PLL_SYS
108    }
109    #[doc = "`1`"]
110    #[inline(always)]
111    pub fn is_clksrc_pll_usb(&self) -> bool {
112        *self == AUXSRC_A::CLKSRC_PLL_USB
113    }
114    #[doc = "`10`"]
115    #[inline(always)]
116    pub fn is_rosc_clksrc(&self) -> bool {
117        *self == AUXSRC_A::ROSC_CLKSRC
118    }
119    #[doc = "`11`"]
120    #[inline(always)]
121    pub fn is_xosc_clksrc(&self) -> bool {
122        *self == AUXSRC_A::XOSC_CLKSRC
123    }
124    #[doc = "`100`"]
125    #[inline(always)]
126    pub fn is_clksrc_gpin0(&self) -> bool {
127        *self == AUXSRC_A::CLKSRC_GPIN0
128    }
129    #[doc = "`101`"]
130    #[inline(always)]
131    pub fn is_clksrc_gpin1(&self) -> bool {
132        *self == AUXSRC_A::CLKSRC_GPIN1
133    }
134}
135#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"]
136pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>;
137impl<'a, REG> AUXSRC_W<'a, REG>
138where
139    REG: crate::Writable + crate::RegisterSpec,
140    REG::Ux: From<u8>,
141{
142    #[doc = "`0`"]
143    #[inline(always)]
144    pub fn clksrc_pll_sys(self) -> &'a mut crate::W<REG> {
145        self.variant(AUXSRC_A::CLKSRC_PLL_SYS)
146    }
147    #[doc = "`1`"]
148    #[inline(always)]
149    pub fn clksrc_pll_usb(self) -> &'a mut crate::W<REG> {
150        self.variant(AUXSRC_A::CLKSRC_PLL_USB)
151    }
152    #[doc = "`10`"]
153    #[inline(always)]
154    pub fn rosc_clksrc(self) -> &'a mut crate::W<REG> {
155        self.variant(AUXSRC_A::ROSC_CLKSRC)
156    }
157    #[doc = "`11`"]
158    #[inline(always)]
159    pub fn xosc_clksrc(self) -> &'a mut crate::W<REG> {
160        self.variant(AUXSRC_A::XOSC_CLKSRC)
161    }
162    #[doc = "`100`"]
163    #[inline(always)]
164    pub fn clksrc_gpin0(self) -> &'a mut crate::W<REG> {
165        self.variant(AUXSRC_A::CLKSRC_GPIN0)
166    }
167    #[doc = "`101`"]
168    #[inline(always)]
169    pub fn clksrc_gpin1(self) -> &'a mut crate::W<REG> {
170        self.variant(AUXSRC_A::CLKSRC_GPIN1)
171    }
172}
173impl R {
174    #[doc = "Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly"]
175    #[inline(always)]
176    pub fn src(&self) -> SRC_R {
177        SRC_R::new((self.bits & 1) != 0)
178    }
179    #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
180    #[inline(always)]
181    pub fn auxsrc(&self) -> AUXSRC_R {
182        AUXSRC_R::new(((self.bits >> 5) & 7) as u8)
183    }
184}
185impl W {
186    #[doc = "Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly"]
187    #[inline(always)]
188    #[must_use]
189    pub fn src(&mut self) -> SRC_W<CLK_SYS_CTRL_SPEC> {
190        SRC_W::new(self, 0)
191    }
192    #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
193    #[inline(always)]
194    #[must_use]
195    pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_SYS_CTRL_SPEC> {
196        AUXSRC_W::new(self, 5)
197    }
198    #[doc = r" Writes raw bits to the register."]
199    #[doc = r""]
200    #[doc = r" # Safety"]
201    #[doc = r""]
202    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
203    #[inline(always)]
204    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
205        self.bits = bits;
206        self
207    }
208}
209#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
210
211You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct CLK_SYS_CTRL_SPEC;
213impl crate::RegisterSpec for CLK_SYS_CTRL_SPEC {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [`clk_sys_ctrl::R`](R) reader structure"]
217impl crate::Readable for CLK_SYS_CTRL_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`clk_sys_ctrl::W`](W) writer structure"]
219impl crate::Writable for CLK_SYS_CTRL_SPEC {
220    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
221    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
222}
223#[doc = "`reset()` method sets CLK_SYS_CTRL to value 0"]
224impl crate::Resettable for CLK_SYS_CTRL_SPEC {
225    const RESET_VALUE: u32 = 0;
226}
rp2040_pac/clocks/clk_sys_ctrl.rs

rp2040_pac/clocks/
clk_sys_ctrl.rs
