rp2040_pac/clocks/
clk_adc_ctrl.rs

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1#[doc = "Register `CLK_ADC_CTRL` reader"]
2pub type R = crate::R<CLK_ADC_CTRL_SPEC>;
3#[doc = "Register `CLK_ADC_CTRL` writer"]
4pub type W = crate::W<CLK_ADC_CTRL_SPEC>;
5#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
6pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
7#[doc = "Selects the auxiliary clock source, will glitch when switching  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum AUXSRC_A {
13    #[doc = "0: `0`"]
14    CLKSRC_PLL_USB = 0,
15    #[doc = "1: `1`"]
16    CLKSRC_PLL_SYS = 1,
17    #[doc = "2: `10`"]
18    ROSC_CLKSRC_PH = 2,
19    #[doc = "3: `11`"]
20    XOSC_CLKSRC = 3,
21    #[doc = "4: `100`"]
22    CLKSRC_GPIN0 = 4,
23    #[doc = "5: `101`"]
24    CLKSRC_GPIN1 = 5,
25}
26impl From<AUXSRC_A> for u8 {
27    #[inline(always)]
28    fn from(variant: AUXSRC_A) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for AUXSRC_A {
33    type Ux = u8;
34}
35impl AUXSRC_R {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<AUXSRC_A> {
39        match self.bits {
40            0 => Some(AUXSRC_A::CLKSRC_PLL_USB),
41            1 => Some(AUXSRC_A::CLKSRC_PLL_SYS),
42            2 => Some(AUXSRC_A::ROSC_CLKSRC_PH),
43            3 => Some(AUXSRC_A::XOSC_CLKSRC),
44            4 => Some(AUXSRC_A::CLKSRC_GPIN0),
45            5 => Some(AUXSRC_A::CLKSRC_GPIN1),
46            _ => None,
47        }
48    }
49    #[doc = "`0`"]
50    #[inline(always)]
51    pub fn is_clksrc_pll_usb(&self) -> bool {
52        *self == AUXSRC_A::CLKSRC_PLL_USB
53    }
54    #[doc = "`1`"]
55    #[inline(always)]
56    pub fn is_clksrc_pll_sys(&self) -> bool {
57        *self == AUXSRC_A::CLKSRC_PLL_SYS
58    }
59    #[doc = "`10`"]
60    #[inline(always)]
61    pub fn is_rosc_clksrc_ph(&self) -> bool {
62        *self == AUXSRC_A::ROSC_CLKSRC_PH
63    }
64    #[doc = "`11`"]
65    #[inline(always)]
66    pub fn is_xosc_clksrc(&self) -> bool {
67        *self == AUXSRC_A::XOSC_CLKSRC
68    }
69    #[doc = "`100`"]
70    #[inline(always)]
71    pub fn is_clksrc_gpin0(&self) -> bool {
72        *self == AUXSRC_A::CLKSRC_GPIN0
73    }
74    #[doc = "`101`"]
75    #[inline(always)]
76    pub fn is_clksrc_gpin1(&self) -> bool {
77        *self == AUXSRC_A::CLKSRC_GPIN1
78    }
79}
80#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"]
81pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>;
82impl<'a, REG> AUXSRC_W<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn clksrc_pll_usb(self) -> &'a mut crate::W<REG> {
90        self.variant(AUXSRC_A::CLKSRC_PLL_USB)
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn clksrc_pll_sys(self) -> &'a mut crate::W<REG> {
95        self.variant(AUXSRC_A::CLKSRC_PLL_SYS)
96    }
97    #[doc = "`10`"]
98    #[inline(always)]
99    pub fn rosc_clksrc_ph(self) -> &'a mut crate::W<REG> {
100        self.variant(AUXSRC_A::ROSC_CLKSRC_PH)
101    }
102    #[doc = "`11`"]
103    #[inline(always)]
104    pub fn xosc_clksrc(self) -> &'a mut crate::W<REG> {
105        self.variant(AUXSRC_A::XOSC_CLKSRC)
106    }
107    #[doc = "`100`"]
108    #[inline(always)]
109    pub fn clksrc_gpin0(self) -> &'a mut crate::W<REG> {
110        self.variant(AUXSRC_A::CLKSRC_GPIN0)
111    }
112    #[doc = "`101`"]
113    #[inline(always)]
114    pub fn clksrc_gpin1(self) -> &'a mut crate::W<REG> {
115        self.variant(AUXSRC_A::CLKSRC_GPIN1)
116    }
117}
118#[doc = "Field `KILL` reader - Asynchronously kills the clock generator"]
119pub type KILL_R = crate::BitReader;
120#[doc = "Field `KILL` writer - Asynchronously kills the clock generator"]
121pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>;
122#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"]
123pub type ENABLE_R = crate::BitReader;
124#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"]
125pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
126#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock  
127 This must be set before the clock is enabled to have any effect"]
128pub type PHASE_R = crate::FieldReader;
129#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock  
130 This must be set before the clock is enabled to have any effect"]
131pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
132#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
133 This can be done at any time"]
134pub type NUDGE_R = crate::BitReader;
135#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
136 This can be done at any time"]
137pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
138impl R {
139    #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
140    #[inline(always)]
141    pub fn auxsrc(&self) -> AUXSRC_R {
142        AUXSRC_R::new(((self.bits >> 5) & 7) as u8)
143    }
144    #[doc = "Bit 10 - Asynchronously kills the clock generator"]
145    #[inline(always)]
146    pub fn kill(&self) -> KILL_R {
147        KILL_R::new(((self.bits >> 10) & 1) != 0)
148    }
149    #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
150    #[inline(always)]
151    pub fn enable(&self) -> ENABLE_R {
152        ENABLE_R::new(((self.bits >> 11) & 1) != 0)
153    }
154    #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock  
155 This must be set before the clock is enabled to have any effect"]
156    #[inline(always)]
157    pub fn phase(&self) -> PHASE_R {
158        PHASE_R::new(((self.bits >> 16) & 3) as u8)
159    }
160    #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
161 This can be done at any time"]
162    #[inline(always)]
163    pub fn nudge(&self) -> NUDGE_R {
164        NUDGE_R::new(((self.bits >> 20) & 1) != 0)
165    }
166}
167impl W {
168    #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
169    #[inline(always)]
170    #[must_use]
171    pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_ADC_CTRL_SPEC> {
172        AUXSRC_W::new(self, 5)
173    }
174    #[doc = "Bit 10 - Asynchronously kills the clock generator"]
175    #[inline(always)]
176    #[must_use]
177    pub fn kill(&mut self) -> KILL_W<CLK_ADC_CTRL_SPEC> {
178        KILL_W::new(self, 10)
179    }
180    #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
181    #[inline(always)]
182    #[must_use]
183    pub fn enable(&mut self) -> ENABLE_W<CLK_ADC_CTRL_SPEC> {
184        ENABLE_W::new(self, 11)
185    }
186    #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock  
187 This must be set before the clock is enabled to have any effect"]
188    #[inline(always)]
189    #[must_use]
190    pub fn phase(&mut self) -> PHASE_W<CLK_ADC_CTRL_SPEC> {
191        PHASE_W::new(self, 16)
192    }
193    #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock  
194 This can be done at any time"]
195    #[inline(always)]
196    #[must_use]
197    pub fn nudge(&mut self) -> NUDGE_W<CLK_ADC_CTRL_SPEC> {
198        NUDGE_W::new(self, 20)
199    }
200    #[doc = r" Writes raw bits to the register."]
201    #[doc = r""]
202    #[doc = r" # Safety"]
203    #[doc = r""]
204    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
205    #[inline(always)]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.bits = bits;
208        self
209    }
210}
211#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
212
213You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
214pub struct CLK_ADC_CTRL_SPEC;
215impl crate::RegisterSpec for CLK_ADC_CTRL_SPEC {
216    type Ux = u32;
217}
218#[doc = "`read()` method returns [`clk_adc_ctrl::R`](R) reader structure"]
219impl crate::Readable for CLK_ADC_CTRL_SPEC {}
220#[doc = "`write(|w| ..)` method takes [`clk_adc_ctrl::W`](W) writer structure"]
221impl crate::Writable for CLK_ADC_CTRL_SPEC {
222    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
223    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
224}
225#[doc = "`reset()` method sets CLK_ADC_CTRL to value 0"]
226impl crate::Resettable for CLK_ADC_CTRL_SPEC {
227    const RESET_VALUE: u32 = 0;
228}
rp2040_pac/clocks/clk_adc_ctrl.rs

rp2040_pac/clocks/
clk_adc_ctrl.rs
