imxrt_ral/blocks/imxrt1011/
iomuxc_gpr.rs
1#[doc = "IOMUXC_GPR"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "GPR0 General Purpose Register"]
5 pub GPR0: crate::RORegister<u32>,
6 #[doc = "GPR1 General Purpose Register"]
7 pub GPR1: crate::RWRegister<u32>,
8 #[doc = "GPR2 General Purpose Register"]
9 pub GPR2: crate::RWRegister<u32>,
10 #[doc = "GPR3 General Purpose Register"]
11 pub GPR3: crate::RWRegister<u32>,
12 #[doc = "GPR4 General Purpose Register"]
13 pub GPR4: crate::RWRegister<u32>,
14 #[doc = "GPR5 General Purpose Register"]
15 pub GPR5: crate::RWRegister<u32>,
16 #[doc = "GPR6 General Purpose Register"]
17 pub GPR6: crate::RWRegister<u32>,
18 #[doc = "GPR7 General Purpose Register"]
19 pub GPR7: crate::RWRegister<u32>,
20 #[doc = "GPR8 General Purpose Register"]
21 pub GPR8: crate::RWRegister<u32>,
22 #[doc = "GPR9 General Purpose Register"]
23 pub GPR9: crate::RORegister<u32>,
24 #[doc = "GPR10 General Purpose Register"]
25 pub GPR10: crate::RWRegister<u32>,
26 #[doc = "GPR11 General Purpose Register"]
27 pub GPR11: crate::RWRegister<u32>,
28 #[doc = "GPR12 General Purpose Register"]
29 pub GPR12: crate::RWRegister<u32>,
30 #[doc = "GPR13 General Purpose Register"]
31 pub GPR13: crate::RWRegister<u32>,
32 #[doc = "GPR14 General Purpose Register"]
33 pub GPR14: crate::RWRegister<u32>,
34 #[doc = "GPR15 General Purpose Register"]
35 pub GPR15: crate::RORegister<u32>,
36 #[doc = "GPR16 General Purpose Register"]
37 pub GPR16: crate::RWRegister<u32>,
38 #[doc = "GPR17 General Purpose Register"]
39 pub GPR17: crate::RWRegister<u32>,
40 #[doc = "GPR18 General Purpose Register"]
41 pub GPR18: crate::RWRegister<u32>,
42 #[doc = "GPR19 General Purpose Register"]
43 pub GPR19: crate::RWRegister<u32>,
44 #[doc = "GPR20 General Purpose Register"]
45 pub GPR20: crate::RWRegister<u32>,
46 #[doc = "GPR21 General Purpose Register"]
47 pub GPR21: crate::RWRegister<u32>,
48 #[doc = "GPR22 General Purpose Register"]
49 pub GPR22: crate::RWRegister<u32>,
50 #[doc = "GPR23 General Purpose Register"]
51 pub GPR23: crate::RWRegister<u32>,
52 #[doc = "GPR24 General Purpose Register"]
53 pub GPR24: crate::RWRegister<u32>,
54 #[doc = "GPR25 General Purpose Register"]
55 pub GPR25: crate::RWRegister<u32>,
56 #[doc = "GPR26 General Purpose Register"]
57 pub GPR26: crate::RWRegister<u32>,
58 #[doc = "GPR27 General Purpose Register"]
59 pub GPR27: crate::RWRegister<u32>,
60 #[doc = "GPR28 General Purpose Register"]
61 pub GPR28: crate::RWRegister<u32>,
62 #[doc = "GPR29 General Purpose Register"]
63 pub GPR29: crate::RWRegister<u32>,
64}
65#[doc = "GPR1 General Purpose Register"]
66pub mod GPR1 {
67 #[doc = "SAI1 MCLK1 source select"]
68 pub mod SAI1_MCLK1_SEL {
69 pub const offset: u32 = 0;
70 pub const mask: u32 = 0x07 << offset;
71 pub mod R {}
72 pub mod W {}
73 pub mod RW {
74 #[doc = "ccm.ssi1_clk_root"]
75 pub const SAI1_MCLK1_SEL_0: u32 = 0;
76 #[doc = "ccm.ssi3_clk_root"]
77 pub const SAI1_MCLK1_SEL_2: u32 = 0x02;
78 #[doc = "iomux.sai1_ipg_clk_sai_mclk"]
79 pub const SAI1_MCLK1_SEL_3: u32 = 0x03;
80 #[doc = "iomux.sai3_ipg_clk_sai_mclk"]
81 pub const SAI1_MCLK1_SEL_5: u32 = 0x05;
82 }
83 }
84 #[doc = "SAI1 MCLK2 source select"]
85 pub mod SAI1_MCLK2_SEL {
86 pub const offset: u32 = 3;
87 pub const mask: u32 = 0x07 << offset;
88 pub mod R {}
89 pub mod W {}
90 pub mod RW {
91 #[doc = "ccm.ssi1_clk_root"]
92 pub const SAI1_MCLK2_SEL_0: u32 = 0;
93 #[doc = "ccm.ssi3_clk_root"]
94 pub const SAI1_MCLK2_SEL_2: u32 = 0x02;
95 #[doc = "iomux.sai1_ipg_clk_sai_mclk"]
96 pub const SAI1_MCLK2_SEL_3: u32 = 0x03;
97 #[doc = "iomux.sai3_ipg_clk_sai_mclk"]
98 pub const SAI1_MCLK2_SEL_5: u32 = 0x05;
99 }
100 }
101 #[doc = "SAI1 MCLK3 source select"]
102 pub mod SAI1_MCLK3_SEL {
103 pub const offset: u32 = 6;
104 pub const mask: u32 = 0x03 << offset;
105 pub mod R {}
106 pub mod W {}
107 pub mod RW {
108 #[doc = "ccm.spdif0_clk_root"]
109 pub const SAI1_MCLK3_SEL_0: u32 = 0;
110 #[doc = "SPDIF_EXT_CLK"]
111 pub const SAI1_MCLK3_SEL_1: u32 = 0x01;
112 #[doc = "spdif.spdif_srclk"]
113 pub const SAI1_MCLK3_SEL_2: u32 = 0x02;
114 #[doc = "spdif.spdif_outclock"]
115 pub const SAI1_MCLK3_SEL_3: u32 = 0x03;
116 }
117 }
118 #[doc = "SAI3 MCLK3 source select"]
119 pub mod SAI3_MCLK3_SEL {
120 pub const offset: u32 = 10;
121 pub const mask: u32 = 0x03 << offset;
122 pub mod R {}
123 pub mod W {}
124 pub mod RW {
125 #[doc = "ccm.spdif0_clk_root"]
126 pub const SAI3_MCLK3_SEL_0: u32 = 0;
127 #[doc = "SPDIF_EXT_CLK"]
128 pub const SAI3_MCLK3_SEL_1: u32 = 0x01;
129 #[doc = "spdif.spdif_srclk"]
130 pub const SAI3_MCLK3_SEL_2: u32 = 0x02;
131 #[doc = "spdif.spdif_outclock"]
132 pub const SAI3_MCLK3_SEL_3: u32 = 0x03;
133 }
134 }
135 #[doc = "Global Interrupt"]
136 pub mod GINT {
137 pub const offset: u32 = 12;
138 pub const mask: u32 = 0x01 << offset;
139 pub mod R {}
140 pub mod W {}
141 pub mod RW {
142 #[doc = "Global interrupt request is not asserted."]
143 pub const GINT_0: u32 = 0;
144 #[doc = "Global interrupt request is asserted."]
145 pub const GINT_1: u32 = 0x01;
146 }
147 }
148 #[doc = "sai1.MCLK signal direction control"]
149 pub mod SAI1_MCLK_DIR {
150 pub const offset: u32 = 19;
151 pub const mask: u32 = 0x01 << offset;
152 pub mod R {}
153 pub mod W {}
154 pub mod RW {
155 #[doc = "sai1.MCLK is input signal"]
156 pub const SAI1_MCLK_DIR_0: u32 = 0;
157 #[doc = "sai1.MCLK is output signal"]
158 pub const SAI1_MCLK_DIR_1: u32 = 0x01;
159 }
160 }
161 #[doc = "sai3.MCLK signal direction control"]
162 pub mod SAI3_MCLK_DIR {
163 pub const offset: u32 = 21;
164 pub const mask: u32 = 0x01 << offset;
165 pub mod R {}
166 pub mod W {}
167 pub mod RW {
168 #[doc = "sai3.MCLK is input signal"]
169 pub const SAI3_MCLK_DIR_0: u32 = 0;
170 #[doc = "sai3.MCLK is output signal"]
171 pub const SAI3_MCLK_DIR_1: u32 = 0x01;
172 }
173 }
174 #[doc = "Exclusive monitor response select of illegal command"]
175 pub mod EXC_MON {
176 pub const offset: u32 = 22;
177 pub const mask: u32 = 0x01 << offset;
178 pub mod R {}
179 pub mod W {}
180 pub mod RW {
181 #[doc = "OKAY response"]
182 pub const EXC_MON_0: u32 = 0;
183 #[doc = "SLVError response"]
184 pub const EXC_MON_1: u32 = 0x01;
185 }
186 }
187 #[doc = "ARM CM7 platform AHB clock enable"]
188 pub mod CM7_FORCE_HCLK_EN {
189 pub const offset: u32 = 31;
190 pub const mask: u32 = 0x01 << offset;
191 pub mod R {}
192 pub mod W {}
193 pub mod RW {
194 #[doc = "AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible."]
195 pub const CM7_FORCE_HCLK_EN_0: u32 = 0;
196 #[doc = "AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible."]
197 pub const CM7_FORCE_HCLK_EN_1: u32 = 0x01;
198 }
199 }
200}
201#[doc = "GPR2 General Purpose Register"]
202pub mod GPR2 {
203 #[doc = "AXBS_P M0 master has higher priority.Do not set both M1 and M0 to high priority."]
204 pub mod AXBS_P_M0_HIGH_PRIORITY {
205 pub const offset: u32 = 3;
206 pub const mask: u32 = 0x01 << offset;
207 pub mod R {}
208 pub mod W {}
209 pub mod RW {
210 #[doc = "AXBS_P M0 master doesn't have high priority"]
211 pub const AXBS_P_M0_HIGH_PRIORITY_0: u32 = 0;
212 #[doc = "AXBS_P M0 master has high priority"]
213 pub const AXBS_P_M0_HIGH_PRIORITY_1: u32 = 0x01;
214 }
215 }
216 #[doc = "AXBS_P M1 master has higher priority.Do not set both M1 and M0 to high priority."]
217 pub mod AXBS_P_M1_HIGH_PRIORITY {
218 pub const offset: u32 = 4;
219 pub const mask: u32 = 0x01 << offset;
220 pub mod R {}
221 pub mod W {}
222 pub mod RW {
223 #[doc = "AXBS_P M1 master does not have high priority"]
224 pub const AXBS_P_M1_HIGH_PRIORITY_0: u32 = 0;
225 #[doc = "AXBS_P M1 master has high priority"]
226 pub const AXBS_P_M1_HIGH_PRIORITY_1: u32 = 0x01;
227 }
228 }
229 #[doc = "Force Round Robin in AXBS_P. This bit can override master M0 M1 high priority configuration."]
230 pub mod AXBS_P_FORCE_ROUND_ROBIN {
231 pub const offset: u32 = 5;
232 pub const mask: u32 = 0x01 << offset;
233 pub mod R {}
234 pub mod W {}
235 pub mod RW {
236 #[doc = "AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings."]
237 pub const AXBS_P_FORCE_ROUND_ROBIN_0: u32 = 0;
238 #[doc = "AXBS_P masters are arbitored in round robin"]
239 pub const AXBS_P_FORCE_ROUND_ROBIN_1: u32 = 0x01;
240 }
241 }
242 #[doc = "Enable power saving features on L2 memory"]
243 pub mod L2_MEM_EN_POWERSAVING {
244 pub const offset: u32 = 12;
245 pub const mask: u32 = 0x01 << offset;
246 pub mod R {}
247 pub mod W {}
248 pub mod RW {
249 #[doc = "Enters power saving mode only when chip is in SUSPEND mode"]
250 pub const L2_MEM_EN_POWERSAVING_0: u32 = 0;
251 #[doc = "Controlled by L2_MEM_DEEPSLEEP bitfield"]
252 pub const L2_MEM_EN_POWERSAVING_1: u32 = 0x01;
253 }
254 }
255 #[doc = "Automatically gate off RAM clock when RAM is not accessed."]
256 pub mod RAM_AUTO_CLK_GATING_EN {
257 pub const offset: u32 = 13;
258 pub const mask: u32 = 0x01 << offset;
259 pub mod R {}
260 pub mod W {}
261 pub mod RW {
262 #[doc = "disable automatically gate off RAM clock"]
263 pub const RAM_AUTO_CLK_GATING_EN_0: u32 = 0;
264 #[doc = "enable automatically gate off RAM clock"]
265 pub const RAM_AUTO_CLK_GATING_EN_1: u32 = 0x01;
266 }
267 }
268 #[doc = "This bit controls how memory (OCRAM) enters Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low"]
269 pub mod L2_MEM_DEEPSLEEP {
270 pub const offset: u32 = 14;
271 pub const mask: u32 = 0x01 << offset;
272 pub mod R {}
273 pub mod W {}
274 pub mod RW {
275 #[doc = "No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)"]
276 pub const L2_MEM_DEEPSLEEP_0: u32 = 0;
277 #[doc = "Force memory into deep sleep mode (OCRAM in power saving mode)"]
278 pub const L2_MEM_DEEPSLEEP_1: u32 = 0x01;
279 }
280 }
281 #[doc = "Divider ratio control for mclk from hmclk"]
282 pub mod MQS_CLK_DIV {
283 pub const offset: u32 = 16;
284 pub const mask: u32 = 0xff << offset;
285 pub mod R {}
286 pub mod W {}
287 pub mod RW {
288 #[doc = "mclk frequency = hmclk frequency"]
289 pub const MQS_CLK_DIV_0: u32 = 0;
290 #[doc = "mclk frequency = 1/2 * hmclk frequency"]
291 pub const MQS_CLK_DIV_1: u32 = 0x01;
292 #[doc = "mclk frequency = 1/3 * hmclk frequency"]
293 pub const MQS_CLK_DIV_2: u32 = 0x02;
294 #[doc = "mclk frequency = 1/256 * hmclk frequency"]
295 pub const MQS_CLK_DIV_255: u32 = 0xff;
296 }
297 }
298 #[doc = "MQS software reset"]
299 pub mod MQS_SW_RST {
300 pub const offset: u32 = 24;
301 pub const mask: u32 = 0x01 << offset;
302 pub mod R {}
303 pub mod W {}
304 pub mod RW {
305 #[doc = "Exit software reset for MQS"]
306 pub const MQS_SW_RST_0: u32 = 0;
307 #[doc = "Enable software reset for MQS"]
308 pub const MQS_SW_RST_1: u32 = 0x01;
309 }
310 }
311 #[doc = "MQS enable."]
312 pub mod MQS_EN {
313 pub const offset: u32 = 25;
314 pub const mask: u32 = 0x01 << offset;
315 pub mod R {}
316 pub mod W {}
317 pub mod RW {
318 #[doc = "Disable MQS"]
319 pub const MQS_EN_0: u32 = 0;
320 #[doc = "Enable MQS"]
321 pub const MQS_EN_1: u32 = 0x01;
322 }
323 }
324 #[doc = "Medium Quality Sound (MQS) Oversample"]
325 pub mod MQS_OVERSAMPLE {
326 pub const offset: u32 = 26;
327 pub const mask: u32 = 0x01 << offset;
328 pub mod R {}
329 pub mod W {}
330 pub mod RW {
331 #[doc = "32"]
332 pub const MQS_OVERSAMPLE_0: u32 = 0;
333 #[doc = "64"]
334 pub const MQS_OVERSAMPLE_1: u32 = 0x01;
335 }
336 }
337}
338#[doc = "GPR3 General Purpose Register"]
339pub mod GPR3 {
340 #[doc = "Select 128-bit DCP key from 256-bit key from SNVS Master Key"]
341 pub mod DCP_KEY_SEL {
342 pub const offset: u32 = 4;
343 pub const mask: u32 = 0x01 << offset;
344 pub mod R {}
345 pub mod W {}
346 pub mod RW {
347 #[doc = "Select \\[127:0\\] from SNVS Master Key as DCP key"]
348 pub const DCP_KEY_SEL_0: u32 = 0;
349 #[doc = "Select \\[255:128\\] from SNVS Master Key as DCP key"]
350 pub const DCP_KEY_SEL_1: u32 = 0x01;
351 }
352 }
353}
354#[doc = "GPR4 General Purpose Register"]
355pub mod GPR4 {
356 #[doc = "EDMA stop request."]
357 pub mod EDMA_STOP_REQ {
358 pub const offset: u32 = 0;
359 pub const mask: u32 = 0x01 << offset;
360 pub mod R {}
361 pub mod W {}
362 pub mod RW {
363 #[doc = "stop request off"]
364 pub const EDMA_STOP_REQ_0: u32 = 0;
365 #[doc = "stop request on"]
366 pub const EDMA_STOP_REQ_1: u32 = 0x01;
367 }
368 }
369 #[doc = "TRNG stop request."]
370 pub mod TRNG_STOP_REQ {
371 pub const offset: u32 = 3;
372 pub const mask: u32 = 0x01 << offset;
373 pub mod R {}
374 pub mod W {}
375 pub mod RW {
376 #[doc = "stop request off"]
377 pub const TRNG_STOP_REQ_0: u32 = 0;
378 #[doc = "stop request on"]
379 pub const TRNG_STOP_REQ_1: u32 = 0x01;
380 }
381 }
382 #[doc = "SAI1 stop request."]
383 pub mod SAI1_STOP_REQ {
384 pub const offset: u32 = 5;
385 pub const mask: u32 = 0x01 << offset;
386 pub mod R {}
387 pub mod W {}
388 pub mod RW {
389 #[doc = "stop request off"]
390 pub const SAI1_STOP_REQ_0: u32 = 0;
391 #[doc = "stop request on"]
392 pub const SAI1_STOP_REQ_1: u32 = 0x01;
393 }
394 }
395 #[doc = "SAI3 stop request."]
396 pub mod SAI3_STOP_REQ {
397 pub const offset: u32 = 7;
398 pub const mask: u32 = 0x01 << offset;
399 pub mod R {}
400 pub mod W {}
401 pub mod RW {
402 #[doc = "stop request off"]
403 pub const SAI3_STOP_REQ_0: u32 = 0;
404 #[doc = "stop request on"]
405 pub const SAI3_STOP_REQ_1: u32 = 0x01;
406 }
407 }
408 #[doc = "PIT stop request."]
409 pub mod PIT_STOP_REQ {
410 pub const offset: u32 = 10;
411 pub const mask: u32 = 0x01 << offset;
412 pub mod R {}
413 pub mod W {}
414 pub mod RW {
415 #[doc = "stop request off"]
416 pub const PIT_STOP_REQ_0: u32 = 0;
417 #[doc = "stop request on"]
418 pub const PIT_STOP_REQ_1: u32 = 0x01;
419 }
420 }
421 #[doc = "FlexSPI stop request."]
422 pub mod FLEXSPI_STOP_REQ {
423 pub const offset: u32 = 11;
424 pub const mask: u32 = 0x01 << offset;
425 pub mod R {}
426 pub mod W {}
427 pub mod RW {
428 #[doc = "stop request off"]
429 pub const FLEXSPI_STOP_REQ_0: u32 = 0;
430 #[doc = "stop request on"]
431 pub const FLEXSPI_STOP_REQ_1: u32 = 0x01;
432 }
433 }
434 #[doc = "FlexIO1 stop request."]
435 pub mod FLEXIO1_STOP_REQ {
436 pub const offset: u32 = 12;
437 pub const mask: u32 = 0x01 << offset;
438 pub mod R {}
439 pub mod W {}
440 pub mod RW {
441 #[doc = "stop request off"]
442 pub const FLEXIO1_STOP_REQ_0: u32 = 0;
443 #[doc = "stop request on"]
444 pub const FLEXIO1_STOP_REQ_1: u32 = 0x01;
445 }
446 }
447 #[doc = "EDMA stop acknowledge. This is a status (read-only) bit"]
448 pub mod EDMA_STOP_ACK {
449 pub const offset: u32 = 16;
450 pub const mask: u32 = 0x01 << offset;
451 pub mod R {}
452 pub mod W {}
453 pub mod RW {
454 #[doc = "EDMA stop acknowledge is not asserted"]
455 pub const EDMA_STOP_ACK_0: u32 = 0;
456 #[doc = "EDMA stop acknowledge is asserted (EDMA is in STOP mode)."]
457 pub const EDMA_STOP_ACK_1: u32 = 0x01;
458 }
459 }
460 #[doc = "TRNG stop acknowledge"]
461 pub mod TRNG_STOP_ACK {
462 pub const offset: u32 = 19;
463 pub const mask: u32 = 0x01 << offset;
464 pub mod R {}
465 pub mod W {}
466 pub mod RW {
467 #[doc = "TRNG stop acknowledge is not asserted"]
468 pub const TRNG_STOP_ACK_0: u32 = 0;
469 #[doc = "TRNG stop acknowledge is asserted"]
470 pub const TRNG_STOP_ACK_1: u32 = 0x01;
471 }
472 }
473 #[doc = "SAI1 stop acknowledge"]
474 pub mod SAI1_STOP_ACK {
475 pub const offset: u32 = 21;
476 pub const mask: u32 = 0x01 << offset;
477 pub mod R {}
478 pub mod W {}
479 pub mod RW {
480 #[doc = "SAI1 stop acknowledge is not asserted"]
481 pub const SAI1_STOP_ACK_0: u32 = 0;
482 #[doc = "SAI1 stop acknowledge is asserted"]
483 pub const SAI1_STOP_ACK_1: u32 = 0x01;
484 }
485 }
486 #[doc = "SAI3 stop acknowledge"]
487 pub mod SAI3_STOP_ACK {
488 pub const offset: u32 = 23;
489 pub const mask: u32 = 0x01 << offset;
490 pub mod R {}
491 pub mod W {}
492 pub mod RW {
493 #[doc = "SAI3 stop acknowledge is not asserted"]
494 pub const SAI3_STOP_ACK_0: u32 = 0;
495 #[doc = "SAI3 stop acknowledge is asserted"]
496 pub const SAI3_STOP_ACK_1: u32 = 0x01;
497 }
498 }
499 #[doc = "PIT stop acknowledge"]
500 pub mod PIT_STOP_ACK {
501 pub const offset: u32 = 26;
502 pub const mask: u32 = 0x01 << offset;
503 pub mod R {}
504 pub mod W {}
505 pub mod RW {
506 #[doc = "PIT stop acknowledge is not asserted"]
507 pub const PIT_STOP_ACK_0: u32 = 0;
508 #[doc = "PIT stop acknowledge is asserted"]
509 pub const PIT_STOP_ACK_1: u32 = 0x01;
510 }
511 }
512 #[doc = "FLEXSPI stop acknowledge"]
513 pub mod FLEXSPI_STOP_ACK {
514 pub const offset: u32 = 27;
515 pub const mask: u32 = 0x01 << offset;
516 pub mod R {}
517 pub mod W {}
518 pub mod RW {
519 #[doc = "FLEXSPI stop acknowledge is not asserted"]
520 pub const FLEXSPI_STOP_ACK_0: u32 = 0;
521 #[doc = "FLEXSPI stop acknowledge is asserted"]
522 pub const FLEXSPI_STOP_ACK_1: u32 = 0x01;
523 }
524 }
525 #[doc = "FLEXIO1 stop acknowledge"]
526 pub mod FLEXIO1_STOP_ACK {
527 pub const offset: u32 = 28;
528 pub const mask: u32 = 0x01 << offset;
529 pub mod R {}
530 pub mod W {}
531 pub mod RW {
532 #[doc = "FLEXIO1 stop acknowledge is not asserted"]
533 pub const FLEXIO1_STOP_ACK_0: u32 = 0;
534 #[doc = "FLEXIO1 stop acknowledge is asserted"]
535 pub const FLEXIO1_STOP_ACK_1: u32 = 0x01;
536 }
537 }
538}
539#[doc = "GPR5 General Purpose Register"]
540pub mod GPR5 {
541 #[doc = "WDOG1 Timeout Mask"]
542 pub mod WDOG1_MASK {
543 pub const offset: u32 = 6;
544 pub const mask: u32 = 0x01 << offset;
545 pub mod R {}
546 pub mod W {}
547 pub mod RW {
548 #[doc = "WDOG1 Timeout behaves normally"]
549 pub const WDOG1_MASK_0: u32 = 0;
550 #[doc = "WDOG1 Timeout is masked"]
551 pub const WDOG1_MASK_1: u32 = 0x01;
552 }
553 }
554 #[doc = "WDOG2 Timeout Mask"]
555 pub mod WDOG2_MASK {
556 pub const offset: u32 = 7;
557 pub const mask: u32 = 0x01 << offset;
558 pub mod R {}
559 pub mod W {}
560 pub mod RW {
561 #[doc = "WDOG2 Timeout behaves normally"]
562 pub const WDOG2_MASK_0: u32 = 0;
563 #[doc = "WDOG2 Timeout is masked"]
564 pub const WDOG2_MASK_1: u32 = 0x01;
565 }
566 }
567 #[doc = "GPT1 1 MHz clock source select"]
568 pub mod VREF_1M_CLK_GPT1 {
569 pub const offset: u32 = 28;
570 pub const mask: u32 = 0x01 << offset;
571 pub mod R {}
572 pub mod W {}
573 pub mod RW {
574 #[doc = "GPT1 ipg_clk_highfreq driven by IPG_PERCLK"]
575 pub const VREF_1M_CLK_GPT1_0: u32 = 0;
576 #[doc = "GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock"]
577 pub const VREF_1M_CLK_GPT1_1: u32 = 0x01;
578 }
579 }
580 #[doc = "GPT2 1 MHz clock source select"]
581 pub mod VREF_1M_CLK_GPT2 {
582 pub const offset: u32 = 29;
583 pub const mask: u32 = 0x01 << offset;
584 pub mod R {}
585 pub mod W {}
586 pub mod RW {
587 #[doc = "GPT2 ipg_clk_highfreq driven by IPG_PERCLK"]
588 pub const VREF_1M_CLK_GPT2_0: u32 = 0;
589 #[doc = "GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock"]
590 pub const VREF_1M_CLK_GPT2_1: u32 = 0x01;
591 }
592 }
593}
594#[doc = "GPR6 General Purpose Register"]
595pub mod GPR6 {
596 #[doc = "IOMUXC XBAR_INOUT2 function direction select"]
597 pub mod IOMUXC_XBAR_DIR_SEL_2 {
598 pub const offset: u32 = 16;
599 pub const mask: u32 = 0x01 << offset;
600 pub mod R {}
601 pub mod W {}
602 pub mod RW {
603 #[doc = "XBAR_INOUT as input"]
604 pub const IOMUXC_XBAR_DIR_SEL_2_0: u32 = 0;
605 #[doc = "XBAR_INOUT as output"]
606 pub const IOMUXC_XBAR_DIR_SEL_2_1: u32 = 0x01;
607 }
608 }
609 #[doc = "IOMUXC XBAR_INOUT3 function direction select"]
610 pub mod IOMUXC_XBAR_DIR_SEL_3 {
611 pub const offset: u32 = 17;
612 pub const mask: u32 = 0x01 << offset;
613 pub mod R {}
614 pub mod W {}
615 pub mod RW {
616 #[doc = "XBAR_INOUT as input"]
617 pub const IOMUXC_XBAR_DIR_SEL_3_0: u32 = 0;
618 #[doc = "XBAR_INOUT as output"]
619 pub const IOMUXC_XBAR_DIR_SEL_3_1: u32 = 0x01;
620 }
621 }
622}
623#[doc = "GPR7 General Purpose Register"]
624pub mod GPR7 {
625 #[doc = "LPI2C1 stop request"]
626 pub mod LPI2C1_STOP_REQ {
627 pub const offset: u32 = 0;
628 pub const mask: u32 = 0x01 << offset;
629 pub mod R {}
630 pub mod W {}
631 pub mod RW {
632 #[doc = "stop request off"]
633 pub const LPI2C1_STOP_REQ_0: u32 = 0;
634 #[doc = "stop request on"]
635 pub const LPI2C1_STOP_REQ_1: u32 = 0x01;
636 }
637 }
638 #[doc = "LPI2C2 stop request"]
639 pub mod LPI2C2_STOP_REQ {
640 pub const offset: u32 = 1;
641 pub const mask: u32 = 0x01 << offset;
642 pub mod R {}
643 pub mod W {}
644 pub mod RW {
645 #[doc = "stop request off"]
646 pub const LPI2C2_STOP_REQ_0: u32 = 0;
647 #[doc = "stop request on"]
648 pub const LPI2C2_STOP_REQ_1: u32 = 0x01;
649 }
650 }
651 #[doc = "LPSPI1 stop request"]
652 pub mod LPSPI1_STOP_REQ {
653 pub const offset: u32 = 4;
654 pub const mask: u32 = 0x01 << offset;
655 pub mod R {}
656 pub mod W {}
657 pub mod RW {
658 #[doc = "stop request off"]
659 pub const LPSPI1_STOP_REQ_0: u32 = 0;
660 #[doc = "stop request on"]
661 pub const LPSPI1_STOP_REQ_1: u32 = 0x01;
662 }
663 }
664 #[doc = "LPSPI2 stop request"]
665 pub mod LPSPI2_STOP_REQ {
666 pub const offset: u32 = 5;
667 pub const mask: u32 = 0x01 << offset;
668 pub mod R {}
669 pub mod W {}
670 pub mod RW {
671 #[doc = "stop request off"]
672 pub const LPSPI2_STOP_REQ_0: u32 = 0;
673 #[doc = "stop request on"]
674 pub const LPSPI2_STOP_REQ_1: u32 = 0x01;
675 }
676 }
677 #[doc = "LPUART1 stop request"]
678 pub mod LPUART1_STOP_REQ {
679 pub const offset: u32 = 8;
680 pub const mask: u32 = 0x01 << offset;
681 pub mod R {}
682 pub mod W {}
683 pub mod RW {
684 #[doc = "stop request off"]
685 pub const LPUART1_STOP_REQ_0: u32 = 0;
686 #[doc = "stop request on"]
687 pub const LPUART1_STOP_REQ_1: u32 = 0x01;
688 }
689 }
690 #[doc = "LPUART1 stop request"]
691 pub mod LPUART2_STOP_REQ {
692 pub const offset: u32 = 9;
693 pub const mask: u32 = 0x01 << offset;
694 pub mod R {}
695 pub mod W {}
696 pub mod RW {
697 #[doc = "stop request off"]
698 pub const LPUART2_STOP_REQ_0: u32 = 0;
699 #[doc = "stop request on"]
700 pub const LPUART2_STOP_REQ_1: u32 = 0x01;
701 }
702 }
703 #[doc = "LPUART3 stop request"]
704 pub mod LPUART3_STOP_REQ {
705 pub const offset: u32 = 10;
706 pub const mask: u32 = 0x01 << offset;
707 pub mod R {}
708 pub mod W {}
709 pub mod RW {
710 #[doc = "stop request off"]
711 pub const LPUART3_STOP_REQ_0: u32 = 0;
712 #[doc = "stop request on"]
713 pub const LPUART3_STOP_REQ_1: u32 = 0x01;
714 }
715 }
716 #[doc = "LPUART4 stop request"]
717 pub mod LPUART4_STOP_REQ {
718 pub const offset: u32 = 11;
719 pub const mask: u32 = 0x01 << offset;
720 pub mod R {}
721 pub mod W {}
722 pub mod RW {
723 #[doc = "stop request off"]
724 pub const LPUART4_STOP_REQ_0: u32 = 0;
725 #[doc = "stop request on"]
726 pub const LPUART4_STOP_REQ_1: u32 = 0x01;
727 }
728 }
729 #[doc = "LPI2C1 stop acknowledge"]
730 pub mod LPI2C1_STOP_ACK {
731 pub const offset: u32 = 16;
732 pub const mask: u32 = 0x01 << offset;
733 pub mod R {}
734 pub mod W {}
735 pub mod RW {
736 #[doc = "stop acknowledge is not asserted"]
737 pub const LPI2C1_STOP_ACK_0: u32 = 0;
738 #[doc = "stop acknowledge is asserted (the module is in Stop mode)"]
739 pub const LPI2C1_STOP_ACK_1: u32 = 0x01;
740 }
741 }
742 #[doc = "LPI2C2 stop acknowledge"]
743 pub mod LPI2C2_STOP_ACK {
744 pub const offset: u32 = 17;
745 pub const mask: u32 = 0x01 << offset;
746 pub mod R {}
747 pub mod W {}
748 pub mod RW {
749 #[doc = "stop acknowledge is not asserted"]
750 pub const LPI2C2_STOP_ACK_0: u32 = 0;
751 #[doc = "stop acknowledge is asserted"]
752 pub const LPI2C2_STOP_ACK_1: u32 = 0x01;
753 }
754 }
755 #[doc = "LPSPI1 stop acknowledge"]
756 pub mod LPSPI1_STOP_ACK {
757 pub const offset: u32 = 20;
758 pub const mask: u32 = 0x01 << offset;
759 pub mod R {}
760 pub mod W {}
761 pub mod RW {
762 #[doc = "stop acknowledge is not asserted"]
763 pub const LPSPI1_STOP_ACK_0: u32 = 0;
764 #[doc = "stop acknowledge is asserted"]
765 pub const LPSPI1_STOP_ACK_1: u32 = 0x01;
766 }
767 }
768 #[doc = "LPSPI2 stop acknowledge"]
769 pub mod LPSPI2_STOP_ACK {
770 pub const offset: u32 = 21;
771 pub const mask: u32 = 0x01 << offset;
772 pub mod R {}
773 pub mod W {}
774 pub mod RW {
775 #[doc = "stop acknowledge is not asserted"]
776 pub const LPSPI2_STOP_ACK_0: u32 = 0;
777 #[doc = "stop acknowledge is asserted"]
778 pub const LPSPI2_STOP_ACK_1: u32 = 0x01;
779 }
780 }
781 #[doc = "LPUART1 stop acknowledge"]
782 pub mod LPUART1_STOP_ACK {
783 pub const offset: u32 = 24;
784 pub const mask: u32 = 0x01 << offset;
785 pub mod R {}
786 pub mod W {}
787 pub mod RW {
788 #[doc = "stop acknowledge is not asserted"]
789 pub const LPUART1_STOP_ACK_0: u32 = 0;
790 #[doc = "stop acknowledge is asserted"]
791 pub const LPUART1_STOP_ACK_1: u32 = 0x01;
792 }
793 }
794 #[doc = "LPUART1 stop acknowledge"]
795 pub mod LPUART2_STOP_ACK {
796 pub const offset: u32 = 25;
797 pub const mask: u32 = 0x01 << offset;
798 pub mod R {}
799 pub mod W {}
800 pub mod RW {
801 #[doc = "stop acknowledge is not asserted"]
802 pub const LPUART2_STOP_ACK_0: u32 = 0;
803 #[doc = "stop acknowledge is asserted"]
804 pub const LPUART2_STOP_ACK_1: u32 = 0x01;
805 }
806 }
807 #[doc = "LPUART3 stop acknowledge"]
808 pub mod LPUART3_STOP_ACK {
809 pub const offset: u32 = 26;
810 pub const mask: u32 = 0x01 << offset;
811 pub mod R {}
812 pub mod W {}
813 pub mod RW {
814 #[doc = "stop acknowledge is not asserted"]
815 pub const LPUART3_STOP_ACK_0: u32 = 0;
816 #[doc = "stop acknowledge is asserted"]
817 pub const LPUART3_STOP_ACK_1: u32 = 0x01;
818 }
819 }
820 #[doc = "LPUART4 stop acknowledge"]
821 pub mod LPUART4_STOP_ACK {
822 pub const offset: u32 = 27;
823 pub const mask: u32 = 0x01 << offset;
824 pub mod R {}
825 pub mod W {}
826 pub mod RW {
827 #[doc = "stop acknowledge is not asserted"]
828 pub const LPUART4_STOP_ACK_0: u32 = 0;
829 #[doc = "stop acknowledge is asserted"]
830 pub const LPUART4_STOP_ACK_1: u32 = 0x01;
831 }
832 }
833}
834#[doc = "GPR8 General Purpose Register"]
835pub mod GPR8 {
836 #[doc = "LPI2C1 stop mode selection, cannot change when ipg_stop is asserted."]
837 pub mod LPI2C1_IPG_STOP_MODE {
838 pub const offset: u32 = 0;
839 pub const mask: u32 = 0x01 << offset;
840 pub mod R {}
841 pub mod W {}
842 pub mod RW {
843 #[doc = "the module is functional in Stop mode"]
844 pub const LPI2C1_IPG_STOP_MODE_0: u32 = 0;
845 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
846 pub const LPI2C1_IPG_STOP_MODE_1: u32 = 0x01;
847 }
848 }
849 #[doc = "LPI2C1 ipg_doze mode"]
850 pub mod LPI2C1_IPG_DOZE {
851 pub const offset: u32 = 1;
852 pub const mask: u32 = 0x01 << offset;
853 pub mod R {}
854 pub mod W {}
855 pub mod RW {
856 #[doc = "not in doze mode"]
857 pub const LPI2C1_IPG_DOZE_0: u32 = 0;
858 #[doc = "in doze mode"]
859 pub const LPI2C1_IPG_DOZE_1: u32 = 0x01;
860 }
861 }
862 #[doc = "LPI2C2 stop mode selection, cannot change when ipg_stop is asserted."]
863 pub mod LPI2C2_IPG_STOP_MODE {
864 pub const offset: u32 = 2;
865 pub const mask: u32 = 0x01 << offset;
866 pub mod R {}
867 pub mod W {}
868 pub mod RW {
869 #[doc = "the module is functional in Stop mode"]
870 pub const LPI2C2_IPG_STOP_MODE_0: u32 = 0;
871 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
872 pub const LPI2C2_IPG_STOP_MODE_1: u32 = 0x01;
873 }
874 }
875 #[doc = "LPI2C2 ipg_doze mode"]
876 pub mod LPI2C2_IPG_DOZE {
877 pub const offset: u32 = 3;
878 pub const mask: u32 = 0x01 << offset;
879 pub mod R {}
880 pub mod W {}
881 pub mod RW {
882 #[doc = "not in doze mode"]
883 pub const LPI2C2_IPG_DOZE_0: u32 = 0;
884 #[doc = "in doze mode"]
885 pub const LPI2C2_IPG_DOZE_1: u32 = 0x01;
886 }
887 }
888 #[doc = "LPSPI1 stop mode selection, cannot change when ipg_stop is asserted."]
889 pub mod LPSPI1_IPG_STOP_MODE {
890 pub const offset: u32 = 8;
891 pub const mask: u32 = 0x01 << offset;
892 pub mod R {}
893 pub mod W {}
894 pub mod RW {
895 #[doc = "the module is functional in Stop mode"]
896 pub const LPSPI1_IPG_STOP_MODE_0: u32 = 0;
897 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
898 pub const LPSPI1_IPG_STOP_MODE_1: u32 = 0x01;
899 }
900 }
901 #[doc = "LPSPI1 ipg_doze mode"]
902 pub mod LPSPI1_IPG_DOZE {
903 pub const offset: u32 = 9;
904 pub const mask: u32 = 0x01 << offset;
905 pub mod R {}
906 pub mod W {}
907 pub mod RW {
908 #[doc = "not in doze mode"]
909 pub const LPSPI1_IPG_DOZE_0: u32 = 0;
910 #[doc = "in doze mode"]
911 pub const LPSPI1_IPG_DOZE_1: u32 = 0x01;
912 }
913 }
914 #[doc = "LPSPI2 stop mode selection, cannot change when ipg_stop is asserted."]
915 pub mod LPSPI2_IPG_STOP_MODE {
916 pub const offset: u32 = 10;
917 pub const mask: u32 = 0x01 << offset;
918 pub mod R {}
919 pub mod W {}
920 pub mod RW {
921 #[doc = "the module is functional in Stop mode"]
922 pub const LPSPI2_IPG_STOP_MODE_0: u32 = 0;
923 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
924 pub const LPSPI2_IPG_STOP_MODE_1: u32 = 0x01;
925 }
926 }
927 #[doc = "LPSPI2 ipg_doze mode"]
928 pub mod LPSPI2_IPG_DOZE {
929 pub const offset: u32 = 11;
930 pub const mask: u32 = 0x01 << offset;
931 pub mod R {}
932 pub mod W {}
933 pub mod RW {
934 #[doc = "not in doze mode"]
935 pub const LPSPI2_IPG_DOZE_0: u32 = 0;
936 #[doc = "in doze mode"]
937 pub const LPSPI2_IPG_DOZE_1: u32 = 0x01;
938 }
939 }
940 #[doc = "LPUART1 stop mode selection, cannot change when ipg_stop is asserted."]
941 pub mod LPUART1_IPG_STOP_MODE {
942 pub const offset: u32 = 16;
943 pub const mask: u32 = 0x01 << offset;
944 pub mod R {}
945 pub mod W {}
946 pub mod RW {
947 #[doc = "the module is functional in Stop mode"]
948 pub const LPUART1_IPG_STOP_MODE_0: u32 = 0;
949 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
950 pub const LPUART1_IPG_STOP_MODE_1: u32 = 0x01;
951 }
952 }
953 #[doc = "LPUART1 ipg_doze mode"]
954 pub mod LPUART1_IPG_DOZE {
955 pub const offset: u32 = 17;
956 pub const mask: u32 = 0x01 << offset;
957 pub mod R {}
958 pub mod W {}
959 pub mod RW {
960 #[doc = "not in doze mode"]
961 pub const LPUART1_IPG_DOZE_0: u32 = 0;
962 #[doc = "in doze mode"]
963 pub const LPUART1_IPG_DOZE_1: u32 = 0x01;
964 }
965 }
966 #[doc = "LPUART2 stop mode selection, cannot change when ipg_stop is asserted."]
967 pub mod LPUART2_IPG_STOP_MODE {
968 pub const offset: u32 = 18;
969 pub const mask: u32 = 0x01 << offset;
970 pub mod R {}
971 pub mod W {}
972 pub mod RW {
973 #[doc = "the module is functional in Stop mode"]
974 pub const LPUART2_IPG_STOP_MODE_0: u32 = 0;
975 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
976 pub const LPUART2_IPG_STOP_MODE_1: u32 = 0x01;
977 }
978 }
979 #[doc = "LPUART2 ipg_doze mode"]
980 pub mod LPUART2_IPG_DOZE {
981 pub const offset: u32 = 19;
982 pub const mask: u32 = 0x01 << offset;
983 pub mod R {}
984 pub mod W {}
985 pub mod RW {
986 #[doc = "not in doze mode"]
987 pub const LPUART2_IPG_DOZE_0: u32 = 0;
988 #[doc = "in doze mode"]
989 pub const LPUART2_IPG_DOZE_1: u32 = 0x01;
990 }
991 }
992 #[doc = "LPUART3 stop mode selection, cannot change when ipg_stop is asserted."]
993 pub mod LPUART3_IPG_STOP_MODE {
994 pub const offset: u32 = 20;
995 pub const mask: u32 = 0x01 << offset;
996 pub mod R {}
997 pub mod W {}
998 pub mod RW {
999 #[doc = "the module is functional in Stop mode"]
1000 pub const LPUART3_IPG_STOP_MODE_0: u32 = 0;
1001 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
1002 pub const LPUART3_IPG_STOP_MODE_1: u32 = 0x01;
1003 }
1004 }
1005 #[doc = "LPUART3 ipg_doze mode"]
1006 pub mod LPUART3_IPG_DOZE {
1007 pub const offset: u32 = 21;
1008 pub const mask: u32 = 0x01 << offset;
1009 pub mod R {}
1010 pub mod W {}
1011 pub mod RW {
1012 #[doc = "not in doze mode"]
1013 pub const LPUART3_IPG_DOZE_0: u32 = 0;
1014 #[doc = "in doze mode"]
1015 pub const LPUART3_IPG_DOZE_1: u32 = 0x01;
1016 }
1017 }
1018 #[doc = "LPUART4 stop mode selection, cannot change when ipg_stop is asserted."]
1019 pub mod LPUART4_IPG_STOP_MODE {
1020 pub const offset: u32 = 22;
1021 pub const mask: u32 = 0x01 << offset;
1022 pub mod R {}
1023 pub mod W {}
1024 pub mod RW {
1025 #[doc = "the module is functional in Stop mode"]
1026 pub const LPUART4_IPG_STOP_MODE_0: u32 = 0;
1027 #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
1028 pub const LPUART4_IPG_STOP_MODE_1: u32 = 0x01;
1029 }
1030 }
1031 #[doc = "LPUART4 ipg_doze mode"]
1032 pub mod LPUART4_IPG_DOZE {
1033 pub const offset: u32 = 23;
1034 pub const mask: u32 = 0x01 << offset;
1035 pub mod R {}
1036 pub mod W {}
1037 pub mod RW {
1038 #[doc = "not in doze mode"]
1039 pub const LPUART4_IPG_DOZE_0: u32 = 0;
1040 #[doc = "in doze mode"]
1041 pub const LPUART4_IPG_DOZE_1: u32 = 0x01;
1042 }
1043 }
1044}
1045#[doc = "GPR10 General Purpose Register"]
1046pub mod GPR10 {
1047 #[doc = "ARM non-secure (non-invasive) debug enable"]
1048 pub mod NIDEN {
1049 pub const offset: u32 = 0;
1050 pub const mask: u32 = 0x01 << offset;
1051 pub mod R {}
1052 pub mod W {}
1053 pub mod RW {
1054 #[doc = "Debug turned off."]
1055 pub const NIDEN_0: u32 = 0;
1056 #[doc = "Debug enabled (default)."]
1057 pub const NIDEN_1: u32 = 0x01;
1058 }
1059 }
1060 #[doc = "ARM invasive debug enable"]
1061 pub mod DBG_EN {
1062 pub const offset: u32 = 1;
1063 pub const mask: u32 = 0x01 << offset;
1064 pub mod R {}
1065 pub mod W {}
1066 pub mod RW {
1067 #[doc = "Debug turned off."]
1068 pub const DBG_EN_0: u32 = 0;
1069 #[doc = "Debug enabled (default)."]
1070 pub const DBG_EN_1: u32 = 0x01;
1071 }
1072 }
1073 #[doc = "Security error response enable for all security gaskets (on both AHB and AXI buses)"]
1074 pub mod SEC_ERR_RESP {
1075 pub const offset: u32 = 2;
1076 pub const mask: u32 = 0x01 << offset;
1077 pub mod R {}
1078 pub mod W {}
1079 pub mod RW {
1080 #[doc = "OKEY response"]
1081 pub const SEC_ERR_RESP_0: u32 = 0;
1082 #[doc = "SLVError (default)"]
1083 pub const SEC_ERR_RESP_1: u32 = 0x01;
1084 }
1085 }
1086 #[doc = "DCP Key selection bit."]
1087 pub mod DCPKEY_OCOTP_OR_KEYMUX {
1088 pub const offset: u32 = 4;
1089 pub const mask: u32 = 0x01 << offset;
1090 pub mod R {}
1091 pub mod W {}
1092 pub mod RW {
1093 #[doc = "Select key from SNVS Master Key."]
1094 pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0;
1095 #[doc = "Select key from OCOTP (SW_GP2)."]
1096 pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01;
1097 }
1098 }
1099 #[doc = "OCRAM TrustZone (TZ) enable."]
1100 pub mod OCRAM_TZ_EN {
1101 pub const offset: u32 = 8;
1102 pub const mask: u32 = 0x01 << offset;
1103 pub mod R {}
1104 pub mod W {}
1105 pub mod RW {
1106 #[doc = "The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor)."]
1107 pub const OCRAM_TZ_EN_0: u32 = 0;
1108 #[doc = "The TrustZone feature is enabled. Access to address in the range specified by \\[ENDADDR:STARTADDR\\] follows the execution mode access policy described in CSU chapter."]
1109 pub const OCRAM_TZ_EN_1: u32 = 0x01;
1110 }
1111 }
1112 #[doc = "OCRAM TrustZone (TZ) start address"]
1113 pub mod OCRAM_TZ_ADDR {
1114 pub const offset: u32 = 9;
1115 pub const mask: u32 = 0x1f << offset;
1116 pub mod R {}
1117 pub mod W {}
1118 pub mod RW {}
1119 }
1120 #[doc = "Lock NIDEN field for changes"]
1121 pub mod LOCK_NIDEN {
1122 pub const offset: u32 = 16;
1123 pub const mask: u32 = 0x01 << offset;
1124 pub mod R {}
1125 pub mod W {}
1126 pub mod RW {
1127 #[doc = "Field is not locked"]
1128 pub const LOCK_NIDEN_0: u32 = 0;
1129 #[doc = "Field is locked (read access only)"]
1130 pub const LOCK_NIDEN_1: u32 = 0x01;
1131 }
1132 }
1133 #[doc = "Lock DBG_EN field for changes"]
1134 pub mod LOCK_DBG_EN {
1135 pub const offset: u32 = 17;
1136 pub const mask: u32 = 0x01 << offset;
1137 pub mod R {}
1138 pub mod W {}
1139 pub mod RW {
1140 #[doc = "Field is not locked"]
1141 pub const LOCK_DBG_EN_0: u32 = 0;
1142 #[doc = "Field is locked (read access only)"]
1143 pub const LOCK_DBG_EN_1: u32 = 0x01;
1144 }
1145 }
1146 #[doc = "Lock SEC_ERR_RESP field for changes"]
1147 pub mod LOCK_SEC_ERR_RESP {
1148 pub const offset: u32 = 18;
1149 pub const mask: u32 = 0x01 << offset;
1150 pub mod R {}
1151 pub mod W {}
1152 pub mod RW {
1153 #[doc = "Field is not locked"]
1154 pub const LOCK_SEC_ERR_RESP_0: u32 = 0;
1155 #[doc = "Field is locked (read access only)"]
1156 pub const LOCK_SEC_ERR_RESP_1: u32 = 0x01;
1157 }
1158 }
1159 #[doc = "Lock DCP Key OCOTP/Key MUX selection bit"]
1160 pub mod LOCK_DCPKEY_OCOTP_OR_KEYMUX {
1161 pub const offset: u32 = 20;
1162 pub const mask: u32 = 0x01 << offset;
1163 pub mod R {}
1164 pub mod W {}
1165 pub mod RW {
1166 #[doc = "Field is not locked"]
1167 pub const LOCK_DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0;
1168 #[doc = "Field is locked (read access only)"]
1169 pub const LOCK_DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01;
1170 }
1171 }
1172 #[doc = "Lock OCRAM_TZ_EN field for changes"]
1173 pub mod LOCK_OCRAM_TZ_EN {
1174 pub const offset: u32 = 24;
1175 pub const mask: u32 = 0x01 << offset;
1176 pub mod R {}
1177 pub mod W {}
1178 pub mod RW {
1179 #[doc = "Field is not locked"]
1180 pub const LOCK_OCRAM_TZ_EN_0: u32 = 0;
1181 #[doc = "Field is locked (read access only)"]
1182 pub const LOCK_OCRAM_TZ_EN_1: u32 = 0x01;
1183 }
1184 }
1185 #[doc = "Lock OCRAM_TZ_ADDR field for changes"]
1186 pub mod LOCK_OCRAM_TZ_ADDR {
1187 pub const offset: u32 = 25;
1188 pub const mask: u32 = 0x1f << offset;
1189 pub mod R {}
1190 pub mod W {}
1191 pub mod RW {
1192 #[doc = "Field is not locked"]
1193 pub const LOCK_OCRAM_TZ_ADDR_0: u32 = 0;
1194 #[doc = "Field is locked (read access only)"]
1195 pub const LOCK_OCRAM_TZ_ADDR_1: u32 = 0x01;
1196 }
1197 }
1198}
1199#[doc = "GPR11 General Purpose Register"]
1200pub mod GPR11 {
1201 #[doc = "Access control of memory region-0"]
1202 pub mod M7_APC_AC_R0_CTRL {
1203 pub const offset: u32 = 0;
1204 pub const mask: u32 = 0x03 << offset;
1205 pub mod R {}
1206 pub mod W {}
1207 pub mod RW {
1208 #[doc = "No access protection"]
1209 pub const M7_APC_AC_R0_CTRL_0: u32 = 0;
1210 #[doc = "M7 debug protection enabled"]
1211 pub const M7_APC_AC_R0_CTRL_1: u32 = 0x01;
1212 }
1213 }
1214 #[doc = "Access control of memory region-1"]
1215 pub mod M7_APC_AC_R1_CTRL {
1216 pub const offset: u32 = 2;
1217 pub const mask: u32 = 0x03 << offset;
1218 pub mod R {}
1219 pub mod W {}
1220 pub mod RW {
1221 #[doc = "No access protection"]
1222 pub const M7_APC_AC_R1_CTRL_0: u32 = 0;
1223 #[doc = "M7 debug protection enabled"]
1224 pub const M7_APC_AC_R1_CTRL_1: u32 = 0x01;
1225 }
1226 }
1227 #[doc = "Access control of memory region-2"]
1228 pub mod M7_APC_AC_R2_CTRL {
1229 pub const offset: u32 = 4;
1230 pub const mask: u32 = 0x03 << offset;
1231 pub mod R {}
1232 pub mod W {}
1233 pub mod RW {
1234 #[doc = "No access protection"]
1235 pub const M7_APC_AC_R2_CTRL_0: u32 = 0;
1236 #[doc = "M7 debug protection enabled"]
1237 pub const M7_APC_AC_R2_CTRL_1: u32 = 0x01;
1238 }
1239 }
1240 #[doc = "Access control of memory region-3"]
1241 pub mod M7_APC_AC_R3_CTRL {
1242 pub const offset: u32 = 6;
1243 pub const mask: u32 = 0x03 << offset;
1244 pub mod R {}
1245 pub mod W {}
1246 pub mod RW {
1247 #[doc = "No access protection"]
1248 pub const M7_APC_AC_R3_CTRL_0: u32 = 0;
1249 #[doc = "M7 debug protection enabled"]
1250 pub const M7_APC_AC_R3_CTRL_1: u32 = 0x01;
1251 }
1252 }
1253 #[doc = "Lock M7_APC_AC_R0_CTRL field for changes"]
1254 pub mod LOCK_M7_APC_AC_R0_CTRL {
1255 pub const offset: u32 = 16;
1256 pub const mask: u32 = 0x03 << offset;
1257 pub mod R {}
1258 pub mod W {}
1259 pub mod RW {}
1260 }
1261 #[doc = "Lock M7_APC_AC_R1_CTRL field for changes"]
1262 pub mod LOCK_M7_APC_AC_R1_CTRL {
1263 pub const offset: u32 = 18;
1264 pub const mask: u32 = 0x03 << offset;
1265 pub mod R {}
1266 pub mod W {}
1267 pub mod RW {}
1268 }
1269 #[doc = "Lock M7_APC_AC_R2_CTRL field for changes"]
1270 pub mod LOCK_M7_APC_AC_R2_CTRL {
1271 pub const offset: u32 = 20;
1272 pub const mask: u32 = 0x03 << offset;
1273 pub mod R {}
1274 pub mod W {}
1275 pub mod RW {}
1276 }
1277 #[doc = "Lock M7_APC_AC_R3_CTRL field for changes"]
1278 pub mod LOCK_M7_APC_AC_R3_CTRL {
1279 pub const offset: u32 = 22;
1280 pub const mask: u32 = 0x03 << offset;
1281 pub mod R {}
1282 pub mod W {}
1283 pub mod RW {}
1284 }
1285}
1286#[doc = "GPR12 General Purpose Register"]
1287pub mod GPR12 {
1288 #[doc = "FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted."]
1289 pub mod FLEXIO1_IPG_STOP_MODE {
1290 pub const offset: u32 = 0;
1291 pub const mask: u32 = 0x01 << offset;
1292 pub mod R {}
1293 pub mod W {}
1294 pub mod RW {
1295 #[doc = "FlexIO1 is functional in Stop mode."]
1296 pub const FLEXIO1_IPG_STOP_MODE_0: u32 = 0;
1297 #[doc = "When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode."]
1298 pub const FLEXIO1_IPG_STOP_MODE_1: u32 = 0x01;
1299 }
1300 }
1301 #[doc = "FLEXIO1 ipg_doze mode"]
1302 pub mod FLEXIO1_IPG_DOZE {
1303 pub const offset: u32 = 1;
1304 pub const mask: u32 = 0x01 << offset;
1305 pub mod R {}
1306 pub mod W {}
1307 pub mod RW {
1308 #[doc = "FLEXIO1 is not in doze mode"]
1309 pub const FLEXIO1_IPG_DOZE_0: u32 = 0;
1310 #[doc = "FLEXIO1 is in doze mode"]
1311 pub const FLEXIO1_IPG_DOZE_1: u32 = 0x01;
1312 }
1313 }
1314}
1315#[doc = "GPR13 General Purpose Register"]
1316pub mod GPR13 {
1317 #[doc = "USB block cacheable attribute value of AXI transactions"]
1318 pub mod CACHE_USB {
1319 pub const offset: u32 = 13;
1320 pub const mask: u32 = 0x01 << offset;
1321 pub mod R {}
1322 pub mod W {}
1323 pub mod RW {
1324 #[doc = "Cacheable attribute is off for read/write transactions."]
1325 pub const CACHE_USB_0: u32 = 0;
1326 #[doc = "Cacheable attribute is on for read/write transactions."]
1327 pub const CACHE_USB_1: u32 = 0x01;
1328 }
1329 }
1330}
1331#[doc = "GPR14 General Purpose Register"]
1332pub mod GPR14 {
1333 #[doc = "ITCM total size configuration"]
1334 pub mod CM7_CFGITCMSZ {
1335 pub const offset: u32 = 16;
1336 pub const mask: u32 = 0x0f << offset;
1337 pub mod R {}
1338 pub mod W {}
1339 pub mod RW {
1340 #[doc = "0 KB (No ITCM)"]
1341 pub const CM7_CFGITCMSZ_0: u32 = 0;
1342 #[doc = "4 KB"]
1343 pub const CM7_CFGITCMSZ_3: u32 = 0x03;
1344 #[doc = "8 KB"]
1345 pub const CM7_CFGITCMSZ_4: u32 = 0x04;
1346 #[doc = "16 KB"]
1347 pub const CM7_CFGITCMSZ_5: u32 = 0x05;
1348 #[doc = "32 KB"]
1349 pub const CM7_CFGITCMSZ_6: u32 = 0x06;
1350 #[doc = "64 KB"]
1351 pub const CM7_CFGITCMSZ_7: u32 = 0x07;
1352 #[doc = "128 KB"]
1353 pub const CM7_CFGITCMSZ_8: u32 = 0x08;
1354 }
1355 }
1356 #[doc = "DTCM total size configuration"]
1357 pub mod CM7_CFGDTCMSZ {
1358 pub const offset: u32 = 20;
1359 pub const mask: u32 = 0x0f << offset;
1360 pub mod R {}
1361 pub mod W {}
1362 pub mod RW {
1363 #[doc = "0 KB (No DTCM)"]
1364 pub const CM7_CFGDTCMSZ_0: u32 = 0;
1365 #[doc = "4 KB"]
1366 pub const CM7_CFGDTCMSZ_3: u32 = 0x03;
1367 #[doc = "8 KB"]
1368 pub const CM7_CFGDTCMSZ_4: u32 = 0x04;
1369 #[doc = "16 KB"]
1370 pub const CM7_CFGDTCMSZ_5: u32 = 0x05;
1371 #[doc = "32 KB"]
1372 pub const CM7_CFGDTCMSZ_6: u32 = 0x06;
1373 #[doc = "64 KB"]
1374 pub const CM7_CFGDTCMSZ_7: u32 = 0x07;
1375 #[doc = "128 KB"]
1376 pub const CM7_CFGDTCMSZ_8: u32 = 0x08;
1377 }
1378 }
1379}
1380#[doc = "GPR16 General Purpose Register"]
1381pub mod GPR16 {
1382 #[doc = "ITCM enable initialization out of reset"]
1383 pub mod INIT_ITCM_EN {
1384 pub const offset: u32 = 0;
1385 pub const mask: u32 = 0x01 << offset;
1386 pub mod R {}
1387 pub mod W {}
1388 pub mod RW {
1389 #[doc = "ITCM is disabled"]
1390 pub const INIT_ITCM_EN_0: u32 = 0;
1391 #[doc = "ITCM is enabled"]
1392 pub const INIT_ITCM_EN_1: u32 = 0x01;
1393 }
1394 }
1395 #[doc = "DTCM enable initialization out of reset"]
1396 pub mod INIT_DTCM_EN {
1397 pub const offset: u32 = 1;
1398 pub const mask: u32 = 0x01 << offset;
1399 pub mod R {}
1400 pub mod W {}
1401 pub mod RW {
1402 #[doc = "DTCM is disabled"]
1403 pub const INIT_DTCM_EN_0: u32 = 0;
1404 #[doc = "DTCM is enabled"]
1405 pub const INIT_DTCM_EN_1: u32 = 0x01;
1406 }
1407 }
1408 #[doc = "FlexRAM bank config source select"]
1409 pub mod FLEXRAM_BANK_CFG_SEL {
1410 pub const offset: u32 = 2;
1411 pub const mask: u32 = 0x01 << offset;
1412 pub mod R {}
1413 pub mod W {}
1414 pub mod RW {
1415 #[doc = "use fuse value to config"]
1416 pub const FLEXRAM_BANK_CFG_SEL_0: u32 = 0;
1417 #[doc = "use FLEXRAM_BANK_CFG to config"]
1418 pub const FLEXRAM_BANK_CFG_SEL_1: u32 = 0x01;
1419 }
1420 }
1421 #[doc = "Lock CM7_INIT_VTOR field for changes"]
1422 pub mod LOCK_VTOR {
1423 pub const offset: u32 = 6;
1424 pub const mask: u32 = 0x01 << offset;
1425 pub mod R {}
1426 pub mod W {}
1427 pub mod RW {
1428 #[doc = "CM7_INIT_VTOR field is not locked."]
1429 pub const LOCK_VTOR_0: u32 = 0;
1430 #[doc = "CM7_INIT_VTOR field is locked (read access only)."]
1431 pub const LOCK_VTOR_1: u32 = 0x01;
1432 }
1433 }
1434 #[doc = "Vector table offset register out of reset"]
1435 pub mod CM7_INIT_VTOR {
1436 pub const offset: u32 = 7;
1437 pub const mask: u32 = 0x01ff_ffff << offset;
1438 pub mod R {}
1439 pub mod W {}
1440 pub mod RW {}
1441 }
1442}
1443#[doc = "GPR17 General Purpose Register"]
1444pub mod GPR17 {
1445 #[doc = "FlexRAM bank config value"]
1446 pub mod FLEXRAM_BANK_CFG {
1447 pub const offset: u32 = 0;
1448 pub const mask: u32 = 0xff << offset;
1449 pub mod R {}
1450 pub mod W {}
1451 pub mod RW {}
1452 }
1453}
1454#[doc = "GPR18 General Purpose Register"]
1455pub mod GPR18 {
1456 #[doc = "lock M7_APC_AC_R0_BOT field for changes"]
1457 pub mod LOCK_M7_APC_AC_R0_BOT {
1458 pub const offset: u32 = 0;
1459 pub const mask: u32 = 0x01 << offset;
1460 pub mod R {}
1461 pub mod W {}
1462 pub mod RW {
1463 #[doc = "Register field \\[31:1\\] is not locked"]
1464 pub const LOCK_M7_APC_AC_R0_BOT_0: u32 = 0;
1465 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1466 pub const LOCK_M7_APC_AC_R0_BOT_1: u32 = 0x01;
1467 }
1468 }
1469 #[doc = "APC end address of memory region-0"]
1470 pub mod M7_APC_AC_R0_BOT {
1471 pub const offset: u32 = 3;
1472 pub const mask: u32 = 0x1fff_ffff << offset;
1473 pub mod R {}
1474 pub mod W {}
1475 pub mod RW {}
1476 }
1477}
1478#[doc = "GPR19 General Purpose Register"]
1479pub mod GPR19 {
1480 #[doc = "lock M7_APC_AC_R0_TOP field for changes"]
1481 pub mod LOCK_M7_APC_AC_R0_TOP {
1482 pub const offset: u32 = 0;
1483 pub const mask: u32 = 0x01 << offset;
1484 pub mod R {}
1485 pub mod W {}
1486 pub mod RW {
1487 #[doc = "Register field \\[31:1\\] is not locked"]
1488 pub const LOCK_M7_APC_AC_R0_TOP_0: u32 = 0;
1489 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1490 pub const LOCK_M7_APC_AC_R0_TOP_1: u32 = 0x01;
1491 }
1492 }
1493 #[doc = "APC start address of memory region-0"]
1494 pub mod M7_APC_AC_R0_TOP {
1495 pub const offset: u32 = 3;
1496 pub const mask: u32 = 0x1fff_ffff << offset;
1497 pub mod R {}
1498 pub mod W {}
1499 pub mod RW {}
1500 }
1501}
1502#[doc = "GPR20 General Purpose Register"]
1503pub mod GPR20 {
1504 #[doc = "lock M7_APC_AC_R1_BOT field for changes"]
1505 pub mod LOCK_M7_APC_AC_R1_BOT {
1506 pub const offset: u32 = 0;
1507 pub const mask: u32 = 0x01 << offset;
1508 pub mod R {}
1509 pub mod W {}
1510 pub mod RW {
1511 #[doc = "Register field \\[31:1\\] is not locked"]
1512 pub const LOCK_M7_APC_AC_R1_BOT_0: u32 = 0;
1513 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1514 pub const LOCK_M7_APC_AC_R1_BOT_1: u32 = 0x01;
1515 }
1516 }
1517 #[doc = "APC end address of memory region-1"]
1518 pub mod M7_APC_AC_R1_BOT {
1519 pub const offset: u32 = 3;
1520 pub const mask: u32 = 0x1fff_ffff << offset;
1521 pub mod R {}
1522 pub mod W {}
1523 pub mod RW {}
1524 }
1525}
1526#[doc = "GPR21 General Purpose Register"]
1527pub mod GPR21 {
1528 #[doc = "lock M7_APC_AC_R1_TOP field for changes"]
1529 pub mod LOCK_M7_APC_AC_R1_TOP {
1530 pub const offset: u32 = 0;
1531 pub const mask: u32 = 0x01 << offset;
1532 pub mod R {}
1533 pub mod W {}
1534 pub mod RW {
1535 #[doc = "Register field \\[31:1\\] is not locked"]
1536 pub const LOCK_M7_APC_AC_R1_TOP_0: u32 = 0;
1537 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1538 pub const LOCK_M7_APC_AC_R1_TOP_1: u32 = 0x01;
1539 }
1540 }
1541 #[doc = "APC start address of memory region-1"]
1542 pub mod M7_APC_AC_R1_TOP {
1543 pub const offset: u32 = 3;
1544 pub const mask: u32 = 0x1fff_ffff << offset;
1545 pub mod R {}
1546 pub mod W {}
1547 pub mod RW {}
1548 }
1549}
1550#[doc = "GPR22 General Purpose Register"]
1551pub mod GPR22 {
1552 #[doc = "lock M7_APC_AC_R2_BOT field for changes"]
1553 pub mod LOCK_M7_APC_AC_R2_BOT {
1554 pub const offset: u32 = 0;
1555 pub const mask: u32 = 0x01 << offset;
1556 pub mod R {}
1557 pub mod W {}
1558 pub mod RW {
1559 #[doc = "Register field \\[31:1\\] is not locked"]
1560 pub const LOCK_M7_APC_AC_R2_BOT_0: u32 = 0;
1561 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1562 pub const LOCK_M7_APC_AC_R2_BOT_1: u32 = 0x01;
1563 }
1564 }
1565 #[doc = "APC end address of memory region-2"]
1566 pub mod M7_APC_AC_R2_BOT {
1567 pub const offset: u32 = 3;
1568 pub const mask: u32 = 0x1fff_ffff << offset;
1569 pub mod R {}
1570 pub mod W {}
1571 pub mod RW {}
1572 }
1573}
1574#[doc = "GPR23 General Purpose Register"]
1575pub mod GPR23 {
1576 #[doc = "lock M7_APC_AC_R2_TOP field for changes"]
1577 pub mod LOCK_M7_APC_AC_R2_TOP {
1578 pub const offset: u32 = 0;
1579 pub const mask: u32 = 0x01 << offset;
1580 pub mod R {}
1581 pub mod W {}
1582 pub mod RW {
1583 #[doc = "Register field \\[31:1\\] is not locked"]
1584 pub const LOCK_M7_APC_AC_R2_TOP_0: u32 = 0;
1585 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1586 pub const LOCK_M7_APC_AC_R2_TOP_1: u32 = 0x01;
1587 }
1588 }
1589 #[doc = "APC start address of memory region-2"]
1590 pub mod M7_APC_AC_R2_TOP {
1591 pub const offset: u32 = 3;
1592 pub const mask: u32 = 0x1fff_ffff << offset;
1593 pub mod R {}
1594 pub mod W {}
1595 pub mod RW {}
1596 }
1597}
1598#[doc = "GPR24 General Purpose Register"]
1599pub mod GPR24 {
1600 #[doc = "lock M7_APC_AC_R3_BOT field for changes"]
1601 pub mod LOCK_M7_APC_AC_R3_BOT {
1602 pub const offset: u32 = 0;
1603 pub const mask: u32 = 0x01 << offset;
1604 pub mod R {}
1605 pub mod W {}
1606 pub mod RW {
1607 #[doc = "Register field \\[31:1\\] is not locked"]
1608 pub const LOCK_M7_APC_AC_R3_BOT_0: u32 = 0;
1609 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1610 pub const LOCK_M7_APC_AC_R3_BOT_1: u32 = 0x01;
1611 }
1612 }
1613 #[doc = "APC end address of memory region-3"]
1614 pub mod M7_APC_AC_R3_BOT {
1615 pub const offset: u32 = 3;
1616 pub const mask: u32 = 0x1fff_ffff << offset;
1617 pub mod R {}
1618 pub mod W {}
1619 pub mod RW {}
1620 }
1621}
1622#[doc = "GPR25 General Purpose Register"]
1623pub mod GPR25 {
1624 #[doc = "lock M7_APC_AC_R3_TOP field for changes"]
1625 pub mod LOCK_M7_APC_AC_R3_TOP {
1626 pub const offset: u32 = 0;
1627 pub const mask: u32 = 0x01 << offset;
1628 pub mod R {}
1629 pub mod W {}
1630 pub mod RW {
1631 #[doc = "Register field \\[31:1\\] is not locked"]
1632 pub const LOCK_M7_APC_AC_R3_TOP_0: u32 = 0;
1633 #[doc = "Register field \\[31:1\\] is locked (read access only)"]
1634 pub const LOCK_M7_APC_AC_R3_TOP_1: u32 = 0x01;
1635 }
1636 }
1637 #[doc = "APC start address of memory region-3"]
1638 pub mod M7_APC_AC_R3_TOP {
1639 pub const offset: u32 = 3;
1640 pub const mask: u32 = 0x1fff_ffff << offset;
1641 pub mod R {}
1642 pub mod W {}
1643 pub mod RW {}
1644 }
1645}
1646#[doc = "GPR26 General Purpose Register"]
1647pub mod GPR26 {
1648 #[doc = "Select GPIO1 or GPIO2"]
1649 pub mod GPIO_SEL {
1650 pub const offset: u32 = 0;
1651 pub const mask: u32 = 0xffff_ffff << offset;
1652 pub mod R {}
1653 pub mod W {}
1654 pub mod RW {}
1655 }
1656}
1657#[doc = "GPR27 General Purpose Register"]
1658pub mod GPR27 {
1659 #[doc = "Start address of flexspi1"]
1660 pub mod FLEXSPI_REMAP_ADDR_START {
1661 pub const offset: u32 = 12;
1662 pub const mask: u32 = 0x000f_ffff << offset;
1663 pub mod R {}
1664 pub mod W {}
1665 pub mod RW {}
1666 }
1667}
1668#[doc = "GPR28 General Purpose Register"]
1669pub mod GPR28 {
1670 #[doc = "End address of flexspi1"]
1671 pub mod FLEXSPI_REMAP_ADDR_END {
1672 pub const offset: u32 = 12;
1673 pub const mask: u32 = 0x000f_ffff << offset;
1674 pub mod R {}
1675 pub mod W {}
1676 pub mod RW {}
1677 }
1678}
1679#[doc = "GPR29 General Purpose Register"]
1680pub mod GPR29 {
1681 #[doc = "Offset address of flexspi1"]
1682 pub mod FLEXSPI_REMAP_ADDR_OFFSET {
1683 pub const offset: u32 = 12;
1684 pub const mask: u32 = 0x000f_ffff << offset;
1685 pub mod R {}
1686 pub mod W {}
1687 pub mod RW {}
1688 }
1689}