imxrt_ral/blocks/imxrt1011/
pit.rs

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1#[doc = "PIT"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "PIT Module Control Register"]
5    pub MCR: crate::RWRegister<u32>,
6    _reserved0: [u8; 0xdc],
7    #[doc = "PIT Upper Lifetime Timer Register"]
8    pub LTMR64H: crate::RORegister<u32>,
9    #[doc = "PIT Lower Lifetime Timer Register"]
10    pub LTMR64L: crate::RORegister<u32>,
11    _reserved1: [u8; 0x18],
12    #[doc = "no description available"]
13    pub TIMER: [timer::RegisterBlock; 4usize],
14}
15#[doc = "PIT Module Control Register"]
16pub mod MCR {
17    #[doc = "Freeze"]
18    pub mod FRZ {
19        pub const offset: u32 = 0;
20        pub const mask: u32 = 0x01 << offset;
21        pub mod R {}
22        pub mod W {}
23        pub mod RW {
24            #[doc = "Timers continue to run in Debug mode."]
25            pub const FRZ_0: u32 = 0;
26            #[doc = "Timers are stopped in Debug mode."]
27            pub const FRZ_1: u32 = 0x01;
28        }
29    }
30    #[doc = "Module Disable for PIT"]
31    pub mod MDIS {
32        pub const offset: u32 = 1;
33        pub const mask: u32 = 0x01 << offset;
34        pub mod R {}
35        pub mod W {}
36        pub mod RW {
37            #[doc = "Clock for standard PIT timers is enabled."]
38            pub const MDIS_0: u32 = 0;
39            #[doc = "Clock for standard PIT timers is disabled."]
40            pub const MDIS_1: u32 = 0x01;
41        }
42    }
43}
44#[doc = "PIT Upper Lifetime Timer Register"]
45pub mod LTMR64H {
46    #[doc = "Life Timer value"]
47    pub mod LTH {
48        pub const offset: u32 = 0;
49        pub const mask: u32 = 0xffff_ffff << offset;
50        pub mod R {}
51        pub mod W {}
52        pub mod RW {}
53    }
54}
55#[doc = "PIT Lower Lifetime Timer Register"]
56pub mod LTMR64L {
57    #[doc = "Life Timer value"]
58    pub mod LTL {
59        pub const offset: u32 = 0;
60        pub const mask: u32 = 0xffff_ffff << offset;
61        pub mod R {}
62        pub mod W {}
63        pub mod RW {}
64    }
65}
66pub mod timer {
67    #[doc = "no description available"]
68    #[repr(C)]
69    pub struct RegisterBlock {
70        #[doc = "Timer Load Value Register"]
71        pub LDVAL: crate::RWRegister<u32>,
72        #[doc = "Current Timer Value Register"]
73        pub CVAL: crate::RORegister<u32>,
74        #[doc = "Timer Control Register"]
75        pub TCTRL: crate::RWRegister<u32>,
76        #[doc = "Timer Flag Register"]
77        pub TFLG: crate::RWRegister<u32>,
78    }
79    #[doc = "Timer Load Value Register"]
80    pub mod LDVAL {
81        #[doc = "Timer Start Value"]
82        pub mod TSV {
83            pub const offset: u32 = 0;
84            pub const mask: u32 = 0xffff_ffff << offset;
85            pub mod R {}
86            pub mod W {}
87            pub mod RW {}
88        }
89    }
90    #[doc = "Current Timer Value Register"]
91    pub mod CVAL {
92        #[doc = "Current Timer Value"]
93        pub mod TVL {
94            pub const offset: u32 = 0;
95            pub const mask: u32 = 0xffff_ffff << offset;
96            pub mod R {}
97            pub mod W {}
98            pub mod RW {}
99        }
100    }
101    #[doc = "Timer Control Register"]
102    pub mod TCTRL {
103        #[doc = "Timer Enable"]
104        pub mod TEN {
105            pub const offset: u32 = 0;
106            pub const mask: u32 = 0x01 << offset;
107            pub mod R {}
108            pub mod W {}
109            pub mod RW {
110                #[doc = "Timer n is disabled."]
111                pub const TEN_0: u32 = 0;
112                #[doc = "Timer n is enabled."]
113                pub const TEN_1: u32 = 0x01;
114            }
115        }
116        #[doc = "Timer Interrupt Enable"]
117        pub mod TIE {
118            pub const offset: u32 = 1;
119            pub const mask: u32 = 0x01 << offset;
120            pub mod R {}
121            pub mod W {}
122            pub mod RW {
123                #[doc = "Interrupt requests from Timer n are disabled."]
124                pub const TIE_0: u32 = 0;
125                #[doc = "Interrupt is requested whenever TIF is set."]
126                pub const TIE_1: u32 = 0x01;
127            }
128        }
129        #[doc = "Chain Mode"]
130        pub mod CHN {
131            pub const offset: u32 = 2;
132            pub const mask: u32 = 0x01 << offset;
133            pub mod R {}
134            pub mod W {}
135            pub mod RW {
136                #[doc = "Timer is not chained."]
137                pub const CHN_0: u32 = 0;
138                #[doc = "Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1."]
139                pub const CHN_1: u32 = 0x01;
140            }
141        }
142    }
143    #[doc = "Timer Flag Register"]
144    pub mod TFLG {
145        #[doc = "Timer Interrupt Flag"]
146        pub mod TIF {
147            pub const offset: u32 = 0;
148            pub const mask: u32 = 0x01 << offset;
149            pub mod R {}
150            pub mod W {}
151            pub mod RW {
152                #[doc = "Timeout has not yet occurred."]
153                pub const TIF_0: u32 = 0;
154                #[doc = "Timeout has occurred."]
155                pub const TIF_1: u32 = 0x01;
156            }
157        }
158    }
159}
imxrt_ral/blocks/imxrt1011/pit.rs

imxrt_ral/blocks/imxrt1011/
pit.rs
