imxrt_ral/blocks/imxrt1011/
dcp.rs

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1#[doc = "DCP register reference index"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "DCP control register 0"]
5    pub CTRL: crate::RWRegister<u32>,
6    #[doc = "DCP control register 0"]
7    pub CTRL_SET: crate::RWRegister<u32>,
8    #[doc = "DCP control register 0"]
9    pub CTRL_CLR: crate::RWRegister<u32>,
10    #[doc = "DCP control register 0"]
11    pub CTRL_TOG: crate::RWRegister<u32>,
12    #[doc = "DCP status register"]
13    pub STAT: crate::RWRegister<u32>,
14    #[doc = "DCP status register"]
15    pub STAT_SET: crate::RWRegister<u32>,
16    #[doc = "DCP status register"]
17    pub STAT_CLR: crate::RWRegister<u32>,
18    #[doc = "DCP status register"]
19    pub STAT_TOG: crate::RWRegister<u32>,
20    #[doc = "DCP channel control register"]
21    pub CHANNELCTRL: crate::RWRegister<u32>,
22    #[doc = "DCP channel control register"]
23    pub CHANNELCTRL_SET: crate::RWRegister<u32>,
24    #[doc = "DCP channel control register"]
25    pub CHANNELCTRL_CLR: crate::RWRegister<u32>,
26    #[doc = "DCP channel control register"]
27    pub CHANNELCTRL_TOG: crate::RWRegister<u32>,
28    #[doc = "DCP capability 0 register"]
29    pub CAPABILITY0: crate::RWRegister<u32>,
30    _reserved0: [u8; 0x0c],
31    #[doc = "DCP capability 1 register"]
32    pub CAPABILITY1: crate::RORegister<u32>,
33    _reserved1: [u8; 0x0c],
34    #[doc = "DCP context buffer pointer"]
35    pub CONTEXT: crate::RWRegister<u32>,
36    _reserved2: [u8; 0x0c],
37    #[doc = "DCP key index"]
38    pub KEY: crate::RWRegister<u32>,
39    _reserved3: [u8; 0x0c],
40    #[doc = "DCP key data"]
41    pub KEYDATA: crate::RWRegister<u32>,
42    _reserved4: [u8; 0x0c],
43    #[doc = "DCP work packet 0 status register"]
44    pub PACKET0: crate::RORegister<u32>,
45    _reserved5: [u8; 0x0c],
46    #[doc = "DCP work packet 1 status register"]
47    pub PACKET1: crate::RORegister<u32>,
48    _reserved6: [u8; 0x0c],
49    #[doc = "DCP work packet 2 status register"]
50    pub PACKET2: crate::RORegister<u32>,
51    _reserved7: [u8; 0x0c],
52    #[doc = "DCP work packet 3 status register"]
53    pub PACKET3: crate::RORegister<u32>,
54    _reserved8: [u8; 0x0c],
55    #[doc = "DCP work packet 4 status register"]
56    pub PACKET4: crate::RORegister<u32>,
57    _reserved9: [u8; 0x0c],
58    #[doc = "DCP work packet 5 status register"]
59    pub PACKET5: crate::RORegister<u32>,
60    _reserved10: [u8; 0x0c],
61    #[doc = "DCP work packet 6 status register"]
62    pub PACKET6: crate::RORegister<u32>,
63    _reserved11: [u8; 0x1c],
64    #[doc = "DCP channel 0 command pointer address register"]
65    pub CH0CMDPTR: crate::RWRegister<u32>,
66    _reserved12: [u8; 0x0c],
67    #[doc = "DCP channel 0 semaphore register"]
68    pub CH0SEMA: crate::RWRegister<u32>,
69    _reserved13: [u8; 0x0c],
70    #[doc = "DCP channel 0 status register"]
71    pub CH0STAT: crate::RWRegister<u32>,
72    #[doc = "DCP channel 0 status register"]
73    pub CH0STAT_SET: crate::RWRegister<u32>,
74    #[doc = "DCP channel 0 status register"]
75    pub CH0STAT_CLR: crate::RWRegister<u32>,
76    #[doc = "DCP channel 0 status register"]
77    pub CH0STAT_TOG: crate::RWRegister<u32>,
78    #[doc = "DCP channel 0 options register"]
79    pub CH0OPTS: crate::RWRegister<u32>,
80    #[doc = "DCP channel 0 options register"]
81    pub CH0OPTS_SET: crate::RWRegister<u32>,
82    #[doc = "DCP channel 0 options register"]
83    pub CH0OPTS_CLR: crate::RWRegister<u32>,
84    #[doc = "DCP channel 0 options register"]
85    pub CH0OPTS_TOG: crate::RWRegister<u32>,
86    #[doc = "DCP channel 1 command pointer address register"]
87    pub CH1CMDPTR: crate::RWRegister<u32>,
88    _reserved14: [u8; 0x0c],
89    #[doc = "DCP channel 1 semaphore register"]
90    pub CH1SEMA: crate::RWRegister<u32>,
91    _reserved15: [u8; 0x0c],
92    #[doc = "DCP channel 1 status register"]
93    pub CH1STAT: crate::RWRegister<u32>,
94    #[doc = "DCP channel 1 status register"]
95    pub CH1STAT_SET: crate::RWRegister<u32>,
96    #[doc = "DCP channel 1 status register"]
97    pub CH1STAT_CLR: crate::RWRegister<u32>,
98    #[doc = "DCP channel 1 status register"]
99    pub CH1STAT_TOG: crate::RWRegister<u32>,
100    #[doc = "DCP channel 1 options register"]
101    pub CH1OPTS: crate::RWRegister<u32>,
102    #[doc = "DCP channel 1 options register"]
103    pub CH1OPTS_SET: crate::RWRegister<u32>,
104    #[doc = "DCP channel 1 options register"]
105    pub CH1OPTS_CLR: crate::RWRegister<u32>,
106    #[doc = "DCP channel 1 options register"]
107    pub CH1OPTS_TOG: crate::RWRegister<u32>,
108    #[doc = "DCP channel 2 command pointer address register"]
109    pub CH2CMDPTR: crate::RWRegister<u32>,
110    _reserved16: [u8; 0x0c],
111    #[doc = "DCP channel 2 semaphore register"]
112    pub CH2SEMA: crate::RWRegister<u32>,
113    _reserved17: [u8; 0x0c],
114    #[doc = "DCP channel 2 status register"]
115    pub CH2STAT: crate::RWRegister<u32>,
116    #[doc = "DCP channel 2 status register"]
117    pub CH2STAT_SET: crate::RWRegister<u32>,
118    #[doc = "DCP channel 2 status register"]
119    pub CH2STAT_CLR: crate::RWRegister<u32>,
120    #[doc = "DCP channel 2 status register"]
121    pub CH2STAT_TOG: crate::RWRegister<u32>,
122    #[doc = "DCP channel 2 options register"]
123    pub CH2OPTS: crate::RWRegister<u32>,
124    #[doc = "DCP channel 2 options register"]
125    pub CH2OPTS_SET: crate::RWRegister<u32>,
126    #[doc = "DCP channel 2 options register"]
127    pub CH2OPTS_CLR: crate::RWRegister<u32>,
128    #[doc = "DCP channel 2 options register"]
129    pub CH2OPTS_TOG: crate::RWRegister<u32>,
130    #[doc = "DCP channel 3 command pointer address register"]
131    pub CH3CMDPTR: crate::RWRegister<u32>,
132    _reserved18: [u8; 0x0c],
133    #[doc = "DCP channel 3 semaphore register"]
134    pub CH3SEMA: crate::RWRegister<u32>,
135    _reserved19: [u8; 0x0c],
136    #[doc = "DCP channel 3 status register"]
137    pub CH3STAT: crate::RWRegister<u32>,
138    #[doc = "DCP channel 3 status register"]
139    pub CH3STAT_SET: crate::RWRegister<u32>,
140    #[doc = "DCP channel 3 status register"]
141    pub CH3STAT_CLR: crate::RWRegister<u32>,
142    #[doc = "DCP channel 3 status register"]
143    pub CH3STAT_TOG: crate::RWRegister<u32>,
144    #[doc = "DCP channel 3 options register"]
145    pub CH3OPTS: crate::RWRegister<u32>,
146    #[doc = "DCP channel 3 options register"]
147    pub CH3OPTS_SET: crate::RWRegister<u32>,
148    #[doc = "DCP channel 3 options register"]
149    pub CH3OPTS_CLR: crate::RWRegister<u32>,
150    #[doc = "DCP channel 3 options register"]
151    pub CH3OPTS_TOG: crate::RWRegister<u32>,
152    _reserved20: [u8; 0x0200],
153    #[doc = "DCP debug select register"]
154    pub DBGSELECT: crate::RWRegister<u32>,
155    _reserved21: [u8; 0x0c],
156    #[doc = "DCP debug data register"]
157    pub DBGDATA: crate::RORegister<u32>,
158    _reserved22: [u8; 0x0c],
159    #[doc = "DCP page table register"]
160    pub PAGETABLE: crate::RWRegister<u32>,
161    _reserved23: [u8; 0x0c],
162    #[doc = "DCP version register"]
163    pub VERSION: crate::RORegister<u32>,
164}
165#[doc = "DCP control register 0"]
166pub mod CTRL {
167    #[doc = "Per-channel interrupt enable bit"]
168    pub mod CHANNEL_INTERRUPT_ENABLE {
169        pub const offset: u32 = 0;
170        pub const mask: u32 = 0xff << offset;
171        pub mod R {}
172        pub mod W {}
173        pub mod RW {
174            #[doc = "CH0"]
175            pub const CH0: u32 = 0x01;
176            #[doc = "CH1"]
177            pub const CH1: u32 = 0x02;
178            #[doc = "CH2"]
179            pub const CH2: u32 = 0x04;
180            #[doc = "CH3"]
181            pub const CH3: u32 = 0x08;
182        }
183    }
184    #[doc = "Enable automatic context switching for the channels"]
185    pub mod ENABLE_CONTEXT_SWITCHING {
186        pub const offset: u32 = 21;
187        pub const mask: u32 = 0x01 << offset;
188        pub mod R {}
189        pub mod W {}
190        pub mod RW {}
191    }
192    #[doc = "The software must set this bit to enable the caching of contexts between the operations"]
193    pub mod ENABLE_CONTEXT_CACHING {
194        pub const offset: u32 = 22;
195        pub const mask: u32 = 0x01 << offset;
196        pub mod R {}
197        pub mod W {}
198        pub mod RW {}
199    }
200    #[doc = "The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations"]
201    pub mod GATHER_RESIDUAL_WRITES {
202        pub const offset: u32 = 23;
203        pub const mask: u32 = 0x01 << offset;
204        pub mod R {}
205        pub mod W {}
206        pub mod RW {}
207    }
208    #[doc = "Indicates whether the SHA1/SHA2 functions are present."]
209    pub mod PRESENT_SHA {
210        pub const offset: u32 = 28;
211        pub const mask: u32 = 0x01 << offset;
212        pub mod R {}
213        pub mod W {}
214        pub mod RW {
215            #[doc = "Absent"]
216            pub const ABSENT: u32 = 0;
217            #[doc = "Present"]
218            pub const PRESENT: u32 = 0x01;
219        }
220    }
221    #[doc = "Indicates whether the crypto (cipher/hash) functions are present."]
222    pub mod PRESENT_CRYPTO {
223        pub const offset: u32 = 29;
224        pub const mask: u32 = 0x01 << offset;
225        pub mod R {}
226        pub mod W {}
227        pub mod RW {
228            #[doc = "Absent"]
229            pub const ABSENT: u32 = 0;
230            #[doc = "Present"]
231            pub const PRESENT: u32 = 0x01;
232        }
233    }
234    #[doc = "This bit must be set to zero for a normal operation"]
235    pub mod CLKGATE {
236        pub const offset: u32 = 30;
237        pub const mask: u32 = 0x01 << offset;
238        pub mod R {}
239        pub mod W {}
240        pub mod RW {}
241    }
242    #[doc = "Set this bit to zero to enable a normal DCP operation"]
243    pub mod SFTRST {
244        pub const offset: u32 = 31;
245        pub const mask: u32 = 0x01 << offset;
246        pub mod R {}
247        pub mod W {}
248        pub mod RW {}
249    }
250}
251#[doc = "DCP control register 0"]
252pub mod CTRL_SET {
253    #[doc = "Per-channel interrupt enable bit"]
254    pub mod CHANNEL_INTERRUPT_ENABLE {
255        pub const offset: u32 = 0;
256        pub const mask: u32 = 0xff << offset;
257        pub mod R {}
258        pub mod W {}
259        pub mod RW {
260            #[doc = "CH0"]
261            pub const CH0: u32 = 0x01;
262            #[doc = "CH1"]
263            pub const CH1: u32 = 0x02;
264            #[doc = "CH2"]
265            pub const CH2: u32 = 0x04;
266            #[doc = "CH3"]
267            pub const CH3: u32 = 0x08;
268        }
269    }
270    #[doc = "Enable automatic context switching for the channels"]
271    pub mod ENABLE_CONTEXT_SWITCHING {
272        pub const offset: u32 = 21;
273        pub const mask: u32 = 0x01 << offset;
274        pub mod R {}
275        pub mod W {}
276        pub mod RW {}
277    }
278    #[doc = "The software must set this bit to enable the caching of contexts between the operations"]
279    pub mod ENABLE_CONTEXT_CACHING {
280        pub const offset: u32 = 22;
281        pub const mask: u32 = 0x01 << offset;
282        pub mod R {}
283        pub mod W {}
284        pub mod RW {}
285    }
286    #[doc = "The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations"]
287    pub mod GATHER_RESIDUAL_WRITES {
288        pub const offset: u32 = 23;
289        pub const mask: u32 = 0x01 << offset;
290        pub mod R {}
291        pub mod W {}
292        pub mod RW {}
293    }
294    #[doc = "Indicates whether the SHA1/SHA2 functions are present."]
295    pub mod PRESENT_SHA {
296        pub const offset: u32 = 28;
297        pub const mask: u32 = 0x01 << offset;
298        pub mod R {}
299        pub mod W {}
300        pub mod RW {
301            #[doc = "Absent"]
302            pub const ABSENT: u32 = 0;
303            #[doc = "Present"]
304            pub const PRESENT: u32 = 0x01;
305        }
306    }
307    #[doc = "Indicates whether the crypto (cipher/hash) functions are present."]
308    pub mod PRESENT_CRYPTO {
309        pub const offset: u32 = 29;
310        pub const mask: u32 = 0x01 << offset;
311        pub mod R {}
312        pub mod W {}
313        pub mod RW {
314            #[doc = "Absent"]
315            pub const ABSENT: u32 = 0;
316            #[doc = "Present"]
317            pub const PRESENT: u32 = 0x01;
318        }
319    }
320    #[doc = "This bit must be set to zero for a normal operation"]
321    pub mod CLKGATE {
322        pub const offset: u32 = 30;
323        pub const mask: u32 = 0x01 << offset;
324        pub mod R {}
325        pub mod W {}
326        pub mod RW {}
327    }
328    #[doc = "Set this bit to zero to enable a normal DCP operation"]
329    pub mod SFTRST {
330        pub const offset: u32 = 31;
331        pub const mask: u32 = 0x01 << offset;
332        pub mod R {}
333        pub mod W {}
334        pub mod RW {}
335    }
336}
337#[doc = "DCP control register 0"]
338pub mod CTRL_CLR {
339    #[doc = "Per-channel interrupt enable bit"]
340    pub mod CHANNEL_INTERRUPT_ENABLE {
341        pub const offset: u32 = 0;
342        pub const mask: u32 = 0xff << offset;
343        pub mod R {}
344        pub mod W {}
345        pub mod RW {
346            #[doc = "CH0"]
347            pub const CH0: u32 = 0x01;
348            #[doc = "CH1"]
349            pub const CH1: u32 = 0x02;
350            #[doc = "CH2"]
351            pub const CH2: u32 = 0x04;
352            #[doc = "CH3"]
353            pub const CH3: u32 = 0x08;
354        }
355    }
356    #[doc = "Enable automatic context switching for the channels"]
357    pub mod ENABLE_CONTEXT_SWITCHING {
358        pub const offset: u32 = 21;
359        pub const mask: u32 = 0x01 << offset;
360        pub mod R {}
361        pub mod W {}
362        pub mod RW {}
363    }
364    #[doc = "The software must set this bit to enable the caching of contexts between the operations"]
365    pub mod ENABLE_CONTEXT_CACHING {
366        pub const offset: u32 = 22;
367        pub const mask: u32 = 0x01 << offset;
368        pub mod R {}
369        pub mod W {}
370        pub mod RW {}
371    }
372    #[doc = "The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations"]
373    pub mod GATHER_RESIDUAL_WRITES {
374        pub const offset: u32 = 23;
375        pub const mask: u32 = 0x01 << offset;
376        pub mod R {}
377        pub mod W {}
378        pub mod RW {}
379    }
380    #[doc = "Indicates whether the SHA1/SHA2 functions are present."]
381    pub mod PRESENT_SHA {
382        pub const offset: u32 = 28;
383        pub const mask: u32 = 0x01 << offset;
384        pub mod R {}
385        pub mod W {}
386        pub mod RW {
387            #[doc = "Absent"]
388            pub const ABSENT: u32 = 0;
389            #[doc = "Present"]
390            pub const PRESENT: u32 = 0x01;
391        }
392    }
393    #[doc = "Indicates whether the crypto (cipher/hash) functions are present."]
394    pub mod PRESENT_CRYPTO {
395        pub const offset: u32 = 29;
396        pub const mask: u32 = 0x01 << offset;
397        pub mod R {}
398        pub mod W {}
399        pub mod RW {
400            #[doc = "Absent"]
401            pub const ABSENT: u32 = 0;
402            #[doc = "Present"]
403            pub const PRESENT: u32 = 0x01;
404        }
405    }
406    #[doc = "This bit must be set to zero for a normal operation"]
407    pub mod CLKGATE {
408        pub const offset: u32 = 30;
409        pub const mask: u32 = 0x01 << offset;
410        pub mod R {}
411        pub mod W {}
412        pub mod RW {}
413    }
414    #[doc = "Set this bit to zero to enable a normal DCP operation"]
415    pub mod SFTRST {
416        pub const offset: u32 = 31;
417        pub const mask: u32 = 0x01 << offset;
418        pub mod R {}
419        pub mod W {}
420        pub mod RW {}
421    }
422}
423#[doc = "DCP control register 0"]
424pub mod CTRL_TOG {
425    #[doc = "Per-channel interrupt enable bit"]
426    pub mod CHANNEL_INTERRUPT_ENABLE {
427        pub const offset: u32 = 0;
428        pub const mask: u32 = 0xff << offset;
429        pub mod R {}
430        pub mod W {}
431        pub mod RW {
432            #[doc = "CH0"]
433            pub const CH0: u32 = 0x01;
434            #[doc = "CH1"]
435            pub const CH1: u32 = 0x02;
436            #[doc = "CH2"]
437            pub const CH2: u32 = 0x04;
438            #[doc = "CH3"]
439            pub const CH3: u32 = 0x08;
440        }
441    }
442    #[doc = "Enable automatic context switching for the channels"]
443    pub mod ENABLE_CONTEXT_SWITCHING {
444        pub const offset: u32 = 21;
445        pub const mask: u32 = 0x01 << offset;
446        pub mod R {}
447        pub mod W {}
448        pub mod RW {}
449    }
450    #[doc = "The software must set this bit to enable the caching of contexts between the operations"]
451    pub mod ENABLE_CONTEXT_CACHING {
452        pub const offset: u32 = 22;
453        pub const mask: u32 = 0x01 << offset;
454        pub mod R {}
455        pub mod W {}
456        pub mod RW {}
457    }
458    #[doc = "The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations"]
459    pub mod GATHER_RESIDUAL_WRITES {
460        pub const offset: u32 = 23;
461        pub const mask: u32 = 0x01 << offset;
462        pub mod R {}
463        pub mod W {}
464        pub mod RW {}
465    }
466    #[doc = "Indicates whether the SHA1/SHA2 functions are present."]
467    pub mod PRESENT_SHA {
468        pub const offset: u32 = 28;
469        pub const mask: u32 = 0x01 << offset;
470        pub mod R {}
471        pub mod W {}
472        pub mod RW {
473            #[doc = "Absent"]
474            pub const ABSENT: u32 = 0;
475            #[doc = "Present"]
476            pub const PRESENT: u32 = 0x01;
477        }
478    }
479    #[doc = "Indicates whether the crypto (cipher/hash) functions are present."]
480    pub mod PRESENT_CRYPTO {
481        pub const offset: u32 = 29;
482        pub const mask: u32 = 0x01 << offset;
483        pub mod R {}
484        pub mod W {}
485        pub mod RW {
486            #[doc = "Absent"]
487            pub const ABSENT: u32 = 0;
488            #[doc = "Present"]
489            pub const PRESENT: u32 = 0x01;
490        }
491    }
492    #[doc = "This bit must be set to zero for a normal operation"]
493    pub mod CLKGATE {
494        pub const offset: u32 = 30;
495        pub const mask: u32 = 0x01 << offset;
496        pub mod R {}
497        pub mod W {}
498        pub mod RW {}
499    }
500    #[doc = "Set this bit to zero to enable a normal DCP operation"]
501    pub mod SFTRST {
502        pub const offset: u32 = 31;
503        pub const mask: u32 = 0x01 << offset;
504        pub mod R {}
505        pub mod W {}
506        pub mod RW {}
507    }
508}
509#[doc = "DCP status register"]
510pub mod STAT {
511    #[doc = "Indicates which channels have pending interrupt requests"]
512    pub mod IRQ {
513        pub const offset: u32 = 0;
514        pub const mask: u32 = 0x0f << offset;
515        pub mod R {}
516        pub mod W {}
517        pub mod RW {}
518    }
519    #[doc = "Indicates which channels are ready to proceed with a transfer (the active channel is also included)"]
520    pub mod READY_CHANNELS {
521        pub const offset: u32 = 16;
522        pub const mask: u32 = 0xff << offset;
523        pub mod R {}
524        pub mod W {}
525        pub mod RW {
526            #[doc = "CH0"]
527            pub const CH0: u32 = 0x01;
528            #[doc = "CH1"]
529            pub const CH1: u32 = 0x02;
530            #[doc = "CH2"]
531            pub const CH2: u32 = 0x04;
532            #[doc = "CH3"]
533            pub const CH3: u32 = 0x08;
534        }
535    }
536    #[doc = "Current (active) channel (encoded)"]
537    pub mod CUR_CHANNEL {
538        pub const offset: u32 = 24;
539        pub const mask: u32 = 0x0f << offset;
540        pub mod R {}
541        pub mod W {}
542        pub mod RW {
543            #[doc = "None"]
544            pub const NONE: u32 = 0;
545            #[doc = "CH0"]
546            pub const CH0: u32 = 0x01;
547            #[doc = "CH1"]
548            pub const CH1: u32 = 0x02;
549            #[doc = "CH2"]
550            pub const CH2: u32 = 0x03;
551            #[doc = "CH3"]
552            pub const CH3: u32 = 0x04;
553        }
554    }
555    #[doc = "When set, it indicates that the OTP key is shifted from the fuse block and is ready for use."]
556    pub mod OTP_KEY_READY {
557        pub const offset: u32 = 28;
558        pub const mask: u32 = 0x01 << offset;
559        pub mod R {}
560        pub mod W {}
561        pub mod RW {}
562    }
563}
564#[doc = "DCP status register"]
565pub mod STAT_SET {
566    #[doc = "Indicates which channels have pending interrupt requests"]
567    pub mod IRQ {
568        pub const offset: u32 = 0;
569        pub const mask: u32 = 0x0f << offset;
570        pub mod R {}
571        pub mod W {}
572        pub mod RW {}
573    }
574    #[doc = "Indicates which channels are ready to proceed with a transfer (the active channel is also included)"]
575    pub mod READY_CHANNELS {
576        pub const offset: u32 = 16;
577        pub const mask: u32 = 0xff << offset;
578        pub mod R {}
579        pub mod W {}
580        pub mod RW {
581            #[doc = "CH0"]
582            pub const CH0: u32 = 0x01;
583            #[doc = "CH1"]
584            pub const CH1: u32 = 0x02;
585            #[doc = "CH2"]
586            pub const CH2: u32 = 0x04;
587            #[doc = "CH3"]
588            pub const CH3: u32 = 0x08;
589        }
590    }
591    #[doc = "Current (active) channel (encoded)"]
592    pub mod CUR_CHANNEL {
593        pub const offset: u32 = 24;
594        pub const mask: u32 = 0x0f << offset;
595        pub mod R {}
596        pub mod W {}
597        pub mod RW {
598            #[doc = "None"]
599            pub const NONE: u32 = 0;
600            #[doc = "CH0"]
601            pub const CH0: u32 = 0x01;
602            #[doc = "CH1"]
603            pub const CH1: u32 = 0x02;
604            #[doc = "CH2"]
605            pub const CH2: u32 = 0x03;
606            #[doc = "CH3"]
607            pub const CH3: u32 = 0x04;
608        }
609    }
610    #[doc = "When set, it indicates that the OTP key is shifted from the fuse block and is ready for use."]
611    pub mod OTP_KEY_READY {
612        pub const offset: u32 = 28;
613        pub const mask: u32 = 0x01 << offset;
614        pub mod R {}
615        pub mod W {}
616        pub mod RW {}
617    }
618}
619#[doc = "DCP status register"]
620pub mod STAT_CLR {
621    #[doc = "Indicates which channels have pending interrupt requests"]
622    pub mod IRQ {
623        pub const offset: u32 = 0;
624        pub const mask: u32 = 0x0f << offset;
625        pub mod R {}
626        pub mod W {}
627        pub mod RW {}
628    }
629    #[doc = "Indicates which channels are ready to proceed with a transfer (the active channel is also included)"]
630    pub mod READY_CHANNELS {
631        pub const offset: u32 = 16;
632        pub const mask: u32 = 0xff << offset;
633        pub mod R {}
634        pub mod W {}
635        pub mod RW {
636            #[doc = "CH0"]
637            pub const CH0: u32 = 0x01;
638            #[doc = "CH1"]
639            pub const CH1: u32 = 0x02;
640            #[doc = "CH2"]
641            pub const CH2: u32 = 0x04;
642            #[doc = "CH3"]
643            pub const CH3: u32 = 0x08;
644        }
645    }
646    #[doc = "Current (active) channel (encoded)"]
647    pub mod CUR_CHANNEL {
648        pub const offset: u32 = 24;
649        pub const mask: u32 = 0x0f << offset;
650        pub mod R {}
651        pub mod W {}
652        pub mod RW {
653            #[doc = "None"]
654            pub const NONE: u32 = 0;
655            #[doc = "CH0"]
656            pub const CH0: u32 = 0x01;
657            #[doc = "CH1"]
658            pub const CH1: u32 = 0x02;
659            #[doc = "CH2"]
660            pub const CH2: u32 = 0x03;
661            #[doc = "CH3"]
662            pub const CH3: u32 = 0x04;
663        }
664    }
665    #[doc = "When set, it indicates that the OTP key is shifted from the fuse block and is ready for use."]
666    pub mod OTP_KEY_READY {
667        pub const offset: u32 = 28;
668        pub const mask: u32 = 0x01 << offset;
669        pub mod R {}
670        pub mod W {}
671        pub mod RW {}
672    }
673}
674#[doc = "DCP status register"]
675pub mod STAT_TOG {
676    #[doc = "Indicates which channels have pending interrupt requests"]
677    pub mod IRQ {
678        pub const offset: u32 = 0;
679        pub const mask: u32 = 0x0f << offset;
680        pub mod R {}
681        pub mod W {}
682        pub mod RW {}
683    }
684    #[doc = "Indicates which channels are ready to proceed with a transfer (the active channel is also included)"]
685    pub mod READY_CHANNELS {
686        pub const offset: u32 = 16;
687        pub const mask: u32 = 0xff << offset;
688        pub mod R {}
689        pub mod W {}
690        pub mod RW {
691            #[doc = "CH0"]
692            pub const CH0: u32 = 0x01;
693            #[doc = "CH1"]
694            pub const CH1: u32 = 0x02;
695            #[doc = "CH2"]
696            pub const CH2: u32 = 0x04;
697            #[doc = "CH3"]
698            pub const CH3: u32 = 0x08;
699        }
700    }
701    #[doc = "Current (active) channel (encoded)"]
702    pub mod CUR_CHANNEL {
703        pub const offset: u32 = 24;
704        pub const mask: u32 = 0x0f << offset;
705        pub mod R {}
706        pub mod W {}
707        pub mod RW {
708            #[doc = "None"]
709            pub const NONE: u32 = 0;
710            #[doc = "CH0"]
711            pub const CH0: u32 = 0x01;
712            #[doc = "CH1"]
713            pub const CH1: u32 = 0x02;
714            #[doc = "CH2"]
715            pub const CH2: u32 = 0x03;
716            #[doc = "CH3"]
717            pub const CH3: u32 = 0x04;
718        }
719    }
720    #[doc = "When set, it indicates that the OTP key is shifted from the fuse block and is ready for use."]
721    pub mod OTP_KEY_READY {
722        pub const offset: u32 = 28;
723        pub const mask: u32 = 0x01 << offset;
724        pub mod R {}
725        pub mod W {}
726        pub mod RW {}
727    }
728}
729#[doc = "DCP channel control register"]
730pub mod CHANNELCTRL {
731    #[doc = "Setting a bit in this field enables the DMA channel associated with it"]
732    pub mod ENABLE_CHANNEL {
733        pub const offset: u32 = 0;
734        pub const mask: u32 = 0xff << offset;
735        pub mod R {}
736        pub mod W {}
737        pub mod RW {
738            #[doc = "CH0"]
739            pub const CH0: u32 = 0x01;
740            #[doc = "CH1"]
741            pub const CH1: u32 = 0x02;
742            #[doc = "CH2"]
743            pub const CH2: u32 = 0x04;
744            #[doc = "CH3"]
745            pub const CH3: u32 = 0x08;
746        }
747    }
748    #[doc = "Setting a bit in this field causes the corresponding channel to have high-priority arbitration"]
749    pub mod HIGH_PRIORITY_CHANNEL {
750        pub const offset: u32 = 8;
751        pub const mask: u32 = 0xff << offset;
752        pub mod R {}
753        pub mod W {}
754        pub mod RW {
755            #[doc = "CH0"]
756            pub const CH0: u32 = 0x01;
757            #[doc = "CH1"]
758            pub const CH1: u32 = 0x02;
759            #[doc = "CH2"]
760            pub const CH2: u32 = 0x04;
761            #[doc = "CH3"]
762            pub const CH3: u32 = 0x08;
763        }
764    }
765    #[doc = "Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt"]
766    pub mod CH0_IRQ_MERGED {
767        pub const offset: u32 = 16;
768        pub const mask: u32 = 0x01 << offset;
769        pub mod R {}
770        pub mod W {}
771        pub mod RW {}
772    }
773}
774#[doc = "DCP channel control register"]
775pub mod CHANNELCTRL_SET {
776    #[doc = "Setting a bit in this field enables the DMA channel associated with it"]
777    pub mod ENABLE_CHANNEL {
778        pub const offset: u32 = 0;
779        pub const mask: u32 = 0xff << offset;
780        pub mod R {}
781        pub mod W {}
782        pub mod RW {
783            #[doc = "CH0"]
784            pub const CH0: u32 = 0x01;
785            #[doc = "CH1"]
786            pub const CH1: u32 = 0x02;
787            #[doc = "CH2"]
788            pub const CH2: u32 = 0x04;
789            #[doc = "CH3"]
790            pub const CH3: u32 = 0x08;
791        }
792    }
793    #[doc = "Setting a bit in this field causes the corresponding channel to have high-priority arbitration"]
794    pub mod HIGH_PRIORITY_CHANNEL {
795        pub const offset: u32 = 8;
796        pub const mask: u32 = 0xff << offset;
797        pub mod R {}
798        pub mod W {}
799        pub mod RW {
800            #[doc = "CH0"]
801            pub const CH0: u32 = 0x01;
802            #[doc = "CH1"]
803            pub const CH1: u32 = 0x02;
804            #[doc = "CH2"]
805            pub const CH2: u32 = 0x04;
806            #[doc = "CH3"]
807            pub const CH3: u32 = 0x08;
808        }
809    }
810    #[doc = "Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt"]
811    pub mod CH0_IRQ_MERGED {
812        pub const offset: u32 = 16;
813        pub const mask: u32 = 0x01 << offset;
814        pub mod R {}
815        pub mod W {}
816        pub mod RW {}
817    }
818}
819#[doc = "DCP channel control register"]
820pub mod CHANNELCTRL_CLR {
821    #[doc = "Setting a bit in this field enables the DMA channel associated with it"]
822    pub mod ENABLE_CHANNEL {
823        pub const offset: u32 = 0;
824        pub const mask: u32 = 0xff << offset;
825        pub mod R {}
826        pub mod W {}
827        pub mod RW {
828            #[doc = "CH0"]
829            pub const CH0: u32 = 0x01;
830            #[doc = "CH1"]
831            pub const CH1: u32 = 0x02;
832            #[doc = "CH2"]
833            pub const CH2: u32 = 0x04;
834            #[doc = "CH3"]
835            pub const CH3: u32 = 0x08;
836        }
837    }
838    #[doc = "Setting a bit in this field causes the corresponding channel to have high-priority arbitration"]
839    pub mod HIGH_PRIORITY_CHANNEL {
840        pub const offset: u32 = 8;
841        pub const mask: u32 = 0xff << offset;
842        pub mod R {}
843        pub mod W {}
844        pub mod RW {
845            #[doc = "CH0"]
846            pub const CH0: u32 = 0x01;
847            #[doc = "CH1"]
848            pub const CH1: u32 = 0x02;
849            #[doc = "CH2"]
850            pub const CH2: u32 = 0x04;
851            #[doc = "CH3"]
852            pub const CH3: u32 = 0x08;
853        }
854    }
855    #[doc = "Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt"]
856    pub mod CH0_IRQ_MERGED {
857        pub const offset: u32 = 16;
858        pub const mask: u32 = 0x01 << offset;
859        pub mod R {}
860        pub mod W {}
861        pub mod RW {}
862    }
863}
864#[doc = "DCP channel control register"]
865pub mod CHANNELCTRL_TOG {
866    #[doc = "Setting a bit in this field enables the DMA channel associated with it"]
867    pub mod ENABLE_CHANNEL {
868        pub const offset: u32 = 0;
869        pub const mask: u32 = 0xff << offset;
870        pub mod R {}
871        pub mod W {}
872        pub mod RW {
873            #[doc = "CH0"]
874            pub const CH0: u32 = 0x01;
875            #[doc = "CH1"]
876            pub const CH1: u32 = 0x02;
877            #[doc = "CH2"]
878            pub const CH2: u32 = 0x04;
879            #[doc = "CH3"]
880            pub const CH3: u32 = 0x08;
881        }
882    }
883    #[doc = "Setting a bit in this field causes the corresponding channel to have high-priority arbitration"]
884    pub mod HIGH_PRIORITY_CHANNEL {
885        pub const offset: u32 = 8;
886        pub const mask: u32 = 0xff << offset;
887        pub mod R {}
888        pub mod W {}
889        pub mod RW {
890            #[doc = "CH0"]
891            pub const CH0: u32 = 0x01;
892            #[doc = "CH1"]
893            pub const CH1: u32 = 0x02;
894            #[doc = "CH2"]
895            pub const CH2: u32 = 0x04;
896            #[doc = "CH3"]
897            pub const CH3: u32 = 0x08;
898        }
899    }
900    #[doc = "Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt"]
901    pub mod CH0_IRQ_MERGED {
902        pub const offset: u32 = 16;
903        pub const mask: u32 = 0x01 << offset;
904        pub mod R {}
905        pub mod W {}
906        pub mod RW {}
907    }
908}
909#[doc = "DCP capability 0 register"]
910pub mod CAPABILITY0 {
911    #[doc = "Encoded value indicating the number of key-storage locations implemented in the design"]
912    pub mod NUM_KEYS {
913        pub const offset: u32 = 0;
914        pub const mask: u32 = 0xff << offset;
915        pub mod R {}
916        pub mod W {}
917        pub mod RW {}
918    }
919    #[doc = "Encoded value indicating the number of channels implemented in the design"]
920    pub mod NUM_CHANNELS {
921        pub const offset: u32 = 8;
922        pub const mask: u32 = 0x0f << offset;
923        pub mod R {}
924        pub mod W {}
925        pub mod RW {}
926    }
927    #[doc = "Write to a 1 to disable the per-device unique key"]
928    pub mod DISABLE_UNIQUE_KEY {
929        pub const offset: u32 = 29;
930        pub const mask: u32 = 0x01 << offset;
931        pub mod R {}
932        pub mod W {}
933        pub mod RW {}
934    }
935    #[doc = "Write to 1 to disable the decryption"]
936    pub mod DISABLE_DECRYPT {
937        pub const offset: u32 = 31;
938        pub const mask: u32 = 0x01 << offset;
939        pub mod R {}
940        pub mod W {}
941        pub mod RW {}
942    }
943}
944#[doc = "DCP capability 1 register"]
945pub mod CAPABILITY1 {
946    #[doc = "One-hot field indicating which cipher algorithms are available"]
947    pub mod CIPHER_ALGORITHMS {
948        pub const offset: u32 = 0;
949        pub const mask: u32 = 0xffff << offset;
950        pub mod R {}
951        pub mod W {}
952        pub mod RW {
953            #[doc = "AES128"]
954            pub const AES128: u32 = 0x01;
955        }
956    }
957    #[doc = "One-hot field indicating which hashing features are implemented in the hardware"]
958    pub mod HASH_ALGORITHMS {
959        pub const offset: u32 = 16;
960        pub const mask: u32 = 0xffff << offset;
961        pub mod R {}
962        pub mod W {}
963        pub mod RW {
964            #[doc = "SHA1"]
965            pub const SHA1: u32 = 0x01;
966            #[doc = "CRC32"]
967            pub const CRC32: u32 = 0x02;
968            #[doc = "SHA256"]
969            pub const SHA256: u32 = 0x04;
970        }
971    }
972}
973#[doc = "DCP context buffer pointer"]
974pub mod CONTEXT {
975    #[doc = "Context pointer address"]
976    pub mod ADDR {
977        pub const offset: u32 = 0;
978        pub const mask: u32 = 0xffff_ffff << offset;
979        pub mod R {}
980        pub mod W {}
981        pub mod RW {}
982    }
983}
984#[doc = "DCP key index"]
985pub mod KEY {
986    #[doc = "Key subword pointer"]
987    pub mod SUBWORD {
988        pub const offset: u32 = 0;
989        pub const mask: u32 = 0x03 << offset;
990        pub mod R {}
991        pub mod W {}
992        pub mod RW {}
993    }
994    #[doc = "Key index pointer. The valid indices are 0-\\[number_keys\\]."]
995    pub mod INDEX {
996        pub const offset: u32 = 4;
997        pub const mask: u32 = 0x03 << offset;
998        pub mod R {}
999        pub mod W {}
1000        pub mod RW {}
1001    }
1002}
1003#[doc = "DCP key data"]
1004pub mod KEYDATA {
1005    #[doc = "Word 0 data for the key. This is the least-significant word."]
1006    pub mod DATA {
1007        pub const offset: u32 = 0;
1008        pub const mask: u32 = 0xffff_ffff << offset;
1009        pub mod R {}
1010        pub mod W {}
1011        pub mod RW {}
1012    }
1013}
1014#[doc = "DCP work packet 0 status register"]
1015pub mod PACKET0 {
1016    #[doc = "Next pointer register"]
1017    pub mod ADDR {
1018        pub const offset: u32 = 0;
1019        pub const mask: u32 = 0xffff_ffff << offset;
1020        pub mod R {}
1021        pub mod W {}
1022        pub mod RW {}
1023    }
1024}
1025#[doc = "DCP work packet 1 status register"]
1026pub mod PACKET1 {
1027    #[doc = "Reflects whether the channel must issue an interrupt upon the completion of the packet."]
1028    pub mod INTERRUPT {
1029        pub const offset: u32 = 0;
1030        pub const mask: u32 = 0x01 << offset;
1031        pub mod R {}
1032        pub mod W {}
1033        pub mod RW {}
1034    }
1035    #[doc = "Reflects whether the channel's semaphore must be decremented at the end of the current operation"]
1036    pub mod DECR_SEMAPHORE {
1037        pub const offset: u32 = 1;
1038        pub const mask: u32 = 0x01 << offset;
1039        pub mod R {}
1040        pub mod W {}
1041        pub mod RW {}
1042    }
1043    #[doc = "Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer"]
1044    pub mod CHAIN {
1045        pub const offset: u32 = 2;
1046        pub const mask: u32 = 0x01 << offset;
1047        pub mod R {}
1048        pub mod W {}
1049        pub mod RW {}
1050    }
1051    #[doc = "Reflects whether the next packet's address is located following this packet's payload."]
1052    pub mod CHAIN_CONTIGUOUS {
1053        pub const offset: u32 = 3;
1054        pub const mask: u32 = 0x01 << offset;
1055        pub mod R {}
1056        pub mod W {}
1057        pub mod RW {}
1058    }
1059    #[doc = "Reflects whether the selected hashing function should be enabled for this operation."]
1060    pub mod ENABLE_MEMCOPY {
1061        pub const offset: u32 = 4;
1062        pub const mask: u32 = 0x01 << offset;
1063        pub mod R {}
1064        pub mod W {}
1065        pub mod RW {}
1066    }
1067    #[doc = "Reflects whether the selected cipher function must be enabled for this operation."]
1068    pub mod ENABLE_CIPHER {
1069        pub const offset: u32 = 5;
1070        pub const mask: u32 = 0x01 << offset;
1071        pub mod R {}
1072        pub mod W {}
1073        pub mod RW {}
1074    }
1075    #[doc = "Reflects whether the selected hashing function must be enabled for this operation."]
1076    pub mod ENABLE_HASH {
1077        pub const offset: u32 = 6;
1078        pub const mask: u32 = 0x01 << offset;
1079        pub mod R {}
1080        pub mod W {}
1081        pub mod RW {}
1082    }
1083    #[doc = "Reflects whether the DCP must perform a blit operation"]
1084    pub mod ENABLE_BLIT {
1085        pub const offset: u32 = 7;
1086        pub const mask: u32 = 0x01 << offset;
1087        pub mod R {}
1088        pub mod W {}
1089        pub mod RW {}
1090    }
1091    #[doc = "When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption"]
1092    pub mod CIPHER_ENCRYPT {
1093        pub const offset: u32 = 8;
1094        pub const mask: u32 = 0x01 << offset;
1095        pub mod R {}
1096        pub mod W {}
1097        pub mod RW {
1098            #[doc = "DECRYPT"]
1099            pub const DECRYPT: u32 = 0;
1100            #[doc = "ENCRYPT"]
1101            pub const ENCRYPT: u32 = 0x01;
1102        }
1103    }
1104    #[doc = "Reflects whether the cipher block must load the initialization vector from the payload for this operation"]
1105    pub mod CIPHER_INIT {
1106        pub const offset: u32 = 9;
1107        pub const mask: u32 = 0x01 << offset;
1108        pub mod R {}
1109        pub mod W {}
1110        pub mod RW {}
1111    }
1112    #[doc = "Reflects whether a hardware-based key must be used"]
1113    pub mod OTP_KEY {
1114        pub const offset: u32 = 10;
1115        pub const mask: u32 = 0x01 << offset;
1116        pub mod R {}
1117        pub mod W {}
1118        pub mod RW {}
1119    }
1120    #[doc = "When set, it indicates the payload contains the key"]
1121    pub mod PAYLOAD_KEY {
1122        pub const offset: u32 = 11;
1123        pub const mask: u32 = 0x01 << offset;
1124        pub mod R {}
1125        pub mod W {}
1126        pub mod RW {}
1127    }
1128    #[doc = "Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation"]
1129    pub mod HASH_INIT {
1130        pub const offset: u32 = 12;
1131        pub const mask: u32 = 0x01 << offset;
1132        pub mod R {}
1133        pub mod W {}
1134        pub mod RW {}
1135    }
1136    #[doc = "Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware"]
1137    pub mod HASH_TERM {
1138        pub const offset: u32 = 13;
1139        pub const mask: u32 = 0x01 << offset;
1140        pub mod R {}
1141        pub mod W {}
1142        pub mod RW {}
1143    }
1144    #[doc = "Reflects whether the calculated hash value must be compared to the hash provided in the payload."]
1145    pub mod CHECK_HASH {
1146        pub const offset: u32 = 14;
1147        pub const mask: u32 = 0x01 << offset;
1148        pub mod R {}
1149        pub mod W {}
1150        pub mod RW {}
1151    }
1152    #[doc = "When the hashing is enabled, this bit controls whether the input or output data is hashed."]
1153    pub mod HASH_OUTPUT {
1154        pub const offset: u32 = 15;
1155        pub const mask: u32 = 0x01 << offset;
1156        pub mod R {}
1157        pub mod W {}
1158        pub mod RW {
1159            #[doc = "INPUT"]
1160            pub const INPUT: u32 = 0;
1161            #[doc = "OUTPUT"]
1162            pub const OUTPUT: u32 = 0x01;
1163        }
1164    }
1165    #[doc = "When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field"]
1166    pub mod CONSTANT_FILL {
1167        pub const offset: u32 = 16;
1168        pub const mask: u32 = 0x01 << offset;
1169        pub mod R {}
1170        pub mod W {}
1171        pub mod RW {}
1172    }
1173    #[doc = "This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY!"]
1174    pub mod TEST_SEMA_IRQ {
1175        pub const offset: u32 = 17;
1176        pub const mask: u32 = 0x01 << offset;
1177        pub mod R {}
1178        pub mod W {}
1179        pub mod RW {}
1180    }
1181    #[doc = "Reflects whether the DCP engine swaps the key bytes (big-endian key)."]
1182    pub mod KEY_BYTESWAP {
1183        pub const offset: u32 = 18;
1184        pub const mask: u32 = 0x01 << offset;
1185        pub mod R {}
1186        pub mod W {}
1187        pub mod RW {}
1188    }
1189    #[doc = "Reflects whether the DCP engine swaps the key words (big-endian key)."]
1190    pub mod KEY_WORDSWAP {
1191        pub const offset: u32 = 19;
1192        pub const mask: u32 = 0x01 << offset;
1193        pub mod R {}
1194        pub mod W {}
1195        pub mod RW {}
1196    }
1197    #[doc = "Reflects whether the DCP engine byteswaps the input data (big-endian data)."]
1198    pub mod INPUT_BYTESWAP {
1199        pub const offset: u32 = 20;
1200        pub const mask: u32 = 0x01 << offset;
1201        pub mod R {}
1202        pub mod W {}
1203        pub mod RW {}
1204    }
1205    #[doc = "Reflects whether the DCP engine wordswaps the input data (big-endian data)."]
1206    pub mod INPUT_WORDSWAP {
1207        pub const offset: u32 = 21;
1208        pub const mask: u32 = 0x01 << offset;
1209        pub mod R {}
1210        pub mod W {}
1211        pub mod RW {}
1212    }
1213    #[doc = "Reflects whether the DCP engine byteswaps the output data (big-endian data)."]
1214    pub mod OUTPUT_BYTESWAP {
1215        pub const offset: u32 = 22;
1216        pub const mask: u32 = 0x01 << offset;
1217        pub mod R {}
1218        pub mod W {}
1219        pub mod RW {}
1220    }
1221    #[doc = "Reflects whether the DCP engine wordswaps the output data (big-endian data)."]
1222    pub mod OUTPUT_WORDSWAP {
1223        pub const offset: u32 = 23;
1224        pub const mask: u32 = 0x01 << offset;
1225        pub mod R {}
1226        pub mod W {}
1227        pub mod RW {}
1228    }
1229    #[doc = "Packet Tag"]
1230    pub mod TAG {
1231        pub const offset: u32 = 24;
1232        pub const mask: u32 = 0xff << offset;
1233        pub mod R {}
1234        pub mod W {}
1235        pub mod RW {}
1236    }
1237}
1238#[doc = "DCP work packet 2 status register"]
1239pub mod PACKET2 {
1240    #[doc = "Cipher selection field"]
1241    pub mod CIPHER_SELECT {
1242        pub const offset: u32 = 0;
1243        pub const mask: u32 = 0x0f << offset;
1244        pub mod R {}
1245        pub mod W {}
1246        pub mod RW {
1247            #[doc = "AES128"]
1248            pub const AES128: u32 = 0;
1249        }
1250    }
1251    #[doc = "Cipher mode selection field. Reflects the mode of operation for the cipher operations."]
1252    pub mod CIPHER_MODE {
1253        pub const offset: u32 = 4;
1254        pub const mask: u32 = 0x0f << offset;
1255        pub mod R {}
1256        pub mod W {}
1257        pub mod RW {
1258            #[doc = "ECB"]
1259            pub const ECB: u32 = 0;
1260            #[doc = "CBC"]
1261            pub const CBC: u32 = 0x01;
1262        }
1263    }
1264    #[doc = "Key selection field"]
1265    pub mod KEY_SELECT {
1266        pub const offset: u32 = 8;
1267        pub const mask: u32 = 0xff << offset;
1268        pub mod R {}
1269        pub mod W {}
1270        pub mod RW {
1271            #[doc = "KEY0"]
1272            pub const KEY0: u32 = 0;
1273            #[doc = "KEY1"]
1274            pub const KEY1: u32 = 0x01;
1275            #[doc = "KEY2"]
1276            pub const KEY2: u32 = 0x02;
1277            #[doc = "KEY3"]
1278            pub const KEY3: u32 = 0x03;
1279            #[doc = "UNIQUE_KEY"]
1280            pub const UNIQUE_KEY: u32 = 0xfe;
1281            #[doc = "OTP_KEY"]
1282            pub const OTP_KEY: u32 = 0xff;
1283        }
1284    }
1285    #[doc = "Hash Selection Field"]
1286    pub mod HASH_SELECT {
1287        pub const offset: u32 = 16;
1288        pub const mask: u32 = 0x0f << offset;
1289        pub mod R {}
1290        pub mod W {}
1291        pub mod RW {
1292            #[doc = "SHA1"]
1293            pub const SHA1: u32 = 0;
1294            #[doc = "CRC32"]
1295            pub const CRC32: u32 = 0x01;
1296            #[doc = "SHA256"]
1297            pub const SHA256: u32 = 0x02;
1298        }
1299    }
1300    #[doc = "Cipher configuration bits. Optional configuration bits are required for the ciphers."]
1301    pub mod CIPHER_CFG {
1302        pub const offset: u32 = 24;
1303        pub const mask: u32 = 0xff << offset;
1304        pub mod R {}
1305        pub mod W {}
1306        pub mod RW {}
1307    }
1308}
1309#[doc = "DCP work packet 3 status register"]
1310pub mod PACKET3 {
1311    #[doc = "Source buffer address pointer"]
1312    pub mod ADDR {
1313        pub const offset: u32 = 0;
1314        pub const mask: u32 = 0xffff_ffff << offset;
1315        pub mod R {}
1316        pub mod W {}
1317        pub mod RW {}
1318    }
1319}
1320#[doc = "DCP work packet 4 status register"]
1321pub mod PACKET4 {
1322    #[doc = "Destination buffer address pointer"]
1323    pub mod ADDR {
1324        pub const offset: u32 = 0;
1325        pub const mask: u32 = 0xffff_ffff << offset;
1326        pub mod R {}
1327        pub mod W {}
1328        pub mod RW {}
1329    }
1330}
1331#[doc = "DCP work packet 5 status register"]
1332pub mod PACKET5 {
1333    #[doc = "Byte count register. This value is the working value and updates as the operation proceeds."]
1334    pub mod COUNT {
1335        pub const offset: u32 = 0;
1336        pub const mask: u32 = 0xffff_ffff << offset;
1337        pub mod R {}
1338        pub mod W {}
1339        pub mod RW {}
1340    }
1341}
1342#[doc = "DCP work packet 6 status register"]
1343pub mod PACKET6 {
1344    #[doc = "This regiser reflects the payload pointer for the current control packet."]
1345    pub mod ADDR {
1346        pub const offset: u32 = 0;
1347        pub const mask: u32 = 0xffff_ffff << offset;
1348        pub mod R {}
1349        pub mod W {}
1350        pub mod RW {}
1351    }
1352}
1353#[doc = "DCP channel 0 command pointer address register"]
1354pub mod CH0CMDPTR {
1355    #[doc = "Pointer to the descriptor structure to be processed for channel 0."]
1356    pub mod ADDR {
1357        pub const offset: u32 = 0;
1358        pub const mask: u32 = 0xffff_ffff << offset;
1359        pub mod R {}
1360        pub mod W {}
1361        pub mod RW {}
1362    }
1363}
1364#[doc = "DCP channel 0 semaphore register"]
1365pub mod CH0SEMA {
1366    #[doc = "The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected"]
1367    pub mod INCREMENT {
1368        pub const offset: u32 = 0;
1369        pub const mask: u32 = 0xff << offset;
1370        pub mod R {}
1371        pub mod W {}
1372        pub mod RW {}
1373    }
1374    #[doc = "This read-only field shows the current (instantaneous) value of the semaphore counter."]
1375    pub mod VALUE {
1376        pub const offset: u32 = 16;
1377        pub const mask: u32 = 0xff << offset;
1378        pub mod R {}
1379        pub mod W {}
1380        pub mod RW {}
1381    }
1382}
1383#[doc = "DCP channel 0 status register"]
1384pub mod CH0STAT {
1385    #[doc = "This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit"]
1386    pub mod HASH_MISMATCH {
1387        pub const offset: u32 = 1;
1388        pub const mask: u32 = 0x01 << offset;
1389        pub mod R {}
1390        pub mod W {}
1391        pub mod RW {}
1392    }
1393    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
1394    pub mod ERROR_SETUP {
1395        pub const offset: u32 = 2;
1396        pub const mask: u32 = 0x01 << offset;
1397        pub mod R {}
1398        pub mod W {}
1399        pub mod RW {}
1400    }
1401    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload"]
1402    pub mod ERROR_PACKET {
1403        pub const offset: u32 = 3;
1404        pub const mask: u32 = 0x01 << offset;
1405        pub mod R {}
1406        pub mod W {}
1407        pub mod RW {}
1408    }
1409    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
1410    pub mod ERROR_SRC {
1411        pub const offset: u32 = 4;
1412        pub const mask: u32 = 0x01 << offset;
1413        pub mod R {}
1414        pub mod W {}
1415        pub mod RW {}
1416    }
1417    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
1418    pub mod ERROR_DST {
1419        pub const offset: u32 = 5;
1420        pub const mask: u32 = 0x01 << offset;
1421        pub mod R {}
1422        pub mod W {}
1423        pub mod RW {}
1424    }
1425    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
1426    pub mod ERROR_PAGEFAULT {
1427        pub const offset: u32 = 6;
1428        pub const mask: u32 = 0x01 << offset;
1429        pub mod R {}
1430        pub mod W {}
1431        pub mod RW {}
1432    }
1433    #[doc = "Indicates the additional error codes for some of the error conditions"]
1434    pub mod ERROR_CODE {
1435        pub const offset: u32 = 16;
1436        pub const mask: u32 = 0xff << offset;
1437        pub mod R {}
1438        pub mod W {}
1439        pub mod RW {
1440            #[doc = "Error signalled because the next pointer is 0x00000000"]
1441            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
1442            #[doc = "Error signalled because the semaphore is non-zero and neither chain bit is set"]
1443            pub const NO_CHAIN: u32 = 0x02;
1444            #[doc = "Error signalled because an error is reported reading/writing the context buffer"]
1445            pub const CONTEXT_ERROR: u32 = 0x03;
1446            #[doc = "Error signalled because an error is reported reading/writing the payload"]
1447            pub const PAYLOAD_ERROR: u32 = 0x04;
1448            #[doc = "Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)"]
1449            pub const INVALID_MODE: u32 = 0x05;
1450        }
1451    }
1452    #[doc = "Indicates the tag from the last completed packet in the command structure"]
1453    pub mod TAG {
1454        pub const offset: u32 = 24;
1455        pub const mask: u32 = 0xff << offset;
1456        pub mod R {}
1457        pub mod W {}
1458        pub mod RW {}
1459    }
1460}
1461#[doc = "DCP channel 0 status register"]
1462pub mod CH0STAT_SET {
1463    #[doc = "This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit"]
1464    pub mod HASH_MISMATCH {
1465        pub const offset: u32 = 1;
1466        pub const mask: u32 = 0x01 << offset;
1467        pub mod R {}
1468        pub mod W {}
1469        pub mod RW {}
1470    }
1471    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
1472    pub mod ERROR_SETUP {
1473        pub const offset: u32 = 2;
1474        pub const mask: u32 = 0x01 << offset;
1475        pub mod R {}
1476        pub mod W {}
1477        pub mod RW {}
1478    }
1479    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload"]
1480    pub mod ERROR_PACKET {
1481        pub const offset: u32 = 3;
1482        pub const mask: u32 = 0x01 << offset;
1483        pub mod R {}
1484        pub mod W {}
1485        pub mod RW {}
1486    }
1487    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
1488    pub mod ERROR_SRC {
1489        pub const offset: u32 = 4;
1490        pub const mask: u32 = 0x01 << offset;
1491        pub mod R {}
1492        pub mod W {}
1493        pub mod RW {}
1494    }
1495    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
1496    pub mod ERROR_DST {
1497        pub const offset: u32 = 5;
1498        pub const mask: u32 = 0x01 << offset;
1499        pub mod R {}
1500        pub mod W {}
1501        pub mod RW {}
1502    }
1503    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
1504    pub mod ERROR_PAGEFAULT {
1505        pub const offset: u32 = 6;
1506        pub const mask: u32 = 0x01 << offset;
1507        pub mod R {}
1508        pub mod W {}
1509        pub mod RW {}
1510    }
1511    #[doc = "Indicates the additional error codes for some of the error conditions"]
1512    pub mod ERROR_CODE {
1513        pub const offset: u32 = 16;
1514        pub const mask: u32 = 0xff << offset;
1515        pub mod R {}
1516        pub mod W {}
1517        pub mod RW {
1518            #[doc = "Error signalled because the next pointer is 0x00000000"]
1519            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
1520            #[doc = "Error signalled because the semaphore is non-zero and neither chain bit is set"]
1521            pub const NO_CHAIN: u32 = 0x02;
1522            #[doc = "Error signalled because an error is reported reading/writing the context buffer"]
1523            pub const CONTEXT_ERROR: u32 = 0x03;
1524            #[doc = "Error signalled because an error is reported reading/writing the payload"]
1525            pub const PAYLOAD_ERROR: u32 = 0x04;
1526            #[doc = "Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)"]
1527            pub const INVALID_MODE: u32 = 0x05;
1528        }
1529    }
1530    #[doc = "Indicates the tag from the last completed packet in the command structure"]
1531    pub mod TAG {
1532        pub const offset: u32 = 24;
1533        pub const mask: u32 = 0xff << offset;
1534        pub mod R {}
1535        pub mod W {}
1536        pub mod RW {}
1537    }
1538}
1539#[doc = "DCP channel 0 status register"]
1540pub mod CH0STAT_CLR {
1541    #[doc = "This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit"]
1542    pub mod HASH_MISMATCH {
1543        pub const offset: u32 = 1;
1544        pub const mask: u32 = 0x01 << offset;
1545        pub mod R {}
1546        pub mod W {}
1547        pub mod RW {}
1548    }
1549    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
1550    pub mod ERROR_SETUP {
1551        pub const offset: u32 = 2;
1552        pub const mask: u32 = 0x01 << offset;
1553        pub mod R {}
1554        pub mod W {}
1555        pub mod RW {}
1556    }
1557    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload"]
1558    pub mod ERROR_PACKET {
1559        pub const offset: u32 = 3;
1560        pub const mask: u32 = 0x01 << offset;
1561        pub mod R {}
1562        pub mod W {}
1563        pub mod RW {}
1564    }
1565    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
1566    pub mod ERROR_SRC {
1567        pub const offset: u32 = 4;
1568        pub const mask: u32 = 0x01 << offset;
1569        pub mod R {}
1570        pub mod W {}
1571        pub mod RW {}
1572    }
1573    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
1574    pub mod ERROR_DST {
1575        pub const offset: u32 = 5;
1576        pub const mask: u32 = 0x01 << offset;
1577        pub mod R {}
1578        pub mod W {}
1579        pub mod RW {}
1580    }
1581    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
1582    pub mod ERROR_PAGEFAULT {
1583        pub const offset: u32 = 6;
1584        pub const mask: u32 = 0x01 << offset;
1585        pub mod R {}
1586        pub mod W {}
1587        pub mod RW {}
1588    }
1589    #[doc = "Indicates the additional error codes for some of the error conditions"]
1590    pub mod ERROR_CODE {
1591        pub const offset: u32 = 16;
1592        pub const mask: u32 = 0xff << offset;
1593        pub mod R {}
1594        pub mod W {}
1595        pub mod RW {
1596            #[doc = "Error signalled because the next pointer is 0x00000000"]
1597            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
1598            #[doc = "Error signalled because the semaphore is non-zero and neither chain bit is set"]
1599            pub const NO_CHAIN: u32 = 0x02;
1600            #[doc = "Error signalled because an error is reported reading/writing the context buffer"]
1601            pub const CONTEXT_ERROR: u32 = 0x03;
1602            #[doc = "Error signalled because an error is reported reading/writing the payload"]
1603            pub const PAYLOAD_ERROR: u32 = 0x04;
1604            #[doc = "Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)"]
1605            pub const INVALID_MODE: u32 = 0x05;
1606        }
1607    }
1608    #[doc = "Indicates the tag from the last completed packet in the command structure"]
1609    pub mod TAG {
1610        pub const offset: u32 = 24;
1611        pub const mask: u32 = 0xff << offset;
1612        pub mod R {}
1613        pub mod W {}
1614        pub mod RW {}
1615    }
1616}
1617#[doc = "DCP channel 0 status register"]
1618pub mod CH0STAT_TOG {
1619    #[doc = "This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit"]
1620    pub mod HASH_MISMATCH {
1621        pub const offset: u32 = 1;
1622        pub const mask: u32 = 0x01 << offset;
1623        pub mod R {}
1624        pub mod W {}
1625        pub mod RW {}
1626    }
1627    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
1628    pub mod ERROR_SETUP {
1629        pub const offset: u32 = 2;
1630        pub const mask: u32 = 0x01 << offset;
1631        pub mod R {}
1632        pub mod W {}
1633        pub mod RW {}
1634    }
1635    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload"]
1636    pub mod ERROR_PACKET {
1637        pub const offset: u32 = 3;
1638        pub const mask: u32 = 0x01 << offset;
1639        pub mod R {}
1640        pub mod W {}
1641        pub mod RW {}
1642    }
1643    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
1644    pub mod ERROR_SRC {
1645        pub const offset: u32 = 4;
1646        pub const mask: u32 = 0x01 << offset;
1647        pub mod R {}
1648        pub mod W {}
1649        pub mod RW {}
1650    }
1651    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
1652    pub mod ERROR_DST {
1653        pub const offset: u32 = 5;
1654        pub const mask: u32 = 0x01 << offset;
1655        pub mod R {}
1656        pub mod W {}
1657        pub mod RW {}
1658    }
1659    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
1660    pub mod ERROR_PAGEFAULT {
1661        pub const offset: u32 = 6;
1662        pub const mask: u32 = 0x01 << offset;
1663        pub mod R {}
1664        pub mod W {}
1665        pub mod RW {}
1666    }
1667    #[doc = "Indicates the additional error codes for some of the error conditions"]
1668    pub mod ERROR_CODE {
1669        pub const offset: u32 = 16;
1670        pub const mask: u32 = 0xff << offset;
1671        pub mod R {}
1672        pub mod W {}
1673        pub mod RW {
1674            #[doc = "Error signalled because the next pointer is 0x00000000"]
1675            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
1676            #[doc = "Error signalled because the semaphore is non-zero and neither chain bit is set"]
1677            pub const NO_CHAIN: u32 = 0x02;
1678            #[doc = "Error signalled because an error is reported reading/writing the context buffer"]
1679            pub const CONTEXT_ERROR: u32 = 0x03;
1680            #[doc = "Error signalled because an error is reported reading/writing the payload"]
1681            pub const PAYLOAD_ERROR: u32 = 0x04;
1682            #[doc = "Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)"]
1683            pub const INVALID_MODE: u32 = 0x05;
1684        }
1685    }
1686    #[doc = "Indicates the tag from the last completed packet in the command structure"]
1687    pub mod TAG {
1688        pub const offset: u32 = 24;
1689        pub const mask: u32 = 0xff << offset;
1690        pub mod R {}
1691        pub mod W {}
1692        pub mod RW {}
1693    }
1694}
1695#[doc = "DCP channel 0 options register"]
1696pub mod CH0OPTS {
1697    #[doc = "This field indicates the recovery time for the channel"]
1698    pub mod RECOVERY_TIMER {
1699        pub const offset: u32 = 0;
1700        pub const mask: u32 = 0xffff << offset;
1701        pub mod R {}
1702        pub mod W {}
1703        pub mod RW {}
1704    }
1705}
1706#[doc = "DCP channel 0 options register"]
1707pub mod CH0OPTS_SET {
1708    #[doc = "This field indicates the recovery time for the channel"]
1709    pub mod RECOVERY_TIMER {
1710        pub const offset: u32 = 0;
1711        pub const mask: u32 = 0xffff << offset;
1712        pub mod R {}
1713        pub mod W {}
1714        pub mod RW {}
1715    }
1716}
1717#[doc = "DCP channel 0 options register"]
1718pub mod CH0OPTS_CLR {
1719    #[doc = "This field indicates the recovery time for the channel"]
1720    pub mod RECOVERY_TIMER {
1721        pub const offset: u32 = 0;
1722        pub const mask: u32 = 0xffff << offset;
1723        pub mod R {}
1724        pub mod W {}
1725        pub mod RW {}
1726    }
1727}
1728#[doc = "DCP channel 0 options register"]
1729pub mod CH0OPTS_TOG {
1730    #[doc = "This field indicates the recovery time for the channel"]
1731    pub mod RECOVERY_TIMER {
1732        pub const offset: u32 = 0;
1733        pub const mask: u32 = 0xffff << offset;
1734        pub mod R {}
1735        pub mod W {}
1736        pub mod RW {}
1737    }
1738}
1739#[doc = "DCP channel 1 command pointer address register"]
1740pub mod CH1CMDPTR {
1741    #[doc = "Pointer to the descriptor structure to be processed for channel 1."]
1742    pub mod ADDR {
1743        pub const offset: u32 = 0;
1744        pub const mask: u32 = 0xffff_ffff << offset;
1745        pub mod R {}
1746        pub mod W {}
1747        pub mod RW {}
1748    }
1749}
1750#[doc = "DCP channel 1 semaphore register"]
1751pub mod CH1SEMA {
1752    #[doc = "The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected"]
1753    pub mod INCREMENT {
1754        pub const offset: u32 = 0;
1755        pub const mask: u32 = 0xff << offset;
1756        pub mod R {}
1757        pub mod W {}
1758        pub mod RW {}
1759    }
1760    #[doc = "This read-only field shows the current (instantaneous) value of the semaphore counter."]
1761    pub mod VALUE {
1762        pub const offset: u32 = 16;
1763        pub const mask: u32 = 0xff << offset;
1764        pub mod R {}
1765        pub mod W {}
1766        pub mod RW {}
1767    }
1768}
1769#[doc = "DCP channel 1 status register"]
1770pub mod CH1STAT {
1771    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
1772    pub mod HASH_MISMATCH {
1773        pub const offset: u32 = 1;
1774        pub const mask: u32 = 0x01 << offset;
1775        pub mod R {}
1776        pub mod W {}
1777        pub mod RW {}
1778    }
1779    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
1780    pub mod ERROR_SETUP {
1781        pub const offset: u32 = 2;
1782        pub const mask: u32 = 0x01 << offset;
1783        pub mod R {}
1784        pub mod W {}
1785        pub mod RW {}
1786    }
1787    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
1788    pub mod ERROR_PACKET {
1789        pub const offset: u32 = 3;
1790        pub const mask: u32 = 0x01 << offset;
1791        pub mod R {}
1792        pub mod W {}
1793        pub mod RW {}
1794    }
1795    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
1796    pub mod ERROR_SRC {
1797        pub const offset: u32 = 4;
1798        pub const mask: u32 = 0x01 << offset;
1799        pub mod R {}
1800        pub mod W {}
1801        pub mod RW {}
1802    }
1803    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
1804    pub mod ERROR_DST {
1805        pub const offset: u32 = 5;
1806        pub const mask: u32 = 0x01 << offset;
1807        pub mod R {}
1808        pub mod W {}
1809        pub mod RW {}
1810    }
1811    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
1812    pub mod ERROR_PAGEFAULT {
1813        pub const offset: u32 = 6;
1814        pub const mask: u32 = 0x01 << offset;
1815        pub mod R {}
1816        pub mod W {}
1817        pub mod RW {}
1818    }
1819    #[doc = "Indicates the additional error codes for some of the error conditions."]
1820    pub mod ERROR_CODE {
1821        pub const offset: u32 = 16;
1822        pub const mask: u32 = 0xff << offset;
1823        pub mod R {}
1824        pub mod W {}
1825        pub mod RW {
1826            #[doc = "Error is signalled because the next pointer is 0x00000000."]
1827            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
1828            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
1829            pub const NO_CHAIN: u32 = 0x02;
1830            #[doc = "Error is signalled because an error was reported when reading/writing the context buffer."]
1831            pub const CONTEXT_ERROR: u32 = 0x03;
1832            #[doc = "Error is signalled because an error was reported when reading/writing the payload."]
1833            pub const PAYLOAD_ERROR: u32 = 0x04;
1834            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
1835            pub const INVALID_MODE: u32 = 0x05;
1836        }
1837    }
1838    #[doc = "Indicates the tag from the last completed packet in the command structure."]
1839    pub mod TAG {
1840        pub const offset: u32 = 24;
1841        pub const mask: u32 = 0xff << offset;
1842        pub mod R {}
1843        pub mod W {}
1844        pub mod RW {}
1845    }
1846}
1847#[doc = "DCP channel 1 status register"]
1848pub mod CH1STAT_SET {
1849    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
1850    pub mod HASH_MISMATCH {
1851        pub const offset: u32 = 1;
1852        pub const mask: u32 = 0x01 << offset;
1853        pub mod R {}
1854        pub mod W {}
1855        pub mod RW {}
1856    }
1857    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
1858    pub mod ERROR_SETUP {
1859        pub const offset: u32 = 2;
1860        pub const mask: u32 = 0x01 << offset;
1861        pub mod R {}
1862        pub mod W {}
1863        pub mod RW {}
1864    }
1865    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
1866    pub mod ERROR_PACKET {
1867        pub const offset: u32 = 3;
1868        pub const mask: u32 = 0x01 << offset;
1869        pub mod R {}
1870        pub mod W {}
1871        pub mod RW {}
1872    }
1873    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
1874    pub mod ERROR_SRC {
1875        pub const offset: u32 = 4;
1876        pub const mask: u32 = 0x01 << offset;
1877        pub mod R {}
1878        pub mod W {}
1879        pub mod RW {}
1880    }
1881    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
1882    pub mod ERROR_DST {
1883        pub const offset: u32 = 5;
1884        pub const mask: u32 = 0x01 << offset;
1885        pub mod R {}
1886        pub mod W {}
1887        pub mod RW {}
1888    }
1889    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
1890    pub mod ERROR_PAGEFAULT {
1891        pub const offset: u32 = 6;
1892        pub const mask: u32 = 0x01 << offset;
1893        pub mod R {}
1894        pub mod W {}
1895        pub mod RW {}
1896    }
1897    #[doc = "Indicates the additional error codes for some of the error conditions."]
1898    pub mod ERROR_CODE {
1899        pub const offset: u32 = 16;
1900        pub const mask: u32 = 0xff << offset;
1901        pub mod R {}
1902        pub mod W {}
1903        pub mod RW {
1904            #[doc = "Error is signalled because the next pointer is 0x00000000."]
1905            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
1906            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
1907            pub const NO_CHAIN: u32 = 0x02;
1908            #[doc = "Error is signalled because an error was reported when reading/writing the context buffer."]
1909            pub const CONTEXT_ERROR: u32 = 0x03;
1910            #[doc = "Error is signalled because an error was reported when reading/writing the payload."]
1911            pub const PAYLOAD_ERROR: u32 = 0x04;
1912            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
1913            pub const INVALID_MODE: u32 = 0x05;
1914        }
1915    }
1916    #[doc = "Indicates the tag from the last completed packet in the command structure."]
1917    pub mod TAG {
1918        pub const offset: u32 = 24;
1919        pub const mask: u32 = 0xff << offset;
1920        pub mod R {}
1921        pub mod W {}
1922        pub mod RW {}
1923    }
1924}
1925#[doc = "DCP channel 1 status register"]
1926pub mod CH1STAT_CLR {
1927    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
1928    pub mod HASH_MISMATCH {
1929        pub const offset: u32 = 1;
1930        pub const mask: u32 = 0x01 << offset;
1931        pub mod R {}
1932        pub mod W {}
1933        pub mod RW {}
1934    }
1935    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
1936    pub mod ERROR_SETUP {
1937        pub const offset: u32 = 2;
1938        pub const mask: u32 = 0x01 << offset;
1939        pub mod R {}
1940        pub mod W {}
1941        pub mod RW {}
1942    }
1943    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
1944    pub mod ERROR_PACKET {
1945        pub const offset: u32 = 3;
1946        pub const mask: u32 = 0x01 << offset;
1947        pub mod R {}
1948        pub mod W {}
1949        pub mod RW {}
1950    }
1951    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
1952    pub mod ERROR_SRC {
1953        pub const offset: u32 = 4;
1954        pub const mask: u32 = 0x01 << offset;
1955        pub mod R {}
1956        pub mod W {}
1957        pub mod RW {}
1958    }
1959    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
1960    pub mod ERROR_DST {
1961        pub const offset: u32 = 5;
1962        pub const mask: u32 = 0x01 << offset;
1963        pub mod R {}
1964        pub mod W {}
1965        pub mod RW {}
1966    }
1967    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
1968    pub mod ERROR_PAGEFAULT {
1969        pub const offset: u32 = 6;
1970        pub const mask: u32 = 0x01 << offset;
1971        pub mod R {}
1972        pub mod W {}
1973        pub mod RW {}
1974    }
1975    #[doc = "Indicates the additional error codes for some of the error conditions."]
1976    pub mod ERROR_CODE {
1977        pub const offset: u32 = 16;
1978        pub const mask: u32 = 0xff << offset;
1979        pub mod R {}
1980        pub mod W {}
1981        pub mod RW {
1982            #[doc = "Error is signalled because the next pointer is 0x00000000."]
1983            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
1984            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
1985            pub const NO_CHAIN: u32 = 0x02;
1986            #[doc = "Error is signalled because an error was reported when reading/writing the context buffer."]
1987            pub const CONTEXT_ERROR: u32 = 0x03;
1988            #[doc = "Error is signalled because an error was reported when reading/writing the payload."]
1989            pub const PAYLOAD_ERROR: u32 = 0x04;
1990            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
1991            pub const INVALID_MODE: u32 = 0x05;
1992        }
1993    }
1994    #[doc = "Indicates the tag from the last completed packet in the command structure."]
1995    pub mod TAG {
1996        pub const offset: u32 = 24;
1997        pub const mask: u32 = 0xff << offset;
1998        pub mod R {}
1999        pub mod W {}
2000        pub mod RW {}
2001    }
2002}
2003#[doc = "DCP channel 1 status register"]
2004pub mod CH1STAT_TOG {
2005    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2006    pub mod HASH_MISMATCH {
2007        pub const offset: u32 = 1;
2008        pub const mask: u32 = 0x01 << offset;
2009        pub mod R {}
2010        pub mod W {}
2011        pub mod RW {}
2012    }
2013    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2014    pub mod ERROR_SETUP {
2015        pub const offset: u32 = 2;
2016        pub const mask: u32 = 0x01 << offset;
2017        pub mod R {}
2018        pub mod W {}
2019        pub mod RW {}
2020    }
2021    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
2022    pub mod ERROR_PACKET {
2023        pub const offset: u32 = 3;
2024        pub const mask: u32 = 0x01 << offset;
2025        pub mod R {}
2026        pub mod W {}
2027        pub mod RW {}
2028    }
2029    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2030    pub mod ERROR_SRC {
2031        pub const offset: u32 = 4;
2032        pub const mask: u32 = 0x01 << offset;
2033        pub mod R {}
2034        pub mod W {}
2035        pub mod RW {}
2036    }
2037    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2038    pub mod ERROR_DST {
2039        pub const offset: u32 = 5;
2040        pub const mask: u32 = 0x01 << offset;
2041        pub mod R {}
2042        pub mod W {}
2043        pub mod RW {}
2044    }
2045    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2046    pub mod ERROR_PAGEFAULT {
2047        pub const offset: u32 = 6;
2048        pub const mask: u32 = 0x01 << offset;
2049        pub mod R {}
2050        pub mod W {}
2051        pub mod RW {}
2052    }
2053    #[doc = "Indicates the additional error codes for some of the error conditions."]
2054    pub mod ERROR_CODE {
2055        pub const offset: u32 = 16;
2056        pub const mask: u32 = 0xff << offset;
2057        pub mod R {}
2058        pub mod W {}
2059        pub mod RW {
2060            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2061            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2062            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2063            pub const NO_CHAIN: u32 = 0x02;
2064            #[doc = "Error is signalled because an error was reported when reading/writing the context buffer."]
2065            pub const CONTEXT_ERROR: u32 = 0x03;
2066            #[doc = "Error is signalled because an error was reported when reading/writing the payload."]
2067            pub const PAYLOAD_ERROR: u32 = 0x04;
2068            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
2069            pub const INVALID_MODE: u32 = 0x05;
2070        }
2071    }
2072    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2073    pub mod TAG {
2074        pub const offset: u32 = 24;
2075        pub const mask: u32 = 0xff << offset;
2076        pub mod R {}
2077        pub mod W {}
2078        pub mod RW {}
2079    }
2080}
2081#[doc = "DCP channel 1 options register"]
2082pub mod CH1OPTS {
2083    #[doc = "This field indicates the recovery time for the channel"]
2084    pub mod RECOVERY_TIMER {
2085        pub const offset: u32 = 0;
2086        pub const mask: u32 = 0xffff << offset;
2087        pub mod R {}
2088        pub mod W {}
2089        pub mod RW {}
2090    }
2091}
2092#[doc = "DCP channel 1 options register"]
2093pub mod CH1OPTS_SET {
2094    #[doc = "This field indicates the recovery time for the channel"]
2095    pub mod RECOVERY_TIMER {
2096        pub const offset: u32 = 0;
2097        pub const mask: u32 = 0xffff << offset;
2098        pub mod R {}
2099        pub mod W {}
2100        pub mod RW {}
2101    }
2102}
2103#[doc = "DCP channel 1 options register"]
2104pub mod CH1OPTS_CLR {
2105    #[doc = "This field indicates the recovery time for the channel"]
2106    pub mod RECOVERY_TIMER {
2107        pub const offset: u32 = 0;
2108        pub const mask: u32 = 0xffff << offset;
2109        pub mod R {}
2110        pub mod W {}
2111        pub mod RW {}
2112    }
2113}
2114#[doc = "DCP channel 1 options register"]
2115pub mod CH1OPTS_TOG {
2116    #[doc = "This field indicates the recovery time for the channel"]
2117    pub mod RECOVERY_TIMER {
2118        pub const offset: u32 = 0;
2119        pub const mask: u32 = 0xffff << offset;
2120        pub mod R {}
2121        pub mod W {}
2122        pub mod RW {}
2123    }
2124}
2125#[doc = "DCP channel 2 command pointer address register"]
2126pub mod CH2CMDPTR {
2127    #[doc = "Pointer to the descriptor structure to be processed for channel 2."]
2128    pub mod ADDR {
2129        pub const offset: u32 = 0;
2130        pub const mask: u32 = 0xffff_ffff << offset;
2131        pub mod R {}
2132        pub mod W {}
2133        pub mod RW {}
2134    }
2135}
2136#[doc = "DCP channel 2 semaphore register"]
2137pub mod CH2SEMA {
2138    #[doc = "The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected"]
2139    pub mod INCREMENT {
2140        pub const offset: u32 = 0;
2141        pub const mask: u32 = 0xff << offset;
2142        pub mod R {}
2143        pub mod W {}
2144        pub mod RW {}
2145    }
2146    #[doc = "This read-only field shows the current (instantaneous) value of the semaphore counter."]
2147    pub mod VALUE {
2148        pub const offset: u32 = 16;
2149        pub const mask: u32 = 0xff << offset;
2150        pub mod R {}
2151        pub mod W {}
2152        pub mod RW {}
2153    }
2154}
2155#[doc = "DCP channel 2 status register"]
2156pub mod CH2STAT {
2157    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2158    pub mod HASH_MISMATCH {
2159        pub const offset: u32 = 1;
2160        pub const mask: u32 = 0x01 << offset;
2161        pub mod R {}
2162        pub mod W {}
2163        pub mod RW {}
2164    }
2165    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2166    pub mod ERROR_SETUP {
2167        pub const offset: u32 = 2;
2168        pub const mask: u32 = 0x01 << offset;
2169        pub mod R {}
2170        pub mod W {}
2171        pub mod RW {}
2172    }
2173    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
2174    pub mod ERROR_PACKET {
2175        pub const offset: u32 = 3;
2176        pub const mask: u32 = 0x01 << offset;
2177        pub mod R {}
2178        pub mod W {}
2179        pub mod RW {}
2180    }
2181    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2182    pub mod ERROR_SRC {
2183        pub const offset: u32 = 4;
2184        pub const mask: u32 = 0x01 << offset;
2185        pub mod R {}
2186        pub mod W {}
2187        pub mod RW {}
2188    }
2189    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2190    pub mod ERROR_DST {
2191        pub const offset: u32 = 5;
2192        pub const mask: u32 = 0x01 << offset;
2193        pub mod R {}
2194        pub mod W {}
2195        pub mod RW {}
2196    }
2197    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2198    pub mod ERROR_PAGEFAULT {
2199        pub const offset: u32 = 6;
2200        pub const mask: u32 = 0x01 << offset;
2201        pub mod R {}
2202        pub mod W {}
2203        pub mod RW {}
2204    }
2205    #[doc = "Indicates additional error codes for some of the error conditions."]
2206    pub mod ERROR_CODE {
2207        pub const offset: u32 = 16;
2208        pub const mask: u32 = 0xff << offset;
2209        pub mod R {}
2210        pub mod W {}
2211        pub mod RW {
2212            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2213            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2214            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2215            pub const NO_CHAIN: u32 = 0x02;
2216            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2217            pub const CONTEXT_ERROR: u32 = 0x03;
2218            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2219            pub const PAYLOAD_ERROR: u32 = 0x04;
2220            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash)."]
2221            pub const INVALID_MODE: u32 = 0x05;
2222        }
2223    }
2224    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2225    pub mod TAG {
2226        pub const offset: u32 = 24;
2227        pub const mask: u32 = 0xff << offset;
2228        pub mod R {}
2229        pub mod W {}
2230        pub mod RW {}
2231    }
2232}
2233#[doc = "DCP channel 2 status register"]
2234pub mod CH2STAT_SET {
2235    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2236    pub mod HASH_MISMATCH {
2237        pub const offset: u32 = 1;
2238        pub const mask: u32 = 0x01 << offset;
2239        pub mod R {}
2240        pub mod W {}
2241        pub mod RW {}
2242    }
2243    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2244    pub mod ERROR_SETUP {
2245        pub const offset: u32 = 2;
2246        pub const mask: u32 = 0x01 << offset;
2247        pub mod R {}
2248        pub mod W {}
2249        pub mod RW {}
2250    }
2251    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
2252    pub mod ERROR_PACKET {
2253        pub const offset: u32 = 3;
2254        pub const mask: u32 = 0x01 << offset;
2255        pub mod R {}
2256        pub mod W {}
2257        pub mod RW {}
2258    }
2259    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2260    pub mod ERROR_SRC {
2261        pub const offset: u32 = 4;
2262        pub const mask: u32 = 0x01 << offset;
2263        pub mod R {}
2264        pub mod W {}
2265        pub mod RW {}
2266    }
2267    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2268    pub mod ERROR_DST {
2269        pub const offset: u32 = 5;
2270        pub const mask: u32 = 0x01 << offset;
2271        pub mod R {}
2272        pub mod W {}
2273        pub mod RW {}
2274    }
2275    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2276    pub mod ERROR_PAGEFAULT {
2277        pub const offset: u32 = 6;
2278        pub const mask: u32 = 0x01 << offset;
2279        pub mod R {}
2280        pub mod W {}
2281        pub mod RW {}
2282    }
2283    #[doc = "Indicates additional error codes for some of the error conditions."]
2284    pub mod ERROR_CODE {
2285        pub const offset: u32 = 16;
2286        pub const mask: u32 = 0xff << offset;
2287        pub mod R {}
2288        pub mod W {}
2289        pub mod RW {
2290            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2291            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2292            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2293            pub const NO_CHAIN: u32 = 0x02;
2294            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2295            pub const CONTEXT_ERROR: u32 = 0x03;
2296            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2297            pub const PAYLOAD_ERROR: u32 = 0x04;
2298            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash)."]
2299            pub const INVALID_MODE: u32 = 0x05;
2300        }
2301    }
2302    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2303    pub mod TAG {
2304        pub const offset: u32 = 24;
2305        pub const mask: u32 = 0xff << offset;
2306        pub mod R {}
2307        pub mod W {}
2308        pub mod RW {}
2309    }
2310}
2311#[doc = "DCP channel 2 status register"]
2312pub mod CH2STAT_CLR {
2313    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2314    pub mod HASH_MISMATCH {
2315        pub const offset: u32 = 1;
2316        pub const mask: u32 = 0x01 << offset;
2317        pub mod R {}
2318        pub mod W {}
2319        pub mod RW {}
2320    }
2321    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2322    pub mod ERROR_SETUP {
2323        pub const offset: u32 = 2;
2324        pub const mask: u32 = 0x01 << offset;
2325        pub mod R {}
2326        pub mod W {}
2327        pub mod RW {}
2328    }
2329    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
2330    pub mod ERROR_PACKET {
2331        pub const offset: u32 = 3;
2332        pub const mask: u32 = 0x01 << offset;
2333        pub mod R {}
2334        pub mod W {}
2335        pub mod RW {}
2336    }
2337    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2338    pub mod ERROR_SRC {
2339        pub const offset: u32 = 4;
2340        pub const mask: u32 = 0x01 << offset;
2341        pub mod R {}
2342        pub mod W {}
2343        pub mod RW {}
2344    }
2345    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2346    pub mod ERROR_DST {
2347        pub const offset: u32 = 5;
2348        pub const mask: u32 = 0x01 << offset;
2349        pub mod R {}
2350        pub mod W {}
2351        pub mod RW {}
2352    }
2353    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2354    pub mod ERROR_PAGEFAULT {
2355        pub const offset: u32 = 6;
2356        pub const mask: u32 = 0x01 << offset;
2357        pub mod R {}
2358        pub mod W {}
2359        pub mod RW {}
2360    }
2361    #[doc = "Indicates additional error codes for some of the error conditions."]
2362    pub mod ERROR_CODE {
2363        pub const offset: u32 = 16;
2364        pub const mask: u32 = 0xff << offset;
2365        pub mod R {}
2366        pub mod W {}
2367        pub mod RW {
2368            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2369            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2370            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2371            pub const NO_CHAIN: u32 = 0x02;
2372            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2373            pub const CONTEXT_ERROR: u32 = 0x03;
2374            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2375            pub const PAYLOAD_ERROR: u32 = 0x04;
2376            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash)."]
2377            pub const INVALID_MODE: u32 = 0x05;
2378        }
2379    }
2380    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2381    pub mod TAG {
2382        pub const offset: u32 = 24;
2383        pub const mask: u32 = 0xff << offset;
2384        pub mod R {}
2385        pub mod W {}
2386        pub mod RW {}
2387    }
2388}
2389#[doc = "DCP channel 2 status register"]
2390pub mod CH2STAT_TOG {
2391    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2392    pub mod HASH_MISMATCH {
2393        pub const offset: u32 = 1;
2394        pub const mask: u32 = 0x01 << offset;
2395        pub mod R {}
2396        pub mod W {}
2397        pub mod RW {}
2398    }
2399    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2400    pub mod ERROR_SETUP {
2401        pub const offset: u32 = 2;
2402        pub const mask: u32 = 0x01 << offset;
2403        pub mod R {}
2404        pub mod W {}
2405        pub mod RW {}
2406    }
2407    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod"]
2408    pub mod ERROR_PACKET {
2409        pub const offset: u32 = 3;
2410        pub const mask: u32 = 0x01 << offset;
2411        pub mod R {}
2412        pub mod W {}
2413        pub mod RW {}
2414    }
2415    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2416    pub mod ERROR_SRC {
2417        pub const offset: u32 = 4;
2418        pub const mask: u32 = 0x01 << offset;
2419        pub mod R {}
2420        pub mod W {}
2421        pub mod RW {}
2422    }
2423    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2424    pub mod ERROR_DST {
2425        pub const offset: u32 = 5;
2426        pub const mask: u32 = 0x01 << offset;
2427        pub mod R {}
2428        pub mod W {}
2429        pub mod RW {}
2430    }
2431    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2432    pub mod ERROR_PAGEFAULT {
2433        pub const offset: u32 = 6;
2434        pub const mask: u32 = 0x01 << offset;
2435        pub mod R {}
2436        pub mod W {}
2437        pub mod RW {}
2438    }
2439    #[doc = "Indicates additional error codes for some of the error conditions."]
2440    pub mod ERROR_CODE {
2441        pub const offset: u32 = 16;
2442        pub const mask: u32 = 0xff << offset;
2443        pub mod R {}
2444        pub mod W {}
2445        pub mod RW {
2446            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2447            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2448            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2449            pub const NO_CHAIN: u32 = 0x02;
2450            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2451            pub const CONTEXT_ERROR: u32 = 0x03;
2452            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2453            pub const PAYLOAD_ERROR: u32 = 0x04;
2454            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash)."]
2455            pub const INVALID_MODE: u32 = 0x05;
2456        }
2457    }
2458    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2459    pub mod TAG {
2460        pub const offset: u32 = 24;
2461        pub const mask: u32 = 0xff << offset;
2462        pub mod R {}
2463        pub mod W {}
2464        pub mod RW {}
2465    }
2466}
2467#[doc = "DCP channel 2 options register"]
2468pub mod CH2OPTS {
2469    #[doc = "This field indicates the recovery time for the channel"]
2470    pub mod RECOVERY_TIMER {
2471        pub const offset: u32 = 0;
2472        pub const mask: u32 = 0xffff << offset;
2473        pub mod R {}
2474        pub mod W {}
2475        pub mod RW {}
2476    }
2477}
2478#[doc = "DCP channel 2 options register"]
2479pub mod CH2OPTS_SET {
2480    #[doc = "This field indicates the recovery time for the channel"]
2481    pub mod RECOVERY_TIMER {
2482        pub const offset: u32 = 0;
2483        pub const mask: u32 = 0xffff << offset;
2484        pub mod R {}
2485        pub mod W {}
2486        pub mod RW {}
2487    }
2488}
2489#[doc = "DCP channel 2 options register"]
2490pub mod CH2OPTS_CLR {
2491    #[doc = "This field indicates the recovery time for the channel"]
2492    pub mod RECOVERY_TIMER {
2493        pub const offset: u32 = 0;
2494        pub const mask: u32 = 0xffff << offset;
2495        pub mod R {}
2496        pub mod W {}
2497        pub mod RW {}
2498    }
2499}
2500#[doc = "DCP channel 2 options register"]
2501pub mod CH2OPTS_TOG {
2502    #[doc = "This field indicates the recovery time for the channel"]
2503    pub mod RECOVERY_TIMER {
2504        pub const offset: u32 = 0;
2505        pub const mask: u32 = 0xffff << offset;
2506        pub mod R {}
2507        pub mod W {}
2508        pub mod RW {}
2509    }
2510}
2511#[doc = "DCP channel 3 command pointer address register"]
2512pub mod CH3CMDPTR {
2513    #[doc = "Pointer to the descriptor structure to be processed for channel 3."]
2514    pub mod ADDR {
2515        pub const offset: u32 = 0;
2516        pub const mask: u32 = 0xffff_ffff << offset;
2517        pub mod R {}
2518        pub mod W {}
2519        pub mod RW {}
2520    }
2521}
2522#[doc = "DCP channel 3 semaphore register"]
2523pub mod CH3SEMA {
2524    #[doc = "The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected"]
2525    pub mod INCREMENT {
2526        pub const offset: u32 = 0;
2527        pub const mask: u32 = 0xff << offset;
2528        pub mod R {}
2529        pub mod W {}
2530        pub mod RW {}
2531    }
2532    #[doc = "This read-only field shows the current (instantaneous) value of the semaphore counter."]
2533    pub mod VALUE {
2534        pub const offset: u32 = 16;
2535        pub const mask: u32 = 0xff << offset;
2536        pub mod R {}
2537        pub mod W {}
2538        pub mod RW {}
2539    }
2540}
2541#[doc = "DCP channel 3 status register"]
2542pub mod CH3STAT {
2543    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2544    pub mod HASH_MISMATCH {
2545        pub const offset: u32 = 1;
2546        pub const mask: u32 = 0x01 << offset;
2547        pub mod R {}
2548        pub mod W {}
2549        pub mod RW {}
2550    }
2551    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2552    pub mod ERROR_SETUP {
2553        pub const offset: u32 = 2;
2554        pub const mask: u32 = 0x01 << offset;
2555        pub mod R {}
2556        pub mod W {}
2557        pub mod RW {}
2558    }
2559    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod"]
2560    pub mod ERROR_PACKET {
2561        pub const offset: u32 = 3;
2562        pub const mask: u32 = 0x01 << offset;
2563        pub mod R {}
2564        pub mod W {}
2565        pub mod RW {}
2566    }
2567    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2568    pub mod ERROR_SRC {
2569        pub const offset: u32 = 4;
2570        pub const mask: u32 = 0x01 << offset;
2571        pub mod R {}
2572        pub mod W {}
2573        pub mod RW {}
2574    }
2575    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2576    pub mod ERROR_DST {
2577        pub const offset: u32 = 5;
2578        pub const mask: u32 = 0x01 << offset;
2579        pub mod R {}
2580        pub mod W {}
2581        pub mod RW {}
2582    }
2583    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2584    pub mod ERROR_PAGEFAULT {
2585        pub const offset: u32 = 6;
2586        pub const mask: u32 = 0x01 << offset;
2587        pub mod R {}
2588        pub mod W {}
2589        pub mod RW {}
2590    }
2591    #[doc = "Indicates additional error codes for some of the error conditions."]
2592    pub mod ERROR_CODE {
2593        pub const offset: u32 = 16;
2594        pub const mask: u32 = 0xff << offset;
2595        pub mod R {}
2596        pub mod W {}
2597        pub mod RW {
2598            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2599            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2600            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2601            pub const NO_CHAIN: u32 = 0x02;
2602            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2603            pub const CONTEXT_ERROR: u32 = 0x03;
2604            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2605            pub const PAYLOAD_ERROR: u32 = 0x04;
2606            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
2607            pub const INVALID_MODE: u32 = 0x05;
2608        }
2609    }
2610    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2611    pub mod TAG {
2612        pub const offset: u32 = 24;
2613        pub const mask: u32 = 0xff << offset;
2614        pub mod R {}
2615        pub mod W {}
2616        pub mod RW {}
2617    }
2618}
2619#[doc = "DCP channel 3 status register"]
2620pub mod CH3STAT_SET {
2621    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2622    pub mod HASH_MISMATCH {
2623        pub const offset: u32 = 1;
2624        pub const mask: u32 = 0x01 << offset;
2625        pub mod R {}
2626        pub mod W {}
2627        pub mod RW {}
2628    }
2629    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2630    pub mod ERROR_SETUP {
2631        pub const offset: u32 = 2;
2632        pub const mask: u32 = 0x01 << offset;
2633        pub mod R {}
2634        pub mod W {}
2635        pub mod RW {}
2636    }
2637    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod"]
2638    pub mod ERROR_PACKET {
2639        pub const offset: u32 = 3;
2640        pub const mask: u32 = 0x01 << offset;
2641        pub mod R {}
2642        pub mod W {}
2643        pub mod RW {}
2644    }
2645    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2646    pub mod ERROR_SRC {
2647        pub const offset: u32 = 4;
2648        pub const mask: u32 = 0x01 << offset;
2649        pub mod R {}
2650        pub mod W {}
2651        pub mod RW {}
2652    }
2653    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2654    pub mod ERROR_DST {
2655        pub const offset: u32 = 5;
2656        pub const mask: u32 = 0x01 << offset;
2657        pub mod R {}
2658        pub mod W {}
2659        pub mod RW {}
2660    }
2661    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2662    pub mod ERROR_PAGEFAULT {
2663        pub const offset: u32 = 6;
2664        pub const mask: u32 = 0x01 << offset;
2665        pub mod R {}
2666        pub mod W {}
2667        pub mod RW {}
2668    }
2669    #[doc = "Indicates additional error codes for some of the error conditions."]
2670    pub mod ERROR_CODE {
2671        pub const offset: u32 = 16;
2672        pub const mask: u32 = 0xff << offset;
2673        pub mod R {}
2674        pub mod W {}
2675        pub mod RW {
2676            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2677            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2678            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2679            pub const NO_CHAIN: u32 = 0x02;
2680            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2681            pub const CONTEXT_ERROR: u32 = 0x03;
2682            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2683            pub const PAYLOAD_ERROR: u32 = 0x04;
2684            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
2685            pub const INVALID_MODE: u32 = 0x05;
2686        }
2687    }
2688    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2689    pub mod TAG {
2690        pub const offset: u32 = 24;
2691        pub const mask: u32 = 0xff << offset;
2692        pub mod R {}
2693        pub mod W {}
2694        pub mod RW {}
2695    }
2696}
2697#[doc = "DCP channel 3 status register"]
2698pub mod CH3STAT_CLR {
2699    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2700    pub mod HASH_MISMATCH {
2701        pub const offset: u32 = 1;
2702        pub const mask: u32 = 0x01 << offset;
2703        pub mod R {}
2704        pub mod W {}
2705        pub mod RW {}
2706    }
2707    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2708    pub mod ERROR_SETUP {
2709        pub const offset: u32 = 2;
2710        pub const mask: u32 = 0x01 << offset;
2711        pub mod R {}
2712        pub mod W {}
2713        pub mod RW {}
2714    }
2715    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod"]
2716    pub mod ERROR_PACKET {
2717        pub const offset: u32 = 3;
2718        pub const mask: u32 = 0x01 << offset;
2719        pub mod R {}
2720        pub mod W {}
2721        pub mod RW {}
2722    }
2723    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2724    pub mod ERROR_SRC {
2725        pub const offset: u32 = 4;
2726        pub const mask: u32 = 0x01 << offset;
2727        pub mod R {}
2728        pub mod W {}
2729        pub mod RW {}
2730    }
2731    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2732    pub mod ERROR_DST {
2733        pub const offset: u32 = 5;
2734        pub const mask: u32 = 0x01 << offset;
2735        pub mod R {}
2736        pub mod W {}
2737        pub mod RW {}
2738    }
2739    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2740    pub mod ERROR_PAGEFAULT {
2741        pub const offset: u32 = 6;
2742        pub const mask: u32 = 0x01 << offset;
2743        pub mod R {}
2744        pub mod W {}
2745        pub mod RW {}
2746    }
2747    #[doc = "Indicates additional error codes for some of the error conditions."]
2748    pub mod ERROR_CODE {
2749        pub const offset: u32 = 16;
2750        pub const mask: u32 = 0xff << offset;
2751        pub mod R {}
2752        pub mod W {}
2753        pub mod RW {
2754            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2755            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2756            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2757            pub const NO_CHAIN: u32 = 0x02;
2758            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2759            pub const CONTEXT_ERROR: u32 = 0x03;
2760            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2761            pub const PAYLOAD_ERROR: u32 = 0x04;
2762            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
2763            pub const INVALID_MODE: u32 = 0x05;
2764        }
2765    }
2766    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2767    pub mod TAG {
2768        pub const offset: u32 = 24;
2769        pub const mask: u32 = 0xff << offset;
2770        pub mod R {}
2771        pub mod W {}
2772        pub mod RW {}
2773    }
2774}
2775#[doc = "DCP channel 3 status register"]
2776pub mod CH3STAT_TOG {
2777    #[doc = "This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit"]
2778    pub mod HASH_MISMATCH {
2779        pub const offset: u32 = 1;
2780        pub const mask: u32 = 0x01 << offset;
2781        pub mod R {}
2782        pub mod W {}
2783        pub mod RW {}
2784    }
2785    #[doc = "This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)"]
2786    pub mod ERROR_SETUP {
2787        pub const offset: u32 = 2;
2788        pub const mask: u32 = 0x01 << offset;
2789        pub mod R {}
2790        pub mod W {}
2791        pub mod RW {}
2792    }
2793    #[doc = "This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod"]
2794    pub mod ERROR_PACKET {
2795        pub const offset: u32 = 3;
2796        pub const mask: u32 = 0x01 << offset;
2797        pub mod R {}
2798        pub mod W {}
2799        pub mod RW {}
2800    }
2801    #[doc = "This bit indicates that a bus error occurred when reading from the source buffer"]
2802    pub mod ERROR_SRC {
2803        pub const offset: u32 = 4;
2804        pub const mask: u32 = 0x01 << offset;
2805        pub mod R {}
2806        pub mod W {}
2807        pub mod RW {}
2808    }
2809    #[doc = "This bit indicates that a bus error occurred when storing to the destination buffer"]
2810    pub mod ERROR_DST {
2811        pub const offset: u32 = 5;
2812        pub const mask: u32 = 0x01 << offset;
2813        pub mod R {}
2814        pub mod W {}
2815        pub mod RW {}
2816    }
2817    #[doc = "This bit indicates that a page fault occurred while converting a virtual address to a physical address"]
2818    pub mod ERROR_PAGEFAULT {
2819        pub const offset: u32 = 6;
2820        pub const mask: u32 = 0x01 << offset;
2821        pub mod R {}
2822        pub mod W {}
2823        pub mod RW {}
2824    }
2825    #[doc = "Indicates additional error codes for some of the error conditions."]
2826    pub mod ERROR_CODE {
2827        pub const offset: u32 = 16;
2828        pub const mask: u32 = 0xff << offset;
2829        pub mod R {}
2830        pub mod W {}
2831        pub mod RW {
2832            #[doc = "Error is signalled because the next pointer is 0x00000000."]
2833            pub const NEXT_CHAIN_IS_0: u32 = 0x01;
2834            #[doc = "Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set."]
2835            pub const NO_CHAIN: u32 = 0x02;
2836            #[doc = "Error is signalled because an error was reported while reading/writing the context buffer."]
2837            pub const CONTEXT_ERROR: u32 = 0x03;
2838            #[doc = "Error is signalled because an error was reported while reading/writing the payload."]
2839            pub const PAYLOAD_ERROR: u32 = 0x04;
2840            #[doc = "Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash)."]
2841            pub const INVALID_MODE: u32 = 0x05;
2842        }
2843    }
2844    #[doc = "Indicates the tag from the last completed packet in the command structure."]
2845    pub mod TAG {
2846        pub const offset: u32 = 24;
2847        pub const mask: u32 = 0xff << offset;
2848        pub mod R {}
2849        pub mod W {}
2850        pub mod RW {}
2851    }
2852}
2853#[doc = "DCP channel 3 options register"]
2854pub mod CH3OPTS {
2855    #[doc = "This field indicates the recovery time for the channel"]
2856    pub mod RECOVERY_TIMER {
2857        pub const offset: u32 = 0;
2858        pub const mask: u32 = 0xffff << offset;
2859        pub mod R {}
2860        pub mod W {}
2861        pub mod RW {}
2862    }
2863}
2864#[doc = "DCP channel 3 options register"]
2865pub mod CH3OPTS_SET {
2866    #[doc = "This field indicates the recovery time for the channel"]
2867    pub mod RECOVERY_TIMER {
2868        pub const offset: u32 = 0;
2869        pub const mask: u32 = 0xffff << offset;
2870        pub mod R {}
2871        pub mod W {}
2872        pub mod RW {}
2873    }
2874}
2875#[doc = "DCP channel 3 options register"]
2876pub mod CH3OPTS_CLR {
2877    #[doc = "This field indicates the recovery time for the channel"]
2878    pub mod RECOVERY_TIMER {
2879        pub const offset: u32 = 0;
2880        pub const mask: u32 = 0xffff << offset;
2881        pub mod R {}
2882        pub mod W {}
2883        pub mod RW {}
2884    }
2885}
2886#[doc = "DCP channel 3 options register"]
2887pub mod CH3OPTS_TOG {
2888    #[doc = "This field indicates the recovery time for the channel"]
2889    pub mod RECOVERY_TIMER {
2890        pub const offset: u32 = 0;
2891        pub const mask: u32 = 0xffff << offset;
2892        pub mod R {}
2893        pub mod W {}
2894        pub mod RW {}
2895    }
2896}
2897#[doc = "DCP debug select register"]
2898pub mod DBGSELECT {
2899    #[doc = "Selects a value to read via the debug data register."]
2900    pub mod INDEX {
2901        pub const offset: u32 = 0;
2902        pub const mask: u32 = 0xff << offset;
2903        pub mod R {}
2904        pub mod W {}
2905        pub mod RW {
2906            #[doc = "CONTROL"]
2907            pub const CONTROL: u32 = 0x01;
2908            #[doc = "OTPKEY0"]
2909            pub const OTPKEY0: u32 = 0x10;
2910            #[doc = "OTPKEY1"]
2911            pub const OTPKEY1: u32 = 0x11;
2912            #[doc = "OTPKEY2"]
2913            pub const OTPKEY2: u32 = 0x12;
2914            #[doc = "OTPKEY3"]
2915            pub const OTPKEY3: u32 = 0x13;
2916        }
2917    }
2918}
2919#[doc = "DCP debug data register"]
2920pub mod DBGDATA {
2921    #[doc = "Debug data"]
2922    pub mod DATA {
2923        pub const offset: u32 = 0;
2924        pub const mask: u32 = 0xffff_ffff << offset;
2925        pub mod R {}
2926        pub mod W {}
2927        pub mod RW {}
2928    }
2929}
2930#[doc = "DCP page table register"]
2931pub mod PAGETABLE {
2932    #[doc = "Page table enable control"]
2933    pub mod ENABLE {
2934        pub const offset: u32 = 0;
2935        pub const mask: u32 = 0x01 << offset;
2936        pub mod R {}
2937        pub mod W {}
2938        pub mod RW {}
2939    }
2940    #[doc = "Page table flush control. To flush the TLB, write this bit to 1 and then back to 0."]
2941    pub mod FLUSH {
2942        pub const offset: u32 = 1;
2943        pub const mask: u32 = 0x01 << offset;
2944        pub mod R {}
2945        pub mod W {}
2946        pub mod RW {}
2947    }
2948    #[doc = "Page table base address"]
2949    pub mod BASE {
2950        pub const offset: u32 = 2;
2951        pub const mask: u32 = 0x3fff_ffff << offset;
2952        pub mod R {}
2953        pub mod W {}
2954        pub mod RW {}
2955    }
2956}
2957#[doc = "DCP version register"]
2958pub mod VERSION {
2959    #[doc = "Fixed read-only value reflecting the stepping of the version of the design implementation."]
2960    pub mod STEP {
2961        pub const offset: u32 = 0;
2962        pub const mask: u32 = 0xffff << offset;
2963        pub mod R {}
2964        pub mod W {}
2965        pub mod RW {}
2966    }
2967    #[doc = "Fixed read-only value reflecting the MINOR version of the design implementation."]
2968    pub mod MINOR {
2969        pub const offset: u32 = 16;
2970        pub const mask: u32 = 0xff << offset;
2971        pub mod R {}
2972        pub mod W {}
2973        pub mod RW {}
2974    }
2975    #[doc = "Fixed read-only value reflecting the MAJOR version of the design implementation."]
2976    pub mod MAJOR {
2977        pub const offset: u32 = 24;
2978        pub const mask: u32 = 0xff << offset;
2979        pub mod R {}
2980        pub mod W {}
2981        pub mod RW {}
2982    }
2983}
imxrt_ral/blocks/imxrt1011/dcp.rs

imxrt_ral/blocks/imxrt1011/
dcp.rs
