rp2040_pac/ppb/
nvic_ispr.rs

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1#[doc = "Register `NVIC_ISPR` reader"]
2pub type R = crate::R<NVIC_ISPR_SPEC>;
3#[doc = "Register `NVIC_ISPR` writer"]
4pub type W = crate::W<NVIC_ISPR_SPEC>;
5#[doc = "Field `SETPEND` reader - Interrupt set-pending bits.  
6 Write:  
7 0 = No effect.  
8 1 = Changes interrupt state to pending.  
9 Read:  
10 0 = Interrupt is not pending.  
11 1 = Interrupt is pending.  
12 Note: Writing 1 to the NVIC_ISPR bit corresponding to:  
13 An interrupt that is pending has no effect.  
14 A disabled interrupt sets the state of that interrupt to pending."]
15pub type SETPEND_R = crate::FieldReader<u32>;
16#[doc = "Field `SETPEND` writer - Interrupt set-pending bits.  
17 Write:  
18 0 = No effect.  
19 1 = Changes interrupt state to pending.  
20 Read:  
21 0 = Interrupt is not pending.  
22 1 = Interrupt is pending.  
23 Note: Writing 1 to the NVIC_ISPR bit corresponding to:  
24 An interrupt that is pending has no effect.  
25 A disabled interrupt sets the state of that interrupt to pending."]
26pub type SETPEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27impl R {
28    #[doc = "Bits 0:31 - Interrupt set-pending bits.  
29 Write:  
30 0 = No effect.  
31 1 = Changes interrupt state to pending.  
32 Read:  
33 0 = Interrupt is not pending.  
34 1 = Interrupt is pending.  
35 Note: Writing 1 to the NVIC_ISPR bit corresponding to:  
36 An interrupt that is pending has no effect.  
37 A disabled interrupt sets the state of that interrupt to pending."]
38    #[inline(always)]
39    pub fn setpend(&self) -> SETPEND_R {
40        SETPEND_R::new(self.bits)
41    }
42}
43impl W {
44    #[doc = "Bits 0:31 - Interrupt set-pending bits.  
45 Write:  
46 0 = No effect.  
47 1 = Changes interrupt state to pending.  
48 Read:  
49 0 = Interrupt is not pending.  
50 1 = Interrupt is pending.  
51 Note: Writing 1 to the NVIC_ISPR bit corresponding to:  
52 An interrupt that is pending has no effect.  
53 A disabled interrupt sets the state of that interrupt to pending."]
54    #[inline(always)]
55    #[must_use]
56    pub fn setpend(&mut self) -> SETPEND_W<NVIC_ISPR_SPEC> {
57        SETPEND_W::new(self, 0)
58    }
59    #[doc = r" Writes raw bits to the register."]
60    #[doc = r""]
61    #[doc = r" # Safety"]
62    #[doc = r""]
63    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
64    #[inline(always)]
65    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
66        self.bits = bits;
67        self
68    }
69}
70#[doc = "The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.  
71
72You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ispr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ispr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
73pub struct NVIC_ISPR_SPEC;
74impl crate::RegisterSpec for NVIC_ISPR_SPEC {
75    type Ux = u32;
76}
77#[doc = "`read()` method returns [`nvic_ispr::R`](R) reader structure"]
78impl crate::Readable for NVIC_ISPR_SPEC {}
79#[doc = "`write(|w| ..)` method takes [`nvic_ispr::W`](W) writer structure"]
80impl crate::Writable for NVIC_ISPR_SPEC {
81    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
82    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
83}
84#[doc = "`reset()` method sets NVIC_ISPR to value 0"]
85impl crate::Resettable for NVIC_ISPR_SPEC {
86    const RESET_VALUE: u32 = 0;
87}
rp2040_pac/ppb/nvic_ispr.rs

rp2040_pac/ppb/
nvic_ispr.rs
