rp2040_pac/clocks/
clk_sys_selected.rs

Help
1#[doc = "Register `CLK_SYS_SELECTED` reader"]
2pub type R = crate::R<CLK_SYS_SELECTED_SPEC>;
3impl core::fmt::Debug for R {
4    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5        write!(f, "{}", self.bits())
6    }
7}
8impl core::fmt::Debug for crate::generic::Reg<CLK_SYS_SELECTED_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        core::fmt::Debug::fmt(&self.read(), f)
11    }
12}
13#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
14 The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.  
15
16You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17pub struct CLK_SYS_SELECTED_SPEC;
18impl crate::RegisterSpec for CLK_SYS_SELECTED_SPEC {
19    type Ux = u32;
20}
21#[doc = "`read()` method returns [`clk_sys_selected::R`](R) reader structure"]
22impl crate::Readable for CLK_SYS_SELECTED_SPEC {}
23#[doc = "`reset()` method sets CLK_SYS_SELECTED to value 0x01"]
24impl crate::Resettable for CLK_SYS_SELECTED_SPEC {
25    const RESET_VALUE: u32 = 0x01;
26}
rp2040_pac/clocks/clk_sys_selected.rs

rp2040_pac/clocks/
clk_sys_selected.rs
