imxrt_ral/blocks/imxrt1011/
iomuxc_snvs_gpr.rs

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1#[doc = "IOMUXC"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "GPR0 General Purpose Register"]
5    pub GPR0: crate::RORegister<u32>,
6    #[doc = "GPR1 General Purpose Register"]
7    pub GPR1: crate::RORegister<u32>,
8    #[doc = "GPR2 General Purpose Register"]
9    pub GPR2: crate::RORegister<u32>,
10    #[doc = "GPR3 General Purpose Register"]
11    pub GPR3: crate::RWRegister<u32>,
12}
13#[doc = "GPR3 General Purpose Register"]
14pub mod GPR3 {
15    #[doc = "Set to enable LPSR mode."]
16    pub mod LPSR_MODE_ENABLE {
17        pub const offset: u32 = 0;
18        pub const mask: u32 = 0x01 << offset;
19        pub mod R {}
20        pub mod W {}
21        pub mod RW {}
22    }
23    #[doc = "DCDC captured status clear"]
24    pub mod DCDC_STATUS_CAPT_CLR {
25        pub const offset: u32 = 1;
26        pub const mask: u32 = 0x01 << offset;
27        pub mod R {}
28        pub mod W {}
29        pub mod RW {}
30    }
31    #[doc = "POR_B pad control"]
32    pub mod POR_PULL_TYPE {
33        pub const offset: u32 = 2;
34        pub const mask: u32 = 0x03 << offset;
35        pub mod R {}
36        pub mod W {}
37        pub mod RW {}
38    }
39    #[doc = "DCDC_IN low voltage detect."]
40    pub mod DCDC_IN_LOW_VOL {
41        pub const offset: u32 = 16;
42        pub const mask: u32 = 0x01 << offset;
43        pub mod R {}
44        pub mod W {}
45        pub mod RW {}
46    }
47    #[doc = "DCDC output over current alert"]
48    pub mod DCDC_OVER_CUR {
49        pub const offset: u32 = 17;
50        pub const mask: u32 = 0x01 << offset;
51        pub mod R {}
52        pub mod W {}
53        pub mod RW {}
54    }
55    #[doc = "DCDC output over voltage alert"]
56    pub mod DCDC_OVER_VOL {
57        pub const offset: u32 = 18;
58        pub const mask: u32 = 0x01 << offset;
59        pub mod R {}
60        pub mod W {}
61        pub mod RW {}
62    }
63    #[doc = "DCDC status OK"]
64    pub mod DCDC_STS_DC_OK {
65        pub const offset: u32 = 19;
66        pub const mask: u32 = 0x01 << offset;
67        pub mod R {}
68        pub mod W {}
69        pub mod RW {}
70    }
71}
imxrt_ral/blocks/imxrt1011/iomuxc_snvs_gpr.rs

imxrt_ral/blocks/imxrt1011/
iomuxc_snvs_gpr.rs
