nrf52840_pac/uicr/
regout0.rs

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1#[doc = "Register `REGOUT0` reader"]
2pub struct R(crate::R<REGOUT0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<REGOUT0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<REGOUT0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<REGOUT0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `REGOUT0` writer"]
17pub struct W(crate::W<REGOUT0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<REGOUT0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<REGOUT0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<REGOUT0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VOUT` reader - Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF."]
38pub type VOUT_R = crate::FieldReader<u8, VOUT_A>;
39#[doc = "Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.\n\nValue on reset: 7"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41#[repr(u8)]
42pub enum VOUT_A {
43    #[doc = "0: 1.8 V"]
44    _1V8 = 0,
45    #[doc = "1: 2.1 V"]
46    _2V1 = 1,
47    #[doc = "2: 2.4 V"]
48    _2V4 = 2,
49    #[doc = "3: 2.7 V"]
50    _2V7 = 3,
51    #[doc = "4: 3.0 V"]
52    _3V0 = 4,
53    #[doc = "5: 3.3 V"]
54    _3V3 = 5,
55    #[doc = "7: Default voltage: 1.8 V"]
56    DEFAULT = 7,
57}
58impl From<VOUT_A> for u8 {
59    #[inline(always)]
60    fn from(variant: VOUT_A) -> Self {
61        variant as _
62    }
63}
64impl VOUT_R {
65    #[doc = "Get enumerated values variant"]
66    #[inline(always)]
67    pub fn variant(&self) -> Option<VOUT_A> {
68        match self.bits {
69            0 => Some(VOUT_A::_1V8),
70            1 => Some(VOUT_A::_2V1),
71            2 => Some(VOUT_A::_2V4),
72            3 => Some(VOUT_A::_2V7),
73            4 => Some(VOUT_A::_3V0),
74            5 => Some(VOUT_A::_3V3),
75            7 => Some(VOUT_A::DEFAULT),
76            _ => None,
77        }
78    }
79    #[doc = "Checks if the value of the field is `_1V8`"]
80    #[inline(always)]
81    pub fn is_1v8(&self) -> bool {
82        *self == VOUT_A::_1V8
83    }
84    #[doc = "Checks if the value of the field is `_2V1`"]
85    #[inline(always)]
86    pub fn is_2v1(&self) -> bool {
87        *self == VOUT_A::_2V1
88    }
89    #[doc = "Checks if the value of the field is `_2V4`"]
90    #[inline(always)]
91    pub fn is_2v4(&self) -> bool {
92        *self == VOUT_A::_2V4
93    }
94    #[doc = "Checks if the value of the field is `_2V7`"]
95    #[inline(always)]
96    pub fn is_2v7(&self) -> bool {
97        *self == VOUT_A::_2V7
98    }
99    #[doc = "Checks if the value of the field is `_3V0`"]
100    #[inline(always)]
101    pub fn is_3v0(&self) -> bool {
102        *self == VOUT_A::_3V0
103    }
104    #[doc = "Checks if the value of the field is `_3V3`"]
105    #[inline(always)]
106    pub fn is_3v3(&self) -> bool {
107        *self == VOUT_A::_3V3
108    }
109    #[doc = "Checks if the value of the field is `DEFAULT`"]
110    #[inline(always)]
111    pub fn is_default(&self) -> bool {
112        *self == VOUT_A::DEFAULT
113    }
114}
115#[doc = "Field `VOUT` writer - Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF."]
116pub type VOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, REGOUT0_SPEC, u8, VOUT_A, 3, O>;
117impl<'a, const O: u8> VOUT_W<'a, O> {
118    #[doc = "1.8 V"]
119    #[inline(always)]
120    pub fn _1v8(self) -> &'a mut W {
121        self.variant(VOUT_A::_1V8)
122    }
123    #[doc = "2.1 V"]
124    #[inline(always)]
125    pub fn _2v1(self) -> &'a mut W {
126        self.variant(VOUT_A::_2V1)
127    }
128    #[doc = "2.4 V"]
129    #[inline(always)]
130    pub fn _2v4(self) -> &'a mut W {
131        self.variant(VOUT_A::_2V4)
132    }
133    #[doc = "2.7 V"]
134    #[inline(always)]
135    pub fn _2v7(self) -> &'a mut W {
136        self.variant(VOUT_A::_2V7)
137    }
138    #[doc = "3.0 V"]
139    #[inline(always)]
140    pub fn _3v0(self) -> &'a mut W {
141        self.variant(VOUT_A::_3V0)
142    }
143    #[doc = "3.3 V"]
144    #[inline(always)]
145    pub fn _3v3(self) -> &'a mut W {
146        self.variant(VOUT_A::_3V3)
147    }
148    #[doc = "Default voltage: 1.8 V"]
149    #[inline(always)]
150    pub fn default(self) -> &'a mut W {
151        self.variant(VOUT_A::DEFAULT)
152    }
153}
154impl R {
155    #[doc = "Bits 0:2 - Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF."]
156    #[inline(always)]
157    pub fn vout(&self) -> VOUT_R {
158        VOUT_R::new((self.bits & 7) as u8)
159    }
160}
161impl W {
162    #[doc = "Bits 0:2 - Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF."]
163    #[inline(always)]
164    pub fn vout(&mut self) -> VOUT_W<0> {
165        VOUT_W::new(self)
166    }
167    #[doc = "Writes raw bits to the register."]
168    #[inline(always)]
169    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
170        self.0.bits(bits);
171        self
172    }
173}
174#[doc = "GPIO reference voltage / external output supply voltage in high voltage mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [regout0](index.html) module"]
175pub struct REGOUT0_SPEC;
176impl crate::RegisterSpec for REGOUT0_SPEC {
177    type Ux = u32;
178}
179#[doc = "`read()` method returns [regout0::R](R) reader structure"]
180impl crate::Readable for REGOUT0_SPEC {
181    type Reader = R;
182}
183#[doc = "`write(|w| ..)` method takes [regout0::W](W) writer structure"]
184impl crate::Writable for REGOUT0_SPEC {
185    type Writer = W;
186}
187#[doc = "`reset()` method sets REGOUT0 to value 0xffff_ffff"]
188impl crate::Resettable for REGOUT0_SPEC {
189    #[inline(always)]
190    fn reset_value() -> Self::Ux {
191        0xffff_ffff
192    }
193}
nrf52840_pac/uicr/regout0.rs

nrf52840_pac/uicr/
regout0.rs
