rp2040_pac/io_qspi/
proc1_intf.rs

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1#[doc = "Register `PROC1_INTF` reader"]
2pub type R = crate::R<PROC1_INTF_SPEC>;
3#[doc = "Register `PROC1_INTF` writer"]
4pub type W = crate::W<PROC1_INTF_SPEC>;
5#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "]
6pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader;
7#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "]
8pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "]
10pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader;
11#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "]
12pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "]
14pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader;
15#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "]
16pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "]
18pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader;
19#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "]
20pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "]
22pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader;
23#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "]
24pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "]
26pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader;
27#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "]
28pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "]
30pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader;
31#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "]
32pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "]
34pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader;
35#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "]
36pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "]
38pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader;
39#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "]
40pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "]
42pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader;
43#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "]
44pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "]
46pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader;
47#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "]
48pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "]
50pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader;
51#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "]
52pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "]
54pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader;
55#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "]
56pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "]
58pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader;
59#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "]
60pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "]
62pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader;
63#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "]
64pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "]
66pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader;
67#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "]
68pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "]
70pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader;
71#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "]
72pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "]
74pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader;
75#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "]
76pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "]
78pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader;
79#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "]
80pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "]
82pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader;
83#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "]
84pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "]
86pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader;
87#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "]
88pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "]
90pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader;
91#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "]
92pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "]
94pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader;
95#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "]
96pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "]
98pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader;
99#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "]
100pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
101impl R {
102    #[doc = "Bit 0"]
103    #[inline(always)]
104    pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R {
105        GPIO_QSPI_SCLK_LEVEL_LOW_R::new((self.bits & 1) != 0)
106    }
107    #[doc = "Bit 1"]
108    #[inline(always)]
109    pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R {
110        GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0)
111    }
112    #[doc = "Bit 2"]
113    #[inline(always)]
114    pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R {
115        GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0)
116    }
117    #[doc = "Bit 3"]
118    #[inline(always)]
119    pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R {
120        GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0)
121    }
122    #[doc = "Bit 4"]
123    #[inline(always)]
124    pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R {
125        GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0)
126    }
127    #[doc = "Bit 5"]
128    #[inline(always)]
129    pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R {
130        GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0)
131    }
132    #[doc = "Bit 6"]
133    #[inline(always)]
134    pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R {
135        GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0)
136    }
137    #[doc = "Bit 7"]
138    #[inline(always)]
139    pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R {
140        GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0)
141    }
142    #[doc = "Bit 8"]
143    #[inline(always)]
144    pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R {
145        GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0)
146    }
147    #[doc = "Bit 9"]
148    #[inline(always)]
149    pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R {
150        GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0)
151    }
152    #[doc = "Bit 10"]
153    #[inline(always)]
154    pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R {
155        GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0)
156    }
157    #[doc = "Bit 11"]
158    #[inline(always)]
159    pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R {
160        GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0)
161    }
162    #[doc = "Bit 12"]
163    #[inline(always)]
164    pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R {
165        GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0)
166    }
167    #[doc = "Bit 13"]
168    #[inline(always)]
169    pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R {
170        GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0)
171    }
172    #[doc = "Bit 14"]
173    #[inline(always)]
174    pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R {
175        GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0)
176    }
177    #[doc = "Bit 15"]
178    #[inline(always)]
179    pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R {
180        GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0)
181    }
182    #[doc = "Bit 16"]
183    #[inline(always)]
184    pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R {
185        GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0)
186    }
187    #[doc = "Bit 17"]
188    #[inline(always)]
189    pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R {
190        GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0)
191    }
192    #[doc = "Bit 18"]
193    #[inline(always)]
194    pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R {
195        GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0)
196    }
197    #[doc = "Bit 19"]
198    #[inline(always)]
199    pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R {
200        GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0)
201    }
202    #[doc = "Bit 20"]
203    #[inline(always)]
204    pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R {
205        GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0)
206    }
207    #[doc = "Bit 21"]
208    #[inline(always)]
209    pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R {
210        GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0)
211    }
212    #[doc = "Bit 22"]
213    #[inline(always)]
214    pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R {
215        GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0)
216    }
217    #[doc = "Bit 23"]
218    #[inline(always)]
219    pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R {
220        GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0)
221    }
222}
223impl W {
224    #[doc = "Bit 0"]
225    #[inline(always)]
226    #[must_use]
227    pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<PROC1_INTF_SPEC> {
228        GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 0)
229    }
230    #[doc = "Bit 1"]
231    #[inline(always)]
232    #[must_use]
233    pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
234        GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 1)
235    }
236    #[doc = "Bit 2"]
237    #[inline(always)]
238    #[must_use]
239    pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<PROC1_INTF_SPEC> {
240        GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 2)
241    }
242    #[doc = "Bit 3"]
243    #[inline(always)]
244    #[must_use]
245    pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<PROC1_INTF_SPEC> {
246        GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 3)
247    }
248    #[doc = "Bit 4"]
249    #[inline(always)]
250    #[must_use]
251    pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<PROC1_INTF_SPEC> {
252        GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 4)
253    }
254    #[doc = "Bit 5"]
255    #[inline(always)]
256    #[must_use]
257    pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
258        GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 5)
259    }
260    #[doc = "Bit 6"]
261    #[inline(always)]
262    #[must_use]
263    pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<PROC1_INTF_SPEC> {
264        GPIO_QSPI_SS_EDGE_LOW_W::new(self, 6)
265    }
266    #[doc = "Bit 7"]
267    #[inline(always)]
268    #[must_use]
269    pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<PROC1_INTF_SPEC> {
270        GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 7)
271    }
272    #[doc = "Bit 8"]
273    #[inline(always)]
274    #[must_use]
275    pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<PROC1_INTF_SPEC> {
276        GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 8)
277    }
278    #[doc = "Bit 9"]
279    #[inline(always)]
280    #[must_use]
281    pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
282        GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 9)
283    }
284    #[doc = "Bit 10"]
285    #[inline(always)]
286    #[must_use]
287    pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<PROC1_INTF_SPEC> {
288        GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 10)
289    }
290    #[doc = "Bit 11"]
291    #[inline(always)]
292    #[must_use]
293    pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<PROC1_INTF_SPEC> {
294        GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 11)
295    }
296    #[doc = "Bit 12"]
297    #[inline(always)]
298    #[must_use]
299    pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<PROC1_INTF_SPEC> {
300        GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 12)
301    }
302    #[doc = "Bit 13"]
303    #[inline(always)]
304    #[must_use]
305    pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
306        GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 13)
307    }
308    #[doc = "Bit 14"]
309    #[inline(always)]
310    #[must_use]
311    pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<PROC1_INTF_SPEC> {
312        GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 14)
313    }
314    #[doc = "Bit 15"]
315    #[inline(always)]
316    #[must_use]
317    pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<PROC1_INTF_SPEC> {
318        GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 15)
319    }
320    #[doc = "Bit 16"]
321    #[inline(always)]
322    #[must_use]
323    pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<PROC1_INTF_SPEC> {
324        GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 16)
325    }
326    #[doc = "Bit 17"]
327    #[inline(always)]
328    #[must_use]
329    pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
330        GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 17)
331    }
332    #[doc = "Bit 18"]
333    #[inline(always)]
334    #[must_use]
335    pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<PROC1_INTF_SPEC> {
336        GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 18)
337    }
338    #[doc = "Bit 19"]
339    #[inline(always)]
340    #[must_use]
341    pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<PROC1_INTF_SPEC> {
342        GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 19)
343    }
344    #[doc = "Bit 20"]
345    #[inline(always)]
346    #[must_use]
347    pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<PROC1_INTF_SPEC> {
348        GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 20)
349    }
350    #[doc = "Bit 21"]
351    #[inline(always)]
352    #[must_use]
353    pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
354        GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 21)
355    }
356    #[doc = "Bit 22"]
357    #[inline(always)]
358    #[must_use]
359    pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<PROC1_INTF_SPEC> {
360        GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 22)
361    }
362    #[doc = "Bit 23"]
363    #[inline(always)]
364    #[must_use]
365    pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<PROC1_INTF_SPEC> {
366        GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23)
367    }
368    #[doc = r" Writes raw bits to the register."]
369    #[doc = r""]
370    #[doc = r" # Safety"]
371    #[doc = r""]
372    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
373    #[inline(always)]
374    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
375        self.bits = bits;
376        self
377    }
378}
379#[doc = "Interrupt Force for proc1  
380
381You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
382pub struct PROC1_INTF_SPEC;
383impl crate::RegisterSpec for PROC1_INTF_SPEC {
384    type Ux = u32;
385}
386#[doc = "`read()` method returns [`proc1_intf::R`](R) reader structure"]
387impl crate::Readable for PROC1_INTF_SPEC {}
388#[doc = "`write(|w| ..)` method takes [`proc1_intf::W`](W) writer structure"]
389impl crate::Writable for PROC1_INTF_SPEC {
390    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
391    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
392}
393#[doc = "`reset()` method sets PROC1_INTF to value 0"]
394impl crate::Resettable for PROC1_INTF_SPEC {
395    const RESET_VALUE: u32 = 0;
396}
rp2040_pac/io_qspi/proc1_intf.rs

rp2040_pac/io_qspi/
proc1_intf.rs
