rp2040_pac/dma/ch/
ch_al3_ctrl.rs

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1#[doc = "Register `CH_AL3_CTRL` reader"]
2pub type R = crate::R<CH_AL3_CTRL_SPEC>;
3#[doc = "Register `CH_AL3_CTRL` writer"]
4pub type W = crate::W<CH_AL3_CTRL_SPEC>;
5#[doc = "Field `EN` reader - DMA Channel Enable.  
6 When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
7pub type EN_R = crate::BitReader;
8#[doc = "Field `EN` writer - DMA Channel Enable.  
9 When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
10pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.  
12
13 This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
14pub type HIGH_PRIORITY_R = crate::BitReader;
15#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.  
16
17 This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
18pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
20pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
21#[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.  
22
23Value on reset: 0"]
24#[derive(Clone, Copy, Debug, PartialEq, Eq)]
25#[repr(u8)]
26pub enum DATA_SIZE_A {
27    #[doc = "0: `0`"]
28    SIZE_BYTE = 0,
29    #[doc = "1: `1`"]
30    SIZE_HALFWORD = 1,
31    #[doc = "2: `10`"]
32    SIZE_WORD = 2,
33}
34impl From<DATA_SIZE_A> for u8 {
35    #[inline(always)]
36    fn from(variant: DATA_SIZE_A) -> Self {
37        variant as _
38    }
39}
40impl crate::FieldSpec for DATA_SIZE_A {
41    type Ux = u8;
42}
43impl DATA_SIZE_R {
44    #[doc = "Get enumerated values variant"]
45    #[inline(always)]
46    pub const fn variant(&self) -> Option<DATA_SIZE_A> {
47        match self.bits {
48            0 => Some(DATA_SIZE_A::SIZE_BYTE),
49            1 => Some(DATA_SIZE_A::SIZE_HALFWORD),
50            2 => Some(DATA_SIZE_A::SIZE_WORD),
51            _ => None,
52        }
53    }
54    #[doc = "`0`"]
55    #[inline(always)]
56    pub fn is_size_byte(&self) -> bool {
57        *self == DATA_SIZE_A::SIZE_BYTE
58    }
59    #[doc = "`1`"]
60    #[inline(always)]
61    pub fn is_size_halfword(&self) -> bool {
62        *self == DATA_SIZE_A::SIZE_HALFWORD
63    }
64    #[doc = "`10`"]
65    #[inline(always)]
66    pub fn is_size_word(&self) -> bool {
67        *self == DATA_SIZE_A::SIZE_WORD
68    }
69}
70#[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
71pub type DATA_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_SIZE_A>;
72impl<'a, REG> DATA_SIZE_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    #[doc = "`0`"]
78    #[inline(always)]
79    pub fn size_byte(self) -> &'a mut crate::W<REG> {
80        self.variant(DATA_SIZE_A::SIZE_BYTE)
81    }
82    #[doc = "`1`"]
83    #[inline(always)]
84    pub fn size_halfword(self) -> &'a mut crate::W<REG> {
85        self.variant(DATA_SIZE_A::SIZE_HALFWORD)
86    }
87    #[doc = "`10`"]
88    #[inline(always)]
89    pub fn size_word(self) -> &'a mut crate::W<REG> {
90        self.variant(DATA_SIZE_A::SIZE_WORD)
91    }
92}
93#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.  
94
95 Generally this should be disabled for peripheral-to-memory transfers."]
96pub type INCR_READ_R = crate::BitReader;
97#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.  
98
99 Generally this should be disabled for peripheral-to-memory transfers."]
100pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.  
102
103 Generally this should be disabled for memory-to-peripheral transfers."]
104pub type INCR_WRITE_R = crate::BitReader;
105#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.  
106
107 Generally this should be disabled for memory-to-peripheral transfers."]
108pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
110
111 Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
112pub type RING_SIZE_R = crate::FieldReader<RING_SIZE_A>;
113#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
114
115 Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
116
117Value on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119#[repr(u8)]
120pub enum RING_SIZE_A {
121    #[doc = "0: `0`"]
122    RING_NONE = 0,
123}
124impl From<RING_SIZE_A> for u8 {
125    #[inline(always)]
126    fn from(variant: RING_SIZE_A) -> Self {
127        variant as _
128    }
129}
130impl crate::FieldSpec for RING_SIZE_A {
131    type Ux = u8;
132}
133impl RING_SIZE_R {
134    #[doc = "Get enumerated values variant"]
135    #[inline(always)]
136    pub const fn variant(&self) -> Option<RING_SIZE_A> {
137        match self.bits {
138            0 => Some(RING_SIZE_A::RING_NONE),
139            _ => None,
140        }
141    }
142    #[doc = "`0`"]
143    #[inline(always)]
144    pub fn is_ring_none(&self) -> bool {
145        *self == RING_SIZE_A::RING_NONE
146    }
147}
148#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
149
150 Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
151pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>;
152impl<'a, REG> RING_SIZE_W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155    REG::Ux: From<u8>,
156{
157    #[doc = "`0`"]
158    #[inline(always)]
159    pub fn ring_none(self) -> &'a mut crate::W<REG> {
160        self.variant(RING_SIZE_A::RING_NONE)
161    }
162}
163#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses.  
164 If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
165pub type RING_SEL_R = crate::BitReader;
166#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses.  
167 If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
168pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
169#[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
170 Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
171pub type CHAIN_TO_R = crate::FieldReader;
172#[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
173 Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
174pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
175#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
176 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
177 0x0 to 0x3a -> select DREQ n as TREQ"]
178pub type TREQ_SEL_R = crate::FieldReader<TREQ_SEL_A>;
179#[doc = "Select a Transfer Request signal.  
180 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
181 0x0 to 0x3a -> select DREQ n as TREQ  
182
183Value on reset: 0"]
184#[derive(Clone, Copy, Debug, PartialEq, Eq)]
185#[repr(u8)]
186pub enum TREQ_SEL_A {
187    #[doc = "0: Select PIO0's TX FIFO 0 as TREQ"]
188    PIO0_TX0 = 0,
189    #[doc = "1: Select PIO0's TX FIFO 1 as TREQ"]
190    PIO0_TX1 = 1,
191    #[doc = "2: Select PIO0's TX FIFO 2 as TREQ"]
192    PIO0_TX2 = 2,
193    #[doc = "3: Select PIO0's TX FIFO 3 as TREQ"]
194    PIO0_TX3 = 3,
195    #[doc = "4: Select PIO0's RX FIFO 0 as TREQ"]
196    PIO0_RX0 = 4,
197    #[doc = "5: Select PIO0's RX FIFO 1 as TREQ"]
198    PIO0_RX1 = 5,
199    #[doc = "6: Select PIO0's RX FIFO 2 as TREQ"]
200    PIO0_RX2 = 6,
201    #[doc = "7: Select PIO0's RX FIFO 3 as TREQ"]
202    PIO0_RX3 = 7,
203    #[doc = "8: Select PIO1's TX FIFO 0 as TREQ"]
204    PIO1_TX0 = 8,
205    #[doc = "9: Select PIO1's TX FIFO 1 as TREQ"]
206    PIO1_TX1 = 9,
207    #[doc = "10: Select PIO1's TX FIFO 2 as TREQ"]
208    PIO1_TX2 = 10,
209    #[doc = "11: Select PIO1's TX FIFO 3 as TREQ"]
210    PIO1_TX3 = 11,
211    #[doc = "12: Select PIO1's RX FIFO 0 as TREQ"]
212    PIO1_RX0 = 12,
213    #[doc = "13: Select PIO1's RX FIFO 1 as TREQ"]
214    PIO1_RX1 = 13,
215    #[doc = "14: Select PIO1's RX FIFO 2 as TREQ"]
216    PIO1_RX2 = 14,
217    #[doc = "15: Select PIO1's RX FIFO 3 as TREQ"]
218    PIO1_RX3 = 15,
219    #[doc = "16: Select SPI0's TX FIFO as TREQ"]
220    SPI0_TX = 16,
221    #[doc = "17: Select SPI0's RX FIFO as TREQ"]
222    SPI0_RX = 17,
223    #[doc = "18: Select SPI1's TX FIFO as TREQ"]
224    SPI1_TX = 18,
225    #[doc = "19: Select SPI1's RX FIFO as TREQ"]
226    SPI1_RX = 19,
227    #[doc = "20: Select UART0's TX FIFO as TREQ"]
228    UART0_TX = 20,
229    #[doc = "21: Select UART0's RX FIFO as TREQ"]
230    UART0_RX = 21,
231    #[doc = "22: Select UART1's TX FIFO as TREQ"]
232    UART1_TX = 22,
233    #[doc = "23: Select UART1's RX FIFO as TREQ"]
234    UART1_RX = 23,
235    #[doc = "24: Select PWM Counter 0's Wrap Value as TREQ"]
236    PWM_WRAP0 = 24,
237    #[doc = "25: Select PWM Counter 1's Wrap Value as TREQ"]
238    PWM_WRAP1 = 25,
239    #[doc = "26: Select PWM Counter 2's Wrap Value as TREQ"]
240    PWM_WRAP2 = 26,
241    #[doc = "27: Select PWM Counter 3's Wrap Value as TREQ"]
242    PWM_WRAP3 = 27,
243    #[doc = "28: Select PWM Counter 4's Wrap Value as TREQ"]
244    PWM_WRAP4 = 28,
245    #[doc = "29: Select PWM Counter 5's Wrap Value as TREQ"]
246    PWM_WRAP5 = 29,
247    #[doc = "30: Select PWM Counter 6's Wrap Value as TREQ"]
248    PWM_WRAP6 = 30,
249    #[doc = "31: Select PWM Counter 7's Wrap Value as TREQ"]
250    PWM_WRAP7 = 31,
251    #[doc = "32: Select I2C0's TX FIFO as TREQ"]
252    I2C0_TX = 32,
253    #[doc = "33: Select I2C0's RX FIFO as TREQ"]
254    I2C0_RX = 33,
255    #[doc = "34: Select I2C1's TX FIFO as TREQ"]
256    I2C1_TX = 34,
257    #[doc = "35: Select I2C1's RX FIFO as TREQ"]
258    I2C1_RX = 35,
259    #[doc = "36: Select the ADC as TREQ"]
260    ADC = 36,
261    #[doc = "37: Select the XIP Streaming FIFO as TREQ"]
262    XIP_STREAM = 37,
263    #[doc = "38: Select the XIP SSI TX FIFO as TREQ"]
264    XIP_SSITX = 38,
265    #[doc = "39: Select the XIP SSI RX FIFO as TREQ"]
266    XIP_SSIRX = 39,
267    #[doc = "59: Select Timer 0 as TREQ"]
268    TIMER0 = 59,
269    #[doc = "60: Select Timer 1 as TREQ"]
270    TIMER1 = 60,
271    #[doc = "61: Select Timer 2 as TREQ (Optional)"]
272    TIMER2 = 61,
273    #[doc = "62: Select Timer 3 as TREQ (Optional)"]
274    TIMER3 = 62,
275    #[doc = "63: Permanent request, for unpaced transfers."]
276    PERMANENT = 63,
277}
278impl From<TREQ_SEL_A> for u8 {
279    #[inline(always)]
280    fn from(variant: TREQ_SEL_A) -> Self {
281        variant as _
282    }
283}
284impl crate::FieldSpec for TREQ_SEL_A {
285    type Ux = u8;
286}
287impl TREQ_SEL_R {
288    #[doc = "Get enumerated values variant"]
289    #[inline(always)]
290    pub const fn variant(&self) -> Option<TREQ_SEL_A> {
291        match self.bits {
292            0 => Some(TREQ_SEL_A::PIO0_TX0),
293            1 => Some(TREQ_SEL_A::PIO0_TX1),
294            2 => Some(TREQ_SEL_A::PIO0_TX2),
295            3 => Some(TREQ_SEL_A::PIO0_TX3),
296            4 => Some(TREQ_SEL_A::PIO0_RX0),
297            5 => Some(TREQ_SEL_A::PIO0_RX1),
298            6 => Some(TREQ_SEL_A::PIO0_RX2),
299            7 => Some(TREQ_SEL_A::PIO0_RX3),
300            8 => Some(TREQ_SEL_A::PIO1_TX0),
301            9 => Some(TREQ_SEL_A::PIO1_TX1),
302            10 => Some(TREQ_SEL_A::PIO1_TX2),
303            11 => Some(TREQ_SEL_A::PIO1_TX3),
304            12 => Some(TREQ_SEL_A::PIO1_RX0),
305            13 => Some(TREQ_SEL_A::PIO1_RX1),
306            14 => Some(TREQ_SEL_A::PIO1_RX2),
307            15 => Some(TREQ_SEL_A::PIO1_RX3),
308            16 => Some(TREQ_SEL_A::SPI0_TX),
309            17 => Some(TREQ_SEL_A::SPI0_RX),
310            18 => Some(TREQ_SEL_A::SPI1_TX),
311            19 => Some(TREQ_SEL_A::SPI1_RX),
312            20 => Some(TREQ_SEL_A::UART0_TX),
313            21 => Some(TREQ_SEL_A::UART0_RX),
314            22 => Some(TREQ_SEL_A::UART1_TX),
315            23 => Some(TREQ_SEL_A::UART1_RX),
316            24 => Some(TREQ_SEL_A::PWM_WRAP0),
317            25 => Some(TREQ_SEL_A::PWM_WRAP1),
318            26 => Some(TREQ_SEL_A::PWM_WRAP2),
319            27 => Some(TREQ_SEL_A::PWM_WRAP3),
320            28 => Some(TREQ_SEL_A::PWM_WRAP4),
321            29 => Some(TREQ_SEL_A::PWM_WRAP5),
322            30 => Some(TREQ_SEL_A::PWM_WRAP6),
323            31 => Some(TREQ_SEL_A::PWM_WRAP7),
324            32 => Some(TREQ_SEL_A::I2C0_TX),
325            33 => Some(TREQ_SEL_A::I2C0_RX),
326            34 => Some(TREQ_SEL_A::I2C1_TX),
327            35 => Some(TREQ_SEL_A::I2C1_RX),
328            36 => Some(TREQ_SEL_A::ADC),
329            37 => Some(TREQ_SEL_A::XIP_STREAM),
330            38 => Some(TREQ_SEL_A::XIP_SSITX),
331            39 => Some(TREQ_SEL_A::XIP_SSIRX),
332            59 => Some(TREQ_SEL_A::TIMER0),
333            60 => Some(TREQ_SEL_A::TIMER1),
334            61 => Some(TREQ_SEL_A::TIMER2),
335            62 => Some(TREQ_SEL_A::TIMER3),
336            63 => Some(TREQ_SEL_A::PERMANENT),
337            _ => None,
338        }
339    }
340    #[doc = "Select PIO0's TX FIFO 0 as TREQ"]
341    #[inline(always)]
342    pub fn is_pio0_tx0(&self) -> bool {
343        *self == TREQ_SEL_A::PIO0_TX0
344    }
345    #[doc = "Select PIO0's TX FIFO 1 as TREQ"]
346    #[inline(always)]
347    pub fn is_pio0_tx1(&self) -> bool {
348        *self == TREQ_SEL_A::PIO0_TX1
349    }
350    #[doc = "Select PIO0's TX FIFO 2 as TREQ"]
351    #[inline(always)]
352    pub fn is_pio0_tx2(&self) -> bool {
353        *self == TREQ_SEL_A::PIO0_TX2
354    }
355    #[doc = "Select PIO0's TX FIFO 3 as TREQ"]
356    #[inline(always)]
357    pub fn is_pio0_tx3(&self) -> bool {
358        *self == TREQ_SEL_A::PIO0_TX3
359    }
360    #[doc = "Select PIO0's RX FIFO 0 as TREQ"]
361    #[inline(always)]
362    pub fn is_pio0_rx0(&self) -> bool {
363        *self == TREQ_SEL_A::PIO0_RX0
364    }
365    #[doc = "Select PIO0's RX FIFO 1 as TREQ"]
366    #[inline(always)]
367    pub fn is_pio0_rx1(&self) -> bool {
368        *self == TREQ_SEL_A::PIO0_RX1
369    }
370    #[doc = "Select PIO0's RX FIFO 2 as TREQ"]
371    #[inline(always)]
372    pub fn is_pio0_rx2(&self) -> bool {
373        *self == TREQ_SEL_A::PIO0_RX2
374    }
375    #[doc = "Select PIO0's RX FIFO 3 as TREQ"]
376    #[inline(always)]
377    pub fn is_pio0_rx3(&self) -> bool {
378        *self == TREQ_SEL_A::PIO0_RX3
379    }
380    #[doc = "Select PIO1's TX FIFO 0 as TREQ"]
381    #[inline(always)]
382    pub fn is_pio1_tx0(&self) -> bool {
383        *self == TREQ_SEL_A::PIO1_TX0
384    }
385    #[doc = "Select PIO1's TX FIFO 1 as TREQ"]
386    #[inline(always)]
387    pub fn is_pio1_tx1(&self) -> bool {
388        *self == TREQ_SEL_A::PIO1_TX1
389    }
390    #[doc = "Select PIO1's TX FIFO 2 as TREQ"]
391    #[inline(always)]
392    pub fn is_pio1_tx2(&self) -> bool {
393        *self == TREQ_SEL_A::PIO1_TX2
394    }
395    #[doc = "Select PIO1's TX FIFO 3 as TREQ"]
396    #[inline(always)]
397    pub fn is_pio1_tx3(&self) -> bool {
398        *self == TREQ_SEL_A::PIO1_TX3
399    }
400    #[doc = "Select PIO1's RX FIFO 0 as TREQ"]
401    #[inline(always)]
402    pub fn is_pio1_rx0(&self) -> bool {
403        *self == TREQ_SEL_A::PIO1_RX0
404    }
405    #[doc = "Select PIO1's RX FIFO 1 as TREQ"]
406    #[inline(always)]
407    pub fn is_pio1_rx1(&self) -> bool {
408        *self == TREQ_SEL_A::PIO1_RX1
409    }
410    #[doc = "Select PIO1's RX FIFO 2 as TREQ"]
411    #[inline(always)]
412    pub fn is_pio1_rx2(&self) -> bool {
413        *self == TREQ_SEL_A::PIO1_RX2
414    }
415    #[doc = "Select PIO1's RX FIFO 3 as TREQ"]
416    #[inline(always)]
417    pub fn is_pio1_rx3(&self) -> bool {
418        *self == TREQ_SEL_A::PIO1_RX3
419    }
420    #[doc = "Select SPI0's TX FIFO as TREQ"]
421    #[inline(always)]
422    pub fn is_spi0_tx(&self) -> bool {
423        *self == TREQ_SEL_A::SPI0_TX
424    }
425    #[doc = "Select SPI0's RX FIFO as TREQ"]
426    #[inline(always)]
427    pub fn is_spi0_rx(&self) -> bool {
428        *self == TREQ_SEL_A::SPI0_RX
429    }
430    #[doc = "Select SPI1's TX FIFO as TREQ"]
431    #[inline(always)]
432    pub fn is_spi1_tx(&self) -> bool {
433        *self == TREQ_SEL_A::SPI1_TX
434    }
435    #[doc = "Select SPI1's RX FIFO as TREQ"]
436    #[inline(always)]
437    pub fn is_spi1_rx(&self) -> bool {
438        *self == TREQ_SEL_A::SPI1_RX
439    }
440    #[doc = "Select UART0's TX FIFO as TREQ"]
441    #[inline(always)]
442    pub fn is_uart0_tx(&self) -> bool {
443        *self == TREQ_SEL_A::UART0_TX
444    }
445    #[doc = "Select UART0's RX FIFO as TREQ"]
446    #[inline(always)]
447    pub fn is_uart0_rx(&self) -> bool {
448        *self == TREQ_SEL_A::UART0_RX
449    }
450    #[doc = "Select UART1's TX FIFO as TREQ"]
451    #[inline(always)]
452    pub fn is_uart1_tx(&self) -> bool {
453        *self == TREQ_SEL_A::UART1_TX
454    }
455    #[doc = "Select UART1's RX FIFO as TREQ"]
456    #[inline(always)]
457    pub fn is_uart1_rx(&self) -> bool {
458        *self == TREQ_SEL_A::UART1_RX
459    }
460    #[doc = "Select PWM Counter 0's Wrap Value as TREQ"]
461    #[inline(always)]
462    pub fn is_pwm_wrap0(&self) -> bool {
463        *self == TREQ_SEL_A::PWM_WRAP0
464    }
465    #[doc = "Select PWM Counter 1's Wrap Value as TREQ"]
466    #[inline(always)]
467    pub fn is_pwm_wrap1(&self) -> bool {
468        *self == TREQ_SEL_A::PWM_WRAP1
469    }
470    #[doc = "Select PWM Counter 2's Wrap Value as TREQ"]
471    #[inline(always)]
472    pub fn is_pwm_wrap2(&self) -> bool {
473        *self == TREQ_SEL_A::PWM_WRAP2
474    }
475    #[doc = "Select PWM Counter 3's Wrap Value as TREQ"]
476    #[inline(always)]
477    pub fn is_pwm_wrap3(&self) -> bool {
478        *self == TREQ_SEL_A::PWM_WRAP3
479    }
480    #[doc = "Select PWM Counter 4's Wrap Value as TREQ"]
481    #[inline(always)]
482    pub fn is_pwm_wrap4(&self) -> bool {
483        *self == TREQ_SEL_A::PWM_WRAP4
484    }
485    #[doc = "Select PWM Counter 5's Wrap Value as TREQ"]
486    #[inline(always)]
487    pub fn is_pwm_wrap5(&self) -> bool {
488        *self == TREQ_SEL_A::PWM_WRAP5
489    }
490    #[doc = "Select PWM Counter 6's Wrap Value as TREQ"]
491    #[inline(always)]
492    pub fn is_pwm_wrap6(&self) -> bool {
493        *self == TREQ_SEL_A::PWM_WRAP6
494    }
495    #[doc = "Select PWM Counter 7's Wrap Value as TREQ"]
496    #[inline(always)]
497    pub fn is_pwm_wrap7(&self) -> bool {
498        *self == TREQ_SEL_A::PWM_WRAP7
499    }
500    #[doc = "Select I2C0's TX FIFO as TREQ"]
501    #[inline(always)]
502    pub fn is_i2c0_tx(&self) -> bool {
503        *self == TREQ_SEL_A::I2C0_TX
504    }
505    #[doc = "Select I2C0's RX FIFO as TREQ"]
506    #[inline(always)]
507    pub fn is_i2c0_rx(&self) -> bool {
508        *self == TREQ_SEL_A::I2C0_RX
509    }
510    #[doc = "Select I2C1's TX FIFO as TREQ"]
511    #[inline(always)]
512    pub fn is_i2c1_tx(&self) -> bool {
513        *self == TREQ_SEL_A::I2C1_TX
514    }
515    #[doc = "Select I2C1's RX FIFO as TREQ"]
516    #[inline(always)]
517    pub fn is_i2c1_rx(&self) -> bool {
518        *self == TREQ_SEL_A::I2C1_RX
519    }
520    #[doc = "Select the ADC as TREQ"]
521    #[inline(always)]
522    pub fn is_adc(&self) -> bool {
523        *self == TREQ_SEL_A::ADC
524    }
525    #[doc = "Select the XIP Streaming FIFO as TREQ"]
526    #[inline(always)]
527    pub fn is_xip_stream(&self) -> bool {
528        *self == TREQ_SEL_A::XIP_STREAM
529    }
530    #[doc = "Select the XIP SSI TX FIFO as TREQ"]
531    #[inline(always)]
532    pub fn is_xip_ssitx(&self) -> bool {
533        *self == TREQ_SEL_A::XIP_SSITX
534    }
535    #[doc = "Select the XIP SSI RX FIFO as TREQ"]
536    #[inline(always)]
537    pub fn is_xip_ssirx(&self) -> bool {
538        *self == TREQ_SEL_A::XIP_SSIRX
539    }
540    #[doc = "Select Timer 0 as TREQ"]
541    #[inline(always)]
542    pub fn is_timer0(&self) -> bool {
543        *self == TREQ_SEL_A::TIMER0
544    }
545    #[doc = "Select Timer 1 as TREQ"]
546    #[inline(always)]
547    pub fn is_timer1(&self) -> bool {
548        *self == TREQ_SEL_A::TIMER1
549    }
550    #[doc = "Select Timer 2 as TREQ (Optional)"]
551    #[inline(always)]
552    pub fn is_timer2(&self) -> bool {
553        *self == TREQ_SEL_A::TIMER2
554    }
555    #[doc = "Select Timer 3 as TREQ (Optional)"]
556    #[inline(always)]
557    pub fn is_timer3(&self) -> bool {
558        *self == TREQ_SEL_A::TIMER3
559    }
560    #[doc = "Permanent request, for unpaced transfers."]
561    #[inline(always)]
562    pub fn is_permanent(&self) -> bool {
563        *self == TREQ_SEL_A::PERMANENT
564    }
565}
566#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal.  
567 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
568 0x0 to 0x3a -> select DREQ n as TREQ"]
569pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>;
570impl<'a, REG> TREQ_SEL_W<'a, REG>
571where
572    REG: crate::Writable + crate::RegisterSpec,
573    REG::Ux: From<u8>,
574{
575    #[doc = "Select PIO0's TX FIFO 0 as TREQ"]
576    #[inline(always)]
577    pub fn pio0_tx0(self) -> &'a mut crate::W<REG> {
578        self.variant(TREQ_SEL_A::PIO0_TX0)
579    }
580    #[doc = "Select PIO0's TX FIFO 1 as TREQ"]
581    #[inline(always)]
582    pub fn pio0_tx1(self) -> &'a mut crate::W<REG> {
583        self.variant(TREQ_SEL_A::PIO0_TX1)
584    }
585    #[doc = "Select PIO0's TX FIFO 2 as TREQ"]
586    #[inline(always)]
587    pub fn pio0_tx2(self) -> &'a mut crate::W<REG> {
588        self.variant(TREQ_SEL_A::PIO0_TX2)
589    }
590    #[doc = "Select PIO0's TX FIFO 3 as TREQ"]
591    #[inline(always)]
592    pub fn pio0_tx3(self) -> &'a mut crate::W<REG> {
593        self.variant(TREQ_SEL_A::PIO0_TX3)
594    }
595    #[doc = "Select PIO0's RX FIFO 0 as TREQ"]
596    #[inline(always)]
597    pub fn pio0_rx0(self) -> &'a mut crate::W<REG> {
598        self.variant(TREQ_SEL_A::PIO0_RX0)
599    }
600    #[doc = "Select PIO0's RX FIFO 1 as TREQ"]
601    #[inline(always)]
602    pub fn pio0_rx1(self) -> &'a mut crate::W<REG> {
603        self.variant(TREQ_SEL_A::PIO0_RX1)
604    }
605    #[doc = "Select PIO0's RX FIFO 2 as TREQ"]
606    #[inline(always)]
607    pub fn pio0_rx2(self) -> &'a mut crate::W<REG> {
608        self.variant(TREQ_SEL_A::PIO0_RX2)
609    }
610    #[doc = "Select PIO0's RX FIFO 3 as TREQ"]
611    #[inline(always)]
612    pub fn pio0_rx3(self) -> &'a mut crate::W<REG> {
613        self.variant(TREQ_SEL_A::PIO0_RX3)
614    }
615    #[doc = "Select PIO1's TX FIFO 0 as TREQ"]
616    #[inline(always)]
617    pub fn pio1_tx0(self) -> &'a mut crate::W<REG> {
618        self.variant(TREQ_SEL_A::PIO1_TX0)
619    }
620    #[doc = "Select PIO1's TX FIFO 1 as TREQ"]
621    #[inline(always)]
622    pub fn pio1_tx1(self) -> &'a mut crate::W<REG> {
623        self.variant(TREQ_SEL_A::PIO1_TX1)
624    }
625    #[doc = "Select PIO1's TX FIFO 2 as TREQ"]
626    #[inline(always)]
627    pub fn pio1_tx2(self) -> &'a mut crate::W<REG> {
628        self.variant(TREQ_SEL_A::PIO1_TX2)
629    }
630    #[doc = "Select PIO1's TX FIFO 3 as TREQ"]
631    #[inline(always)]
632    pub fn pio1_tx3(self) -> &'a mut crate::W<REG> {
633        self.variant(TREQ_SEL_A::PIO1_TX3)
634    }
635    #[doc = "Select PIO1's RX FIFO 0 as TREQ"]
636    #[inline(always)]
637    pub fn pio1_rx0(self) -> &'a mut crate::W<REG> {
638        self.variant(TREQ_SEL_A::PIO1_RX0)
639    }
640    #[doc = "Select PIO1's RX FIFO 1 as TREQ"]
641    #[inline(always)]
642    pub fn pio1_rx1(self) -> &'a mut crate::W<REG> {
643        self.variant(TREQ_SEL_A::PIO1_RX1)
644    }
645    #[doc = "Select PIO1's RX FIFO 2 as TREQ"]
646    #[inline(always)]
647    pub fn pio1_rx2(self) -> &'a mut crate::W<REG> {
648        self.variant(TREQ_SEL_A::PIO1_RX2)
649    }
650    #[doc = "Select PIO1's RX FIFO 3 as TREQ"]
651    #[inline(always)]
652    pub fn pio1_rx3(self) -> &'a mut crate::W<REG> {
653        self.variant(TREQ_SEL_A::PIO1_RX3)
654    }
655    #[doc = "Select SPI0's TX FIFO as TREQ"]
656    #[inline(always)]
657    pub fn spi0_tx(self) -> &'a mut crate::W<REG> {
658        self.variant(TREQ_SEL_A::SPI0_TX)
659    }
660    #[doc = "Select SPI0's RX FIFO as TREQ"]
661    #[inline(always)]
662    pub fn spi0_rx(self) -> &'a mut crate::W<REG> {
663        self.variant(TREQ_SEL_A::SPI0_RX)
664    }
665    #[doc = "Select SPI1's TX FIFO as TREQ"]
666    #[inline(always)]
667    pub fn spi1_tx(self) -> &'a mut crate::W<REG> {
668        self.variant(TREQ_SEL_A::SPI1_TX)
669    }
670    #[doc = "Select SPI1's RX FIFO as TREQ"]
671    #[inline(always)]
672    pub fn spi1_rx(self) -> &'a mut crate::W<REG> {
673        self.variant(TREQ_SEL_A::SPI1_RX)
674    }
675    #[doc = "Select UART0's TX FIFO as TREQ"]
676    #[inline(always)]
677    pub fn uart0_tx(self) -> &'a mut crate::W<REG> {
678        self.variant(TREQ_SEL_A::UART0_TX)
679    }
680    #[doc = "Select UART0's RX FIFO as TREQ"]
681    #[inline(always)]
682    pub fn uart0_rx(self) -> &'a mut crate::W<REG> {
683        self.variant(TREQ_SEL_A::UART0_RX)
684    }
685    #[doc = "Select UART1's TX FIFO as TREQ"]
686    #[inline(always)]
687    pub fn uart1_tx(self) -> &'a mut crate::W<REG> {
688        self.variant(TREQ_SEL_A::UART1_TX)
689    }
690    #[doc = "Select UART1's RX FIFO as TREQ"]
691    #[inline(always)]
692    pub fn uart1_rx(self) -> &'a mut crate::W<REG> {
693        self.variant(TREQ_SEL_A::UART1_RX)
694    }
695    #[doc = "Select PWM Counter 0's Wrap Value as TREQ"]
696    #[inline(always)]
697    pub fn pwm_wrap0(self) -> &'a mut crate::W<REG> {
698        self.variant(TREQ_SEL_A::PWM_WRAP0)
699    }
700    #[doc = "Select PWM Counter 1's Wrap Value as TREQ"]
701    #[inline(always)]
702    pub fn pwm_wrap1(self) -> &'a mut crate::W<REG> {
703        self.variant(TREQ_SEL_A::PWM_WRAP1)
704    }
705    #[doc = "Select PWM Counter 2's Wrap Value as TREQ"]
706    #[inline(always)]
707    pub fn pwm_wrap2(self) -> &'a mut crate::W<REG> {
708        self.variant(TREQ_SEL_A::PWM_WRAP2)
709    }
710    #[doc = "Select PWM Counter 3's Wrap Value as TREQ"]
711    #[inline(always)]
712    pub fn pwm_wrap3(self) -> &'a mut crate::W<REG> {
713        self.variant(TREQ_SEL_A::PWM_WRAP3)
714    }
715    #[doc = "Select PWM Counter 4's Wrap Value as TREQ"]
716    #[inline(always)]
717    pub fn pwm_wrap4(self) -> &'a mut crate::W<REG> {
718        self.variant(TREQ_SEL_A::PWM_WRAP4)
719    }
720    #[doc = "Select PWM Counter 5's Wrap Value as TREQ"]
721    #[inline(always)]
722    pub fn pwm_wrap5(self) -> &'a mut crate::W<REG> {
723        self.variant(TREQ_SEL_A::PWM_WRAP5)
724    }
725    #[doc = "Select PWM Counter 6's Wrap Value as TREQ"]
726    #[inline(always)]
727    pub fn pwm_wrap6(self) -> &'a mut crate::W<REG> {
728        self.variant(TREQ_SEL_A::PWM_WRAP6)
729    }
730    #[doc = "Select PWM Counter 7's Wrap Value as TREQ"]
731    #[inline(always)]
732    pub fn pwm_wrap7(self) -> &'a mut crate::W<REG> {
733        self.variant(TREQ_SEL_A::PWM_WRAP7)
734    }
735    #[doc = "Select I2C0's TX FIFO as TREQ"]
736    #[inline(always)]
737    pub fn i2c0_tx(self) -> &'a mut crate::W<REG> {
738        self.variant(TREQ_SEL_A::I2C0_TX)
739    }
740    #[doc = "Select I2C0's RX FIFO as TREQ"]
741    #[inline(always)]
742    pub fn i2c0_rx(self) -> &'a mut crate::W<REG> {
743        self.variant(TREQ_SEL_A::I2C0_RX)
744    }
745    #[doc = "Select I2C1's TX FIFO as TREQ"]
746    #[inline(always)]
747    pub fn i2c1_tx(self) -> &'a mut crate::W<REG> {
748        self.variant(TREQ_SEL_A::I2C1_TX)
749    }
750    #[doc = "Select I2C1's RX FIFO as TREQ"]
751    #[inline(always)]
752    pub fn i2c1_rx(self) -> &'a mut crate::W<REG> {
753        self.variant(TREQ_SEL_A::I2C1_RX)
754    }
755    #[doc = "Select the ADC as TREQ"]
756    #[inline(always)]
757    pub fn adc(self) -> &'a mut crate::W<REG> {
758        self.variant(TREQ_SEL_A::ADC)
759    }
760    #[doc = "Select the XIP Streaming FIFO as TREQ"]
761    #[inline(always)]
762    pub fn xip_stream(self) -> &'a mut crate::W<REG> {
763        self.variant(TREQ_SEL_A::XIP_STREAM)
764    }
765    #[doc = "Select the XIP SSI TX FIFO as TREQ"]
766    #[inline(always)]
767    pub fn xip_ssitx(self) -> &'a mut crate::W<REG> {
768        self.variant(TREQ_SEL_A::XIP_SSITX)
769    }
770    #[doc = "Select the XIP SSI RX FIFO as TREQ"]
771    #[inline(always)]
772    pub fn xip_ssirx(self) -> &'a mut crate::W<REG> {
773        self.variant(TREQ_SEL_A::XIP_SSIRX)
774    }
775    #[doc = "Select Timer 0 as TREQ"]
776    #[inline(always)]
777    pub fn timer0(self) -> &'a mut crate::W<REG> {
778        self.variant(TREQ_SEL_A::TIMER0)
779    }
780    #[doc = "Select Timer 1 as TREQ"]
781    #[inline(always)]
782    pub fn timer1(self) -> &'a mut crate::W<REG> {
783        self.variant(TREQ_SEL_A::TIMER1)
784    }
785    #[doc = "Select Timer 2 as TREQ (Optional)"]
786    #[inline(always)]
787    pub fn timer2(self) -> &'a mut crate::W<REG> {
788        self.variant(TREQ_SEL_A::TIMER2)
789    }
790    #[doc = "Select Timer 3 as TREQ (Optional)"]
791    #[inline(always)]
792    pub fn timer3(self) -> &'a mut crate::W<REG> {
793        self.variant(TREQ_SEL_A::TIMER3)
794    }
795    #[doc = "Permanent request, for unpaced transfers."]
796    #[inline(always)]
797    pub fn permanent(self) -> &'a mut crate::W<REG> {
798        self.variant(TREQ_SEL_A::PERMANENT)
799    }
800}
801#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.  
802
803 This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
804pub type IRQ_QUIET_R = crate::BitReader;
805#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.  
806
807 This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
808pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>;
809#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data.  
810 For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
811pub type BSWAP_R = crate::BitReader;
812#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data.  
813 For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
814pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
815#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.  
816
817 This allows checksum to be enabled or disabled on a per-control- block basis."]
818pub type SNIFF_EN_R = crate::BitReader;
819#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.  
820
821 This allows checksum to be enabled or disabled on a per-control- block basis."]
822pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
823#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.  
824
825 To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."]
826pub type BUSY_R = crate::BitReader;
827#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear.  
828 WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
829pub type WRITE_ERROR_R = crate::BitReader;
830#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear.  
831 WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
832pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
833#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear.  
834 READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
835pub type READ_ERROR_R = crate::BitReader;
836#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear.  
837 READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
838pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
839#[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."]
840pub type AHB_ERROR_R = crate::BitReader;
841impl R {
842    #[doc = "Bit 0 - DMA Channel Enable.  
843 When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
844    #[inline(always)]
845    pub fn en(&self) -> EN_R {
846        EN_R::new((self.bits & 1) != 0)
847    }
848    #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.  
849
850 This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
851    #[inline(always)]
852    pub fn high_priority(&self) -> HIGH_PRIORITY_R {
853        HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0)
854    }
855    #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
856    #[inline(always)]
857    pub fn data_size(&self) -> DATA_SIZE_R {
858        DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8)
859    }
860    #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.  
861
862 Generally this should be disabled for peripheral-to-memory transfers."]
863    #[inline(always)]
864    pub fn incr_read(&self) -> INCR_READ_R {
865        INCR_READ_R::new(((self.bits >> 4) & 1) != 0)
866    }
867    #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.  
868
869 Generally this should be disabled for memory-to-peripheral transfers."]
870    #[inline(always)]
871    pub fn incr_write(&self) -> INCR_WRITE_R {
872        INCR_WRITE_R::new(((self.bits >> 5) & 1) != 0)
873    }
874    #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
875
876 Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
877    #[inline(always)]
878    pub fn ring_size(&self) -> RING_SIZE_R {
879        RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8)
880    }
881    #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses.  
882 If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
883    #[inline(always)]
884    pub fn ring_sel(&self) -> RING_SEL_R {
885        RING_SEL_R::new(((self.bits >> 10) & 1) != 0)
886    }
887    #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
888 Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
889    #[inline(always)]
890    pub fn chain_to(&self) -> CHAIN_TO_R {
891        CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8)
892    }
893    #[doc = "Bits 15:20 - Select a Transfer Request signal.  
894 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
895 0x0 to 0x3a -> select DREQ n as TREQ"]
896    #[inline(always)]
897    pub fn treq_sel(&self) -> TREQ_SEL_R {
898        TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8)
899    }
900    #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.  
901
902 This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
903    #[inline(always)]
904    pub fn irq_quiet(&self) -> IRQ_QUIET_R {
905        IRQ_QUIET_R::new(((self.bits >> 21) & 1) != 0)
906    }
907    #[doc = "Bit 22 - Apply byte-swap transformation to DMA data.  
908 For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
909    #[inline(always)]
910    pub fn bswap(&self) -> BSWAP_R {
911        BSWAP_R::new(((self.bits >> 22) & 1) != 0)
912    }
913    #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.  
914
915 This allows checksum to be enabled or disabled on a per-control- block basis."]
916    #[inline(always)]
917    pub fn sniff_en(&self) -> SNIFF_EN_R {
918        SNIFF_EN_R::new(((self.bits >> 23) & 1) != 0)
919    }
920    #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.  
921
922 To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."]
923    #[inline(always)]
924    pub fn busy(&self) -> BUSY_R {
925        BUSY_R::new(((self.bits >> 24) & 1) != 0)
926    }
927    #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear.  
928 WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
929    #[inline(always)]
930    pub fn write_error(&self) -> WRITE_ERROR_R {
931        WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0)
932    }
933    #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear.  
934 READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
935    #[inline(always)]
936    pub fn read_error(&self) -> READ_ERROR_R {
937        READ_ERROR_R::new(((self.bits >> 30) & 1) != 0)
938    }
939    #[doc = "Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."]
940    #[inline(always)]
941    pub fn ahb_error(&self) -> AHB_ERROR_R {
942        AHB_ERROR_R::new(((self.bits >> 31) & 1) != 0)
943    }
944}
945impl W {
946    #[doc = "Bit 0 - DMA Channel Enable.  
947 When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
948    #[inline(always)]
949    #[must_use]
950    pub fn en(&mut self) -> EN_W<CH_AL3_CTRL_SPEC> {
951        EN_W::new(self, 0)
952    }
953    #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.  
954
955 This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
956    #[inline(always)]
957    #[must_use]
958    pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<CH_AL3_CTRL_SPEC> {
959        HIGH_PRIORITY_W::new(self, 1)
960    }
961    #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
962    #[inline(always)]
963    #[must_use]
964    pub fn data_size(&mut self) -> DATA_SIZE_W<CH_AL3_CTRL_SPEC> {
965        DATA_SIZE_W::new(self, 2)
966    }
967    #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.  
968
969 Generally this should be disabled for peripheral-to-memory transfers."]
970    #[inline(always)]
971    #[must_use]
972    pub fn incr_read(&mut self) -> INCR_READ_W<CH_AL3_CTRL_SPEC> {
973        INCR_READ_W::new(self, 4)
974    }
975    #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.  
976
977 Generally this should be disabled for memory-to-peripheral transfers."]
978    #[inline(always)]
979    #[must_use]
980    pub fn incr_write(&mut self) -> INCR_WRITE_W<CH_AL3_CTRL_SPEC> {
981        INCR_WRITE_W::new(self, 5)
982    }
983    #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
984
985 Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
986    #[inline(always)]
987    #[must_use]
988    pub fn ring_size(&mut self) -> RING_SIZE_W<CH_AL3_CTRL_SPEC> {
989        RING_SIZE_W::new(self, 6)
990    }
991    #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses.  
992 If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
993    #[inline(always)]
994    #[must_use]
995    pub fn ring_sel(&mut self) -> RING_SEL_W<CH_AL3_CTRL_SPEC> {
996        RING_SEL_W::new(self, 10)
997    }
998    #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
999 Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
1000    #[inline(always)]
1001    #[must_use]
1002    pub fn chain_to(&mut self) -> CHAIN_TO_W<CH_AL3_CTRL_SPEC> {
1003        CHAIN_TO_W::new(self, 11)
1004    }
1005    #[doc = "Bits 15:20 - Select a Transfer Request signal.  
1006 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
1007 0x0 to 0x3a -> select DREQ n as TREQ"]
1008    #[inline(always)]
1009    #[must_use]
1010    pub fn treq_sel(&mut self) -> TREQ_SEL_W<CH_AL3_CTRL_SPEC> {
1011        TREQ_SEL_W::new(self, 15)
1012    }
1013    #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.  
1014
1015 This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
1016    #[inline(always)]
1017    #[must_use]
1018    pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<CH_AL3_CTRL_SPEC> {
1019        IRQ_QUIET_W::new(self, 21)
1020    }
1021    #[doc = "Bit 22 - Apply byte-swap transformation to DMA data.  
1022 For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
1023    #[inline(always)]
1024    #[must_use]
1025    pub fn bswap(&mut self) -> BSWAP_W<CH_AL3_CTRL_SPEC> {
1026        BSWAP_W::new(self, 22)
1027    }
1028    #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.  
1029
1030 This allows checksum to be enabled or disabled on a per-control- block basis."]
1031    #[inline(always)]
1032    #[must_use]
1033    pub fn sniff_en(&mut self) -> SNIFF_EN_W<CH_AL3_CTRL_SPEC> {
1034        SNIFF_EN_W::new(self, 23)
1035    }
1036    #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear.  
1037 WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
1038    #[inline(always)]
1039    #[must_use]
1040    pub fn write_error(&mut self) -> WRITE_ERROR_W<CH_AL3_CTRL_SPEC> {
1041        WRITE_ERROR_W::new(self, 29)
1042    }
1043    #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear.  
1044 READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
1045    #[inline(always)]
1046    #[must_use]
1047    pub fn read_error(&mut self) -> READ_ERROR_W<CH_AL3_CTRL_SPEC> {
1048        READ_ERROR_W::new(self, 30)
1049    }
1050    #[doc = r" Writes raw bits to the register."]
1051    #[doc = r""]
1052    #[doc = r" # Safety"]
1053    #[doc = r""]
1054    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1055    #[inline(always)]
1056    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1057        self.bits = bits;
1058        self
1059    }
1060}
1061#[doc = "DMA Channel 0 Control and Status  
1062
1063You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1064pub struct CH_AL3_CTRL_SPEC;
1065impl crate::RegisterSpec for CH_AL3_CTRL_SPEC {
1066    type Ux = u32;
1067}
1068#[doc = "`read()` method returns [`ch_al3_ctrl::R`](R) reader structure"]
1069impl crate::Readable for CH_AL3_CTRL_SPEC {}
1070#[doc = "`write(|w| ..)` method takes [`ch_al3_ctrl::W`](W) writer structure"]
1071impl crate::Writable for CH_AL3_CTRL_SPEC {
1072    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1073    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000;
1074}
1075#[doc = "`reset()` method sets CH_AL3_CTRL to value 0"]
1076impl crate::Resettable for CH_AL3_CTRL_SPEC {
1077    const RESET_VALUE: u32 = 0;
1078}
rp2040_pac/dma/ch/ch_al3_ctrl.rs

rp2040_pac/dma/ch/
ch_al3_ctrl.rs
