rp2040_pac/sio/
interp0_base0.rs

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1#[doc = "Register `INTERP0_BASE0` reader"]
2pub type R = crate::R<INTERP0_BASE0_SPEC>;
3#[doc = "Register `INTERP0_BASE0` writer"]
4pub type W = crate::W<INTERP0_BASE0_SPEC>;
5impl core::fmt::Debug for R {
6    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7        write!(f, "{}", self.bits())
8    }
9}
10impl core::fmt::Debug for crate::generic::Reg<INTERP0_BASE0_SPEC> {
11    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12        core::fmt::Debug::fmt(&self.read(), f)
13    }
14}
15impl W {
16    #[doc = r" Writes raw bits to the register."]
17    #[doc = r""]
18    #[doc = r" # Safety"]
19    #[doc = r""]
20    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
21    #[inline(always)]
22    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
23        self.bits = bits;
24        self
25    }
26}
27#[doc = "Read/write access to BASE0 register.  
28
29You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct INTERP0_BASE0_SPEC;
31impl crate::RegisterSpec for INTERP0_BASE0_SPEC {
32    type Ux = u32;
33}
34#[doc = "`read()` method returns [`interp0_base0::R`](R) reader structure"]
35impl crate::Readable for INTERP0_BASE0_SPEC {}
36#[doc = "`write(|w| ..)` method takes [`interp0_base0::W`](W) writer structure"]
37impl crate::Writable for INTERP0_BASE0_SPEC {
38    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
39    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
40}
41#[doc = "`reset()` method sets INTERP0_BASE0 to value 0"]
42impl crate::Resettable for INTERP0_BASE0_SPEC {
43    const RESET_VALUE: u32 = 0;
44}
rp2040_pac/sio/interp0_base0.rs

rp2040_pac/sio/
interp0_base0.rs
