rp2040_pac/uart0/
uartifls.rs

Help
1#[doc = "Register `UARTIFLS` reader"]
2pub type R = crate::R<UARTIFLS_SPEC>;
3#[doc = "Register `UARTIFLS` writer"]
4pub type W = crate::W<UARTIFLS_SPEC>;
5#[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
6pub type TXIFLSEL_R = crate::FieldReader;
7#[doc = "Field `TXIFLSEL` writer - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
8pub type TXIFLSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `RXIFLSEL` reader - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
10pub type RXIFLSEL_R = crate::FieldReader;
11#[doc = "Field `RXIFLSEL` writer - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
12pub type RXIFLSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13impl R {
14    #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
15    #[inline(always)]
16    pub fn txiflsel(&self) -> TXIFLSEL_R {
17        TXIFLSEL_R::new((self.bits & 7) as u8)
18    }
19    #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
20    #[inline(always)]
21    pub fn rxiflsel(&self) -> RXIFLSEL_R {
22        RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8)
23    }
24}
25impl W {
26    #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
27    #[inline(always)]
28    #[must_use]
29    pub fn txiflsel(&mut self) -> TXIFLSEL_W<UARTIFLS_SPEC> {
30        TXIFLSEL_W::new(self, 0)
31    }
32    #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
33    #[inline(always)]
34    #[must_use]
35    pub fn rxiflsel(&mut self) -> RXIFLSEL_W<UARTIFLS_SPEC> {
36        RXIFLSEL_W::new(self, 3)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "Interrupt FIFO Level Select Register, UARTIFLS  
50
51You can [`read`](crate::generic::Reg::read) this register and get [`uartifls::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
52pub struct UARTIFLS_SPEC;
53impl crate::RegisterSpec for UARTIFLS_SPEC {
54    type Ux = u32;
55}
56#[doc = "`read()` method returns [`uartifls::R`](R) reader structure"]
57impl crate::Readable for UARTIFLS_SPEC {}
58#[doc = "`write(|w| ..)` method takes [`uartifls::W`](W) writer structure"]
59impl crate::Writable for UARTIFLS_SPEC {
60    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
61    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62}
63#[doc = "`reset()` method sets UARTIFLS to value 0x12"]
64impl crate::Resettable for UARTIFLS_SPEC {
65    const RESET_VALUE: u32 = 0x12;
66}
rp2040_pac/uart0/uartifls.rs

rp2040_pac/uart0/
uartifls.rs
