rp2040_pac/clocks/
clk_ref_ctrl.rs

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1#[doc = "Register `CLK_REF_CTRL` reader"]
2pub type R = crate::R<CLK_REF_CTRL_SPEC>;
3#[doc = "Register `CLK_REF_CTRL` writer"]
4pub type W = crate::W<CLK_REF_CTRL_SPEC>;
5#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"]
6pub type SRC_R = crate::FieldReader<SRC_A>;
7#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly  
8
9Value on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum SRC_A {
13    #[doc = "0: `0`"]
14    ROSC_CLKSRC_PH = 0,
15    #[doc = "1: `1`"]
16    CLKSRC_CLK_REF_AUX = 1,
17    #[doc = "2: `10`"]
18    XOSC_CLKSRC = 2,
19}
20impl From<SRC_A> for u8 {
21    #[inline(always)]
22    fn from(variant: SRC_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for SRC_A {
27    type Ux = u8;
28}
29impl SRC_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<SRC_A> {
33        match self.bits {
34            0 => Some(SRC_A::ROSC_CLKSRC_PH),
35            1 => Some(SRC_A::CLKSRC_CLK_REF_AUX),
36            2 => Some(SRC_A::XOSC_CLKSRC),
37            _ => None,
38        }
39    }
40    #[doc = "`0`"]
41    #[inline(always)]
42    pub fn is_rosc_clksrc_ph(&self) -> bool {
43        *self == SRC_A::ROSC_CLKSRC_PH
44    }
45    #[doc = "`1`"]
46    #[inline(always)]
47    pub fn is_clksrc_clk_ref_aux(&self) -> bool {
48        *self == SRC_A::CLKSRC_CLK_REF_AUX
49    }
50    #[doc = "`10`"]
51    #[inline(always)]
52    pub fn is_xosc_clksrc(&self) -> bool {
53        *self == SRC_A::XOSC_CLKSRC
54    }
55}
56#[doc = "Field `SRC` writer - Selects the clock source glitchlessly, can be changed on-the-fly"]
57pub type SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SRC_A>;
58impl<'a, REG> SRC_W<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61    REG::Ux: From<u8>,
62{
63    #[doc = "`0`"]
64    #[inline(always)]
65    pub fn rosc_clksrc_ph(self) -> &'a mut crate::W<REG> {
66        self.variant(SRC_A::ROSC_CLKSRC_PH)
67    }
68    #[doc = "`1`"]
69    #[inline(always)]
70    pub fn clksrc_clk_ref_aux(self) -> &'a mut crate::W<REG> {
71        self.variant(SRC_A::CLKSRC_CLK_REF_AUX)
72    }
73    #[doc = "`10`"]
74    #[inline(always)]
75    pub fn xosc_clksrc(self) -> &'a mut crate::W<REG> {
76        self.variant(SRC_A::XOSC_CLKSRC)
77    }
78}
79#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
80pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
81#[doc = "Selects the auxiliary clock source, will glitch when switching  
82
83Value on reset: 0"]
84#[derive(Clone, Copy, Debug, PartialEq, Eq)]
85#[repr(u8)]
86pub enum AUXSRC_A {
87    #[doc = "0: `0`"]
88    CLKSRC_PLL_USB = 0,
89    #[doc = "1: `1`"]
90    CLKSRC_GPIN0 = 1,
91    #[doc = "2: `10`"]
92    CLKSRC_GPIN1 = 2,
93}
94impl From<AUXSRC_A> for u8 {
95    #[inline(always)]
96    fn from(variant: AUXSRC_A) -> Self {
97        variant as _
98    }
99}
100impl crate::FieldSpec for AUXSRC_A {
101    type Ux = u8;
102}
103impl AUXSRC_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub const fn variant(&self) -> Option<AUXSRC_A> {
107        match self.bits {
108            0 => Some(AUXSRC_A::CLKSRC_PLL_USB),
109            1 => Some(AUXSRC_A::CLKSRC_GPIN0),
110            2 => Some(AUXSRC_A::CLKSRC_GPIN1),
111            _ => None,
112        }
113    }
114    #[doc = "`0`"]
115    #[inline(always)]
116    pub fn is_clksrc_pll_usb(&self) -> bool {
117        *self == AUXSRC_A::CLKSRC_PLL_USB
118    }
119    #[doc = "`1`"]
120    #[inline(always)]
121    pub fn is_clksrc_gpin0(&self) -> bool {
122        *self == AUXSRC_A::CLKSRC_GPIN0
123    }
124    #[doc = "`10`"]
125    #[inline(always)]
126    pub fn is_clksrc_gpin1(&self) -> bool {
127        *self == AUXSRC_A::CLKSRC_GPIN1
128    }
129}
130#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"]
131pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, AUXSRC_A>;
132impl<'a, REG> AUXSRC_W<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135    REG::Ux: From<u8>,
136{
137    #[doc = "`0`"]
138    #[inline(always)]
139    pub fn clksrc_pll_usb(self) -> &'a mut crate::W<REG> {
140        self.variant(AUXSRC_A::CLKSRC_PLL_USB)
141    }
142    #[doc = "`1`"]
143    #[inline(always)]
144    pub fn clksrc_gpin0(self) -> &'a mut crate::W<REG> {
145        self.variant(AUXSRC_A::CLKSRC_GPIN0)
146    }
147    #[doc = "`10`"]
148    #[inline(always)]
149    pub fn clksrc_gpin1(self) -> &'a mut crate::W<REG> {
150        self.variant(AUXSRC_A::CLKSRC_GPIN1)
151    }
152}
153impl R {
154    #[doc = "Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly"]
155    #[inline(always)]
156    pub fn src(&self) -> SRC_R {
157        SRC_R::new((self.bits & 3) as u8)
158    }
159    #[doc = "Bits 5:6 - Selects the auxiliary clock source, will glitch when switching"]
160    #[inline(always)]
161    pub fn auxsrc(&self) -> AUXSRC_R {
162        AUXSRC_R::new(((self.bits >> 5) & 3) as u8)
163    }
164}
165impl W {
166    #[doc = "Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly"]
167    #[inline(always)]
168    #[must_use]
169    pub fn src(&mut self) -> SRC_W<CLK_REF_CTRL_SPEC> {
170        SRC_W::new(self, 0)
171    }
172    #[doc = "Bits 5:6 - Selects the auxiliary clock source, will glitch when switching"]
173    #[inline(always)]
174    #[must_use]
175    pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_REF_CTRL_SPEC> {
176        AUXSRC_W::new(self, 5)
177    }
178    #[doc = r" Writes raw bits to the register."]
179    #[doc = r""]
180    #[doc = r" # Safety"]
181    #[doc = r""]
182    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
183    #[inline(always)]
184    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
185        self.bits = bits;
186        self
187    }
188}
189#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
190
191You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
192pub struct CLK_REF_CTRL_SPEC;
193impl crate::RegisterSpec for CLK_REF_CTRL_SPEC {
194    type Ux = u32;
195}
196#[doc = "`read()` method returns [`clk_ref_ctrl::R`](R) reader structure"]
197impl crate::Readable for CLK_REF_CTRL_SPEC {}
198#[doc = "`write(|w| ..)` method takes [`clk_ref_ctrl::W`](W) writer structure"]
199impl crate::Writable for CLK_REF_CTRL_SPEC {
200    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
201    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
202}
203#[doc = "`reset()` method sets CLK_REF_CTRL to value 0"]
204impl crate::Resettable for CLK_REF_CTRL_SPEC {
205    const RESET_VALUE: u32 = 0;
206}
rp2040_pac/clocks/clk_ref_ctrl.rs

rp2040_pac/clocks/
clk_ref_ctrl.rs
