imxrt_ral/blocks/imxrt1011/
sai.rs
1#[doc = "I2S"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Version ID Register"]
5 pub VERID: crate::RORegister<u32>,
6 #[doc = "Parameter Register"]
7 pub PARAM: crate::RORegister<u32>,
8 #[doc = "SAI Transmit Control Register"]
9 pub TCSR: crate::RWRegister<u32>,
10 #[doc = "SAI Transmit Configuration 1 Register"]
11 pub TCR1: crate::RWRegister<u32>,
12 #[doc = "SAI Transmit Configuration 2 Register"]
13 pub TCR2: crate::RWRegister<u32>,
14 #[doc = "SAI Transmit Configuration 3 Register"]
15 pub TCR3: crate::RWRegister<u32>,
16 #[doc = "SAI Transmit Configuration 4 Register"]
17 pub TCR4: crate::RWRegister<u32>,
18 #[doc = "SAI Transmit Configuration 5 Register"]
19 pub TCR5: crate::RWRegister<u32>,
20 #[doc = "SAI Transmit Data Register"]
21 pub TDR: [crate::RWRegister<u32>; 2usize],
22 _reserved0: [u8; 0x18],
23 #[doc = "SAI Transmit FIFO Register"]
24 pub TFR: [crate::RORegister<u32>; 2usize],
25 _reserved1: [u8; 0x18],
26 #[doc = "SAI Transmit Mask Register"]
27 pub TMR: crate::RWRegister<u32>,
28 _reserved2: [u8; 0x24],
29 #[doc = "SAI Receive Control Register"]
30 pub RCSR: crate::RWRegister<u32>,
31 #[doc = "SAI Receive Configuration 1 Register"]
32 pub RCR1: crate::RWRegister<u32>,
33 #[doc = "SAI Receive Configuration 2 Register"]
34 pub RCR2: crate::RWRegister<u32>,
35 #[doc = "SAI Receive Configuration 3 Register"]
36 pub RCR3: crate::RWRegister<u32>,
37 #[doc = "SAI Receive Configuration 4 Register"]
38 pub RCR4: crate::RWRegister<u32>,
39 #[doc = "SAI Receive Configuration 5 Register"]
40 pub RCR5: crate::RWRegister<u32>,
41 #[doc = "SAI Receive Data Register"]
42 pub RDR: [crate::RORegister<u32>; 2usize],
43 _reserved3: [u8; 0x18],
44 #[doc = "SAI Receive FIFO Register"]
45 pub RFR: [crate::RORegister<u32>; 2usize],
46 _reserved4: [u8; 0x18],
47 #[doc = "SAI Receive Mask Register"]
48 pub RMR: crate::RWRegister<u32>,
49}
50#[doc = "Version ID Register"]
51pub mod VERID {
52 #[doc = "Feature Specification Number"]
53 pub mod FEATURE {
54 pub const offset: u32 = 0;
55 pub const mask: u32 = 0xffff << offset;
56 pub mod R {}
57 pub mod W {}
58 pub mod RW {
59 #[doc = "Standard feature set."]
60 pub const FEATURE_0: u32 = 0;
61 }
62 }
63 #[doc = "Minor Version Number"]
64 pub mod MINOR {
65 pub const offset: u32 = 16;
66 pub const mask: u32 = 0xff << offset;
67 pub mod R {}
68 pub mod W {}
69 pub mod RW {}
70 }
71 #[doc = "Major Version Number"]
72 pub mod MAJOR {
73 pub const offset: u32 = 24;
74 pub const mask: u32 = 0xff << offset;
75 pub mod R {}
76 pub mod W {}
77 pub mod RW {}
78 }
79}
80#[doc = "Parameter Register"]
81pub mod PARAM {
82 #[doc = "Number of Datalines"]
83 pub mod DATALINE {
84 pub const offset: u32 = 0;
85 pub const mask: u32 = 0x0f << offset;
86 pub mod R {}
87 pub mod W {}
88 pub mod RW {}
89 }
90 #[doc = "FIFO Size"]
91 pub mod FIFO {
92 pub const offset: u32 = 8;
93 pub const mask: u32 = 0x0f << offset;
94 pub mod R {}
95 pub mod W {}
96 pub mod RW {}
97 }
98 #[doc = "Frame Size"]
99 pub mod FRAME {
100 pub const offset: u32 = 16;
101 pub const mask: u32 = 0x0f << offset;
102 pub mod R {}
103 pub mod W {}
104 pub mod RW {}
105 }
106}
107#[doc = "SAI Transmit Control Register"]
108pub mod TCSR {
109 #[doc = "FIFO Request DMA Enable"]
110 pub mod FRDE {
111 pub const offset: u32 = 0;
112 pub const mask: u32 = 0x01 << offset;
113 pub mod R {}
114 pub mod W {}
115 pub mod RW {
116 #[doc = "Disables the DMA request."]
117 pub const FRDE_0: u32 = 0;
118 #[doc = "Enables the DMA request."]
119 pub const FRDE_1: u32 = 0x01;
120 }
121 }
122 #[doc = "FIFO Warning DMA Enable"]
123 pub mod FWDE {
124 pub const offset: u32 = 1;
125 pub const mask: u32 = 0x01 << offset;
126 pub mod R {}
127 pub mod W {}
128 pub mod RW {
129 #[doc = "Disables the DMA request."]
130 pub const FWDE_0: u32 = 0;
131 #[doc = "Enables the DMA request."]
132 pub const FWDE_1: u32 = 0x01;
133 }
134 }
135 #[doc = "FIFO Request Interrupt Enable"]
136 pub mod FRIE {
137 pub const offset: u32 = 8;
138 pub const mask: u32 = 0x01 << offset;
139 pub mod R {}
140 pub mod W {}
141 pub mod RW {
142 #[doc = "Disables the interrupt."]
143 pub const FRIE_0: u32 = 0;
144 #[doc = "Enables the interrupt."]
145 pub const FRIE_1: u32 = 0x01;
146 }
147 }
148 #[doc = "FIFO Warning Interrupt Enable"]
149 pub mod FWIE {
150 pub const offset: u32 = 9;
151 pub const mask: u32 = 0x01 << offset;
152 pub mod R {}
153 pub mod W {}
154 pub mod RW {
155 #[doc = "Disables the interrupt."]
156 pub const FWIE_0: u32 = 0;
157 #[doc = "Enables the interrupt."]
158 pub const FWIE_1: u32 = 0x01;
159 }
160 }
161 #[doc = "FIFO Error Interrupt Enable"]
162 pub mod FEIE {
163 pub const offset: u32 = 10;
164 pub const mask: u32 = 0x01 << offset;
165 pub mod R {}
166 pub mod W {}
167 pub mod RW {
168 #[doc = "Disables the interrupt."]
169 pub const FEIE_0: u32 = 0;
170 #[doc = "Enables the interrupt."]
171 pub const FEIE_1: u32 = 0x01;
172 }
173 }
174 #[doc = "Sync Error Interrupt Enable"]
175 pub mod SEIE {
176 pub const offset: u32 = 11;
177 pub const mask: u32 = 0x01 << offset;
178 pub mod R {}
179 pub mod W {}
180 pub mod RW {
181 #[doc = "Disables interrupt."]
182 pub const SEIE_0: u32 = 0;
183 #[doc = "Enables interrupt."]
184 pub const SEIE_1: u32 = 0x01;
185 }
186 }
187 #[doc = "Word Start Interrupt Enable"]
188 pub mod WSIE {
189 pub const offset: u32 = 12;
190 pub const mask: u32 = 0x01 << offset;
191 pub mod R {}
192 pub mod W {}
193 pub mod RW {
194 #[doc = "Disables interrupt."]
195 pub const WSIE_0: u32 = 0;
196 #[doc = "Enables interrupt."]
197 pub const WSIE_1: u32 = 0x01;
198 }
199 }
200 #[doc = "FIFO Request Flag"]
201 pub mod FRF {
202 pub const offset: u32 = 16;
203 pub const mask: u32 = 0x01 << offset;
204 pub mod R {}
205 pub mod W {}
206 pub mod RW {
207 #[doc = "Transmit FIFO watermark has not been reached."]
208 pub const FRF_0: u32 = 0;
209 #[doc = "Transmit FIFO watermark has been reached."]
210 pub const FRF_1: u32 = 0x01;
211 }
212 }
213 #[doc = "FIFO Warning Flag"]
214 pub mod FWF {
215 pub const offset: u32 = 17;
216 pub const mask: u32 = 0x01 << offset;
217 pub mod R {}
218 pub mod W {}
219 pub mod RW {
220 #[doc = "No enabled transmit FIFO is empty."]
221 pub const FWF_0: u32 = 0;
222 #[doc = "Enabled transmit FIFO is empty."]
223 pub const FWF_1: u32 = 0x01;
224 }
225 }
226 #[doc = "FIFO Error Flag"]
227 pub mod FEF {
228 pub const offset: u32 = 18;
229 pub const mask: u32 = 0x01 << offset;
230 pub mod R {}
231 pub mod W {}
232 pub mod RW {
233 #[doc = "Transmit underrun not detected."]
234 pub const FEF_0: u32 = 0;
235 #[doc = "Transmit underrun detected."]
236 pub const FEF_1: u32 = 0x01;
237 }
238 }
239 #[doc = "Sync Error Flag"]
240 pub mod SEF {
241 pub const offset: u32 = 19;
242 pub const mask: u32 = 0x01 << offset;
243 pub mod R {}
244 pub mod W {}
245 pub mod RW {
246 #[doc = "Sync error not detected."]
247 pub const SEF_0: u32 = 0;
248 #[doc = "Frame sync error detected."]
249 pub const SEF_1: u32 = 0x01;
250 }
251 }
252 #[doc = "Word Start Flag"]
253 pub mod WSF {
254 pub const offset: u32 = 20;
255 pub const mask: u32 = 0x01 << offset;
256 pub mod R {}
257 pub mod W {}
258 pub mod RW {
259 #[doc = "Start of word not detected."]
260 pub const WSF_0: u32 = 0;
261 #[doc = "Start of word detected."]
262 pub const WSF_1: u32 = 0x01;
263 }
264 }
265 #[doc = "Software Reset"]
266 pub mod SR {
267 pub const offset: u32 = 24;
268 pub const mask: u32 = 0x01 << offset;
269 pub mod R {}
270 pub mod W {}
271 pub mod RW {
272 #[doc = "No effect."]
273 pub const SR_0: u32 = 0;
274 #[doc = "Software reset."]
275 pub const SR_1: u32 = 0x01;
276 }
277 }
278 #[doc = "FIFO Reset"]
279 pub mod FR {
280 pub const offset: u32 = 25;
281 pub const mask: u32 = 0x01 << offset;
282 pub mod R {}
283 pub mod W {}
284 pub mod RW {
285 #[doc = "No effect."]
286 pub const FR_0: u32 = 0;
287 #[doc = "FIFO reset."]
288 pub const FR_1: u32 = 0x01;
289 }
290 }
291 #[doc = "Bit Clock Enable"]
292 pub mod BCE {
293 pub const offset: u32 = 28;
294 pub const mask: u32 = 0x01 << offset;
295 pub mod R {}
296 pub mod W {}
297 pub mod RW {
298 #[doc = "Transmit bit clock is disabled."]
299 pub const BCE_0: u32 = 0;
300 #[doc = "Transmit bit clock is enabled."]
301 pub const BCE_1: u32 = 0x01;
302 }
303 }
304 #[doc = "Debug Enable"]
305 pub mod DBGE {
306 pub const offset: u32 = 29;
307 pub const mask: u32 = 0x01 << offset;
308 pub mod R {}
309 pub mod W {}
310 pub mod RW {
311 #[doc = "Transmitter is disabled in Debug mode, after completing the current frame."]
312 pub const DBGE_0: u32 = 0;
313 #[doc = "Transmitter is enabled in Debug mode."]
314 pub const DBGE_1: u32 = 0x01;
315 }
316 }
317 #[doc = "Stop Enable"]
318 pub mod STOPE {
319 pub const offset: u32 = 30;
320 pub const mask: u32 = 0x01 << offset;
321 pub mod R {}
322 pub mod W {}
323 pub mod RW {
324 #[doc = "Transmitter disabled in Stop mode."]
325 pub const STOPE_0: u32 = 0;
326 #[doc = "Transmitter enabled in Stop mode."]
327 pub const STOPE_1: u32 = 0x01;
328 }
329 }
330 #[doc = "Transmitter Enable"]
331 pub mod TE {
332 pub const offset: u32 = 31;
333 pub const mask: u32 = 0x01 << offset;
334 pub mod R {}
335 pub mod W {}
336 pub mod RW {
337 #[doc = "Transmitter is disabled."]
338 pub const TE_0: u32 = 0;
339 #[doc = "Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame."]
340 pub const TE_1: u32 = 0x01;
341 }
342 }
343}
344#[doc = "SAI Transmit Configuration 1 Register"]
345pub mod TCR1 {
346 #[doc = "Transmit FIFO Watermark"]
347 pub mod TFW {
348 pub const offset: u32 = 0;
349 pub const mask: u32 = 0x1f << offset;
350 pub mod R {}
351 pub mod W {}
352 pub mod RW {}
353 }
354}
355#[doc = "SAI Transmit Configuration 2 Register"]
356pub mod TCR2 {
357 #[doc = "Bit Clock Divide"]
358 pub mod DIV {
359 pub const offset: u32 = 0;
360 pub const mask: u32 = 0xff << offset;
361 pub mod R {}
362 pub mod W {}
363 pub mod RW {}
364 }
365 #[doc = "Bit Clock Direction"]
366 pub mod BCD {
367 pub const offset: u32 = 24;
368 pub const mask: u32 = 0x01 << offset;
369 pub mod R {}
370 pub mod W {}
371 pub mod RW {
372 #[doc = "Bit clock is generated externally in Slave mode."]
373 pub const BCD_0: u32 = 0;
374 #[doc = "Bit clock is generated internally in Master mode."]
375 pub const BCD_1: u32 = 0x01;
376 }
377 }
378 #[doc = "Bit Clock Polarity"]
379 pub mod BCP {
380 pub const offset: u32 = 25;
381 pub const mask: u32 = 0x01 << offset;
382 pub mod R {}
383 pub mod W {}
384 pub mod RW {
385 #[doc = "Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge."]
386 pub const BCP_0: u32 = 0;
387 #[doc = "Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge."]
388 pub const BCP_1: u32 = 0x01;
389 }
390 }
391 #[doc = "MCLK Select"]
392 pub mod MSEL {
393 pub const offset: u32 = 26;
394 pub const mask: u32 = 0x03 << offset;
395 pub mod R {}
396 pub mod W {}
397 pub mod RW {
398 #[doc = "Bus Clock selected."]
399 pub const MSEL_0: u32 = 0;
400 #[doc = "Master Clock (MCLK) 1 option selected."]
401 pub const MSEL_1: u32 = 0x01;
402 #[doc = "Master Clock (MCLK) 2 option selected."]
403 pub const MSEL_2: u32 = 0x02;
404 #[doc = "Master Clock (MCLK) 3 option selected."]
405 pub const MSEL_3: u32 = 0x03;
406 }
407 }
408 #[doc = "Bit Clock Input"]
409 pub mod BCI {
410 pub const offset: u32 = 28;
411 pub const mask: u32 = 0x01 << offset;
412 pub mod R {}
413 pub mod W {}
414 pub mod RW {
415 #[doc = "No effect."]
416 pub const BCI_0: u32 = 0;
417 #[doc = "Internal logic is clocked as if bit clock was externally generated."]
418 pub const BCI_1: u32 = 0x01;
419 }
420 }
421 #[doc = "Bit Clock Swap"]
422 pub mod BCS {
423 pub const offset: u32 = 29;
424 pub const mask: u32 = 0x01 << offset;
425 pub mod R {}
426 pub mod W {}
427 pub mod RW {
428 #[doc = "Use the normal bit clock source."]
429 pub const BCS_0: u32 = 0;
430 #[doc = "Swap the bit clock source."]
431 pub const BCS_1: u32 = 0x01;
432 }
433 }
434 #[doc = "Synchronous Mode"]
435 pub mod SYNC {
436 pub const offset: u32 = 30;
437 pub const mask: u32 = 0x03 << offset;
438 pub mod R {}
439 pub mod W {}
440 pub mod RW {
441 #[doc = "Asynchronous mode."]
442 pub const SYNC_0: u32 = 0;
443 #[doc = "Synchronous with receiver."]
444 pub const SYNC_1: u32 = 0x01;
445 }
446 }
447}
448#[doc = "SAI Transmit Configuration 3 Register"]
449pub mod TCR3 {
450 #[doc = "Word Flag Configuration"]
451 pub mod WDFL {
452 pub const offset: u32 = 0;
453 pub const mask: u32 = 0x1f << offset;
454 pub mod R {}
455 pub mod W {}
456 pub mod RW {}
457 }
458 #[doc = "Transmit Channel Enable"]
459 pub mod TCE {
460 pub const offset: u32 = 16;
461 pub const mask: u32 = 0x03 << offset;
462 pub mod R {}
463 pub mod W {}
464 pub mod RW {}
465 }
466 #[doc = "Channel FIFO Reset"]
467 pub mod CFR {
468 pub const offset: u32 = 24;
469 pub const mask: u32 = 0x03 << offset;
470 pub mod R {}
471 pub mod W {}
472 pub mod RW {}
473 }
474}
475#[doc = "SAI Transmit Configuration 4 Register"]
476pub mod TCR4 {
477 #[doc = "Frame Sync Direction"]
478 pub mod FSD {
479 pub const offset: u32 = 0;
480 pub const mask: u32 = 0x01 << offset;
481 pub mod R {}
482 pub mod W {}
483 pub mod RW {
484 #[doc = "Frame sync is generated externally in Slave mode."]
485 pub const FSD_0: u32 = 0;
486 #[doc = "Frame sync is generated internally in Master mode."]
487 pub const FSD_1: u32 = 0x01;
488 }
489 }
490 #[doc = "Frame Sync Polarity"]
491 pub mod FSP {
492 pub const offset: u32 = 1;
493 pub const mask: u32 = 0x01 << offset;
494 pub mod R {}
495 pub mod W {}
496 pub mod RW {
497 #[doc = "Frame sync is active high."]
498 pub const FSP_0: u32 = 0;
499 #[doc = "Frame sync is active low."]
500 pub const FSP_1: u32 = 0x01;
501 }
502 }
503 #[doc = "On Demand Mode"]
504 pub mod ONDEM {
505 pub const offset: u32 = 2;
506 pub const mask: u32 = 0x01 << offset;
507 pub mod R {}
508 pub mod W {}
509 pub mod RW {
510 #[doc = "Internal frame sync is generated continuously."]
511 pub const ONDEM_0: u32 = 0;
512 #[doc = "Internal frame sync is generated when the FIFO warning flag is clear."]
513 pub const ONDEM_1: u32 = 0x01;
514 }
515 }
516 #[doc = "Frame Sync Early"]
517 pub mod FSE {
518 pub const offset: u32 = 3;
519 pub const mask: u32 = 0x01 << offset;
520 pub mod R {}
521 pub mod W {}
522 pub mod RW {
523 #[doc = "Frame sync asserts with the first bit of the frame."]
524 pub const FSE_0: u32 = 0;
525 #[doc = "Frame sync asserts one bit before the first bit of the frame."]
526 pub const FSE_1: u32 = 0x01;
527 }
528 }
529 #[doc = "MSB First"]
530 pub mod MF {
531 pub const offset: u32 = 4;
532 pub const mask: u32 = 0x01 << offset;
533 pub mod R {}
534 pub mod W {}
535 pub mod RW {
536 #[doc = "LSB is transmitted first."]
537 pub const MF_0: u32 = 0;
538 #[doc = "MSB is transmitted first."]
539 pub const MF_1: u32 = 0x01;
540 }
541 }
542 #[doc = "Channel Mode"]
543 pub mod CHMOD {
544 pub const offset: u32 = 5;
545 pub const mask: u32 = 0x01 << offset;
546 pub mod R {}
547 pub mod W {}
548 pub mod RW {
549 #[doc = "TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled."]
550 pub const CHMOD_0: u32 = 0;
551 #[doc = "Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled."]
552 pub const CHMOD_1: u32 = 0x01;
553 }
554 }
555 #[doc = "Sync Width"]
556 pub mod SYWD {
557 pub const offset: u32 = 8;
558 pub const mask: u32 = 0x1f << offset;
559 pub mod R {}
560 pub mod W {}
561 pub mod RW {}
562 }
563 #[doc = "Frame size"]
564 pub mod FRSZ {
565 pub const offset: u32 = 16;
566 pub const mask: u32 = 0x1f << offset;
567 pub mod R {}
568 pub mod W {}
569 pub mod RW {}
570 }
571 #[doc = "FIFO Packing Mode"]
572 pub mod FPACK {
573 pub const offset: u32 = 24;
574 pub const mask: u32 = 0x03 << offset;
575 pub mod R {}
576 pub mod W {}
577 pub mod RW {
578 #[doc = "FIFO packing is disabled"]
579 pub const FPACK_0: u32 = 0;
580 #[doc = "8-bit FIFO packing is enabled"]
581 pub const FPACK_2: u32 = 0x02;
582 #[doc = "16-bit FIFO packing is enabled"]
583 pub const FPACK_3: u32 = 0x03;
584 }
585 }
586 #[doc = "FIFO Combine Mode"]
587 pub mod FCOMB {
588 pub const offset: u32 = 26;
589 pub const mask: u32 = 0x03 << offset;
590 pub mod R {}
591 pub mod W {}
592 pub mod RW {
593 #[doc = "FIFO combine mode disabled."]
594 pub const FCOMB_0: u32 = 0;
595 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."]
596 pub const FCOMB_1: u32 = 0x01;
597 #[doc = "FIFO combine mode enabled on FIFO writes (by software)."]
598 pub const FCOMB_2: u32 = 0x02;
599 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."]
600 pub const FCOMB_3: u32 = 0x03;
601 }
602 }
603 #[doc = "FIFO Continue on Error"]
604 pub mod FCONT {
605 pub const offset: u32 = 28;
606 pub const mask: u32 = 0x01 << offset;
607 pub mod R {}
608 pub mod W {}
609 pub mod RW {
610 #[doc = "On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared."]
611 pub const FCONT_0: u32 = 0;
612 #[doc = "On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared."]
613 pub const FCONT_1: u32 = 0x01;
614 }
615 }
616}
617#[doc = "SAI Transmit Configuration 5 Register"]
618pub mod TCR5 {
619 #[doc = "First Bit Shifted"]
620 pub mod FBT {
621 pub const offset: u32 = 8;
622 pub const mask: u32 = 0x1f << offset;
623 pub mod R {}
624 pub mod W {}
625 pub mod RW {}
626 }
627 #[doc = "Word 0 Width"]
628 pub mod W0W {
629 pub const offset: u32 = 16;
630 pub const mask: u32 = 0x1f << offset;
631 pub mod R {}
632 pub mod W {}
633 pub mod RW {}
634 }
635 #[doc = "Word N Width"]
636 pub mod WNW {
637 pub const offset: u32 = 24;
638 pub const mask: u32 = 0x1f << offset;
639 pub mod R {}
640 pub mod W {}
641 pub mod RW {}
642 }
643}
644#[doc = "SAI Transmit Data Register"]
645pub mod TDR {
646 #[doc = "Transmit Data Register"]
647 pub mod TDR {
648 pub const offset: u32 = 0;
649 pub const mask: u32 = 0xffff_ffff << offset;
650 pub mod R {}
651 pub mod W {}
652 pub mod RW {}
653 }
654}
655#[doc = "SAI Transmit FIFO Register"]
656pub mod TFR {
657 #[doc = "Read FIFO Pointer"]
658 pub mod RFP {
659 pub const offset: u32 = 0;
660 pub const mask: u32 = 0x3f << offset;
661 pub mod R {}
662 pub mod W {}
663 pub mod RW {}
664 }
665 #[doc = "Write FIFO Pointer"]
666 pub mod WFP {
667 pub const offset: u32 = 16;
668 pub const mask: u32 = 0x3f << offset;
669 pub mod R {}
670 pub mod W {}
671 pub mod RW {}
672 }
673 #[doc = "Write Channel Pointer"]
674 pub mod WCP {
675 pub const offset: u32 = 31;
676 pub const mask: u32 = 0x01 << offset;
677 pub mod R {}
678 pub mod W {}
679 pub mod RW {
680 #[doc = "No effect."]
681 pub const WCP_0: u32 = 0;
682 #[doc = "FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write."]
683 pub const WCP_1: u32 = 0x01;
684 }
685 }
686}
687#[doc = "SAI Transmit Mask Register"]
688pub mod TMR {
689 #[doc = "Transmit Word Mask"]
690 pub mod TWM {
691 pub const offset: u32 = 0;
692 pub const mask: u32 = 0xffff_ffff << offset;
693 pub mod R {}
694 pub mod W {}
695 pub mod RW {
696 #[doc = "Word N is enabled."]
697 pub const TWM_0: u32 = 0;
698 #[doc = "Word N is masked. The transmit data pins are tri-stated or drive zero when masked."]
699 pub const TWM_1: u32 = 0x01;
700 }
701 }
702}
703#[doc = "SAI Receive Control Register"]
704pub mod RCSR {
705 #[doc = "FIFO Request DMA Enable"]
706 pub mod FRDE {
707 pub const offset: u32 = 0;
708 pub const mask: u32 = 0x01 << offset;
709 pub mod R {}
710 pub mod W {}
711 pub mod RW {
712 #[doc = "Disables the DMA request."]
713 pub const FRDE_0: u32 = 0;
714 #[doc = "Enables the DMA request."]
715 pub const FRDE_1: u32 = 0x01;
716 }
717 }
718 #[doc = "FIFO Warning DMA Enable"]
719 pub mod FWDE {
720 pub const offset: u32 = 1;
721 pub const mask: u32 = 0x01 << offset;
722 pub mod R {}
723 pub mod W {}
724 pub mod RW {
725 #[doc = "Disables the DMA request."]
726 pub const FWDE_0: u32 = 0;
727 #[doc = "Enables the DMA request."]
728 pub const FWDE_1: u32 = 0x01;
729 }
730 }
731 #[doc = "FIFO Request Interrupt Enable"]
732 pub mod FRIE {
733 pub const offset: u32 = 8;
734 pub const mask: u32 = 0x01 << offset;
735 pub mod R {}
736 pub mod W {}
737 pub mod RW {
738 #[doc = "Disables the interrupt."]
739 pub const FRIE_0: u32 = 0;
740 #[doc = "Enables the interrupt."]
741 pub const FRIE_1: u32 = 0x01;
742 }
743 }
744 #[doc = "FIFO Warning Interrupt Enable"]
745 pub mod FWIE {
746 pub const offset: u32 = 9;
747 pub const mask: u32 = 0x01 << offset;
748 pub mod R {}
749 pub mod W {}
750 pub mod RW {
751 #[doc = "Disables the interrupt."]
752 pub const FWIE_0: u32 = 0;
753 #[doc = "Enables the interrupt."]
754 pub const FWIE_1: u32 = 0x01;
755 }
756 }
757 #[doc = "FIFO Error Interrupt Enable"]
758 pub mod FEIE {
759 pub const offset: u32 = 10;
760 pub const mask: u32 = 0x01 << offset;
761 pub mod R {}
762 pub mod W {}
763 pub mod RW {
764 #[doc = "Disables the interrupt."]
765 pub const FEIE_0: u32 = 0;
766 #[doc = "Enables the interrupt."]
767 pub const FEIE_1: u32 = 0x01;
768 }
769 }
770 #[doc = "Sync Error Interrupt Enable"]
771 pub mod SEIE {
772 pub const offset: u32 = 11;
773 pub const mask: u32 = 0x01 << offset;
774 pub mod R {}
775 pub mod W {}
776 pub mod RW {
777 #[doc = "Disables interrupt."]
778 pub const SEIE_0: u32 = 0;
779 #[doc = "Enables interrupt."]
780 pub const SEIE_1: u32 = 0x01;
781 }
782 }
783 #[doc = "Word Start Interrupt Enable"]
784 pub mod WSIE {
785 pub const offset: u32 = 12;
786 pub const mask: u32 = 0x01 << offset;
787 pub mod R {}
788 pub mod W {}
789 pub mod RW {
790 #[doc = "Disables interrupt."]
791 pub const WSIE_0: u32 = 0;
792 #[doc = "Enables interrupt."]
793 pub const WSIE_1: u32 = 0x01;
794 }
795 }
796 #[doc = "FIFO Request Flag"]
797 pub mod FRF {
798 pub const offset: u32 = 16;
799 pub const mask: u32 = 0x01 << offset;
800 pub mod R {}
801 pub mod W {}
802 pub mod RW {
803 #[doc = "Receive FIFO watermark not reached."]
804 pub const FRF_0: u32 = 0;
805 #[doc = "Receive FIFO watermark has been reached."]
806 pub const FRF_1: u32 = 0x01;
807 }
808 }
809 #[doc = "FIFO Warning Flag"]
810 pub mod FWF {
811 pub const offset: u32 = 17;
812 pub const mask: u32 = 0x01 << offset;
813 pub mod R {}
814 pub mod W {}
815 pub mod RW {
816 #[doc = "No enabled receive FIFO is full."]
817 pub const FWF_0: u32 = 0;
818 #[doc = "Enabled receive FIFO is full."]
819 pub const FWF_1: u32 = 0x01;
820 }
821 }
822 #[doc = "FIFO Error Flag"]
823 pub mod FEF {
824 pub const offset: u32 = 18;
825 pub const mask: u32 = 0x01 << offset;
826 pub mod R {}
827 pub mod W {}
828 pub mod RW {
829 #[doc = "Receive overflow not detected."]
830 pub const FEF_0: u32 = 0;
831 #[doc = "Receive overflow detected."]
832 pub const FEF_1: u32 = 0x01;
833 }
834 }
835 #[doc = "Sync Error Flag"]
836 pub mod SEF {
837 pub const offset: u32 = 19;
838 pub const mask: u32 = 0x01 << offset;
839 pub mod R {}
840 pub mod W {}
841 pub mod RW {
842 #[doc = "Sync error not detected."]
843 pub const SEF_0: u32 = 0;
844 #[doc = "Frame sync error detected."]
845 pub const SEF_1: u32 = 0x01;
846 }
847 }
848 #[doc = "Word Start Flag"]
849 pub mod WSF {
850 pub const offset: u32 = 20;
851 pub const mask: u32 = 0x01 << offset;
852 pub mod R {}
853 pub mod W {}
854 pub mod RW {
855 #[doc = "Start of word not detected."]
856 pub const WSF_0: u32 = 0;
857 #[doc = "Start of word detected."]
858 pub const WSF_1: u32 = 0x01;
859 }
860 }
861 #[doc = "Software Reset"]
862 pub mod SR {
863 pub const offset: u32 = 24;
864 pub const mask: u32 = 0x01 << offset;
865 pub mod R {}
866 pub mod W {}
867 pub mod RW {
868 #[doc = "No effect."]
869 pub const SR_0: u32 = 0;
870 #[doc = "Software reset."]
871 pub const SR_1: u32 = 0x01;
872 }
873 }
874 #[doc = "FIFO Reset"]
875 pub mod FR {
876 pub const offset: u32 = 25;
877 pub const mask: u32 = 0x01 << offset;
878 pub mod R {}
879 pub mod W {}
880 pub mod RW {
881 #[doc = "No effect."]
882 pub const FR_0: u32 = 0;
883 #[doc = "FIFO reset."]
884 pub const FR_1: u32 = 0x01;
885 }
886 }
887 #[doc = "Bit Clock Enable"]
888 pub mod BCE {
889 pub const offset: u32 = 28;
890 pub const mask: u32 = 0x01 << offset;
891 pub mod R {}
892 pub mod W {}
893 pub mod RW {
894 #[doc = "Receive bit clock is disabled."]
895 pub const BCE_0: u32 = 0;
896 #[doc = "Receive bit clock is enabled."]
897 pub const BCE_1: u32 = 0x01;
898 }
899 }
900 #[doc = "Debug Enable"]
901 pub mod DBGE {
902 pub const offset: u32 = 29;
903 pub const mask: u32 = 0x01 << offset;
904 pub mod R {}
905 pub mod W {}
906 pub mod RW {
907 #[doc = "Receiver is disabled in Debug mode, after completing the current frame."]
908 pub const DBGE_0: u32 = 0;
909 #[doc = "Receiver is enabled in Debug mode."]
910 pub const DBGE_1: u32 = 0x01;
911 }
912 }
913 #[doc = "Stop Enable"]
914 pub mod STOPE {
915 pub const offset: u32 = 30;
916 pub const mask: u32 = 0x01 << offset;
917 pub mod R {}
918 pub mod W {}
919 pub mod RW {
920 #[doc = "Receiver disabled in Stop mode."]
921 pub const STOPE_0: u32 = 0;
922 #[doc = "Receiver enabled in Stop mode."]
923 pub const STOPE_1: u32 = 0x01;
924 }
925 }
926 #[doc = "Receiver Enable"]
927 pub mod RE {
928 pub const offset: u32 = 31;
929 pub const mask: u32 = 0x01 << offset;
930 pub mod R {}
931 pub mod W {}
932 pub mod RW {
933 #[doc = "Receiver is disabled."]
934 pub const RE_0: u32 = 0;
935 #[doc = "Receiver is enabled, or receiver has been disabled and has not yet reached end of frame."]
936 pub const RE_1: u32 = 0x01;
937 }
938 }
939}
940#[doc = "SAI Receive Configuration 1 Register"]
941pub mod RCR1 {
942 #[doc = "Receive FIFO Watermark"]
943 pub mod RFW {
944 pub const offset: u32 = 0;
945 pub const mask: u32 = 0x1f << offset;
946 pub mod R {}
947 pub mod W {}
948 pub mod RW {}
949 }
950}
951#[doc = "SAI Receive Configuration 2 Register"]
952pub mod RCR2 {
953 #[doc = "Bit Clock Divide"]
954 pub mod DIV {
955 pub const offset: u32 = 0;
956 pub const mask: u32 = 0xff << offset;
957 pub mod R {}
958 pub mod W {}
959 pub mod RW {}
960 }
961 #[doc = "Bit Clock Direction"]
962 pub mod BCD {
963 pub const offset: u32 = 24;
964 pub const mask: u32 = 0x01 << offset;
965 pub mod R {}
966 pub mod W {}
967 pub mod RW {
968 #[doc = "Bit clock is generated externally in Slave mode."]
969 pub const BCD_0: u32 = 0;
970 #[doc = "Bit clock is generated internally in Master mode."]
971 pub const BCD_1: u32 = 0x01;
972 }
973 }
974 #[doc = "Bit Clock Polarity"]
975 pub mod BCP {
976 pub const offset: u32 = 25;
977 pub const mask: u32 = 0x01 << offset;
978 pub mod R {}
979 pub mod W {}
980 pub mod RW {
981 #[doc = "Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge."]
982 pub const BCP_0: u32 = 0;
983 #[doc = "Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge."]
984 pub const BCP_1: u32 = 0x01;
985 }
986 }
987 #[doc = "MCLK Select"]
988 pub mod MSEL {
989 pub const offset: u32 = 26;
990 pub const mask: u32 = 0x03 << offset;
991 pub mod R {}
992 pub mod W {}
993 pub mod RW {
994 #[doc = "Bus Clock selected."]
995 pub const MSEL_0: u32 = 0;
996 #[doc = "Master Clock (MCLK) 1 option selected."]
997 pub const MSEL_1: u32 = 0x01;
998 #[doc = "Master Clock (MCLK) 2 option selected."]
999 pub const MSEL_2: u32 = 0x02;
1000 #[doc = "Master Clock (MCLK) 3 option selected."]
1001 pub const MSEL_3: u32 = 0x03;
1002 }
1003 }
1004 #[doc = "Bit Clock Input"]
1005 pub mod BCI {
1006 pub const offset: u32 = 28;
1007 pub const mask: u32 = 0x01 << offset;
1008 pub mod R {}
1009 pub mod W {}
1010 pub mod RW {
1011 #[doc = "No effect."]
1012 pub const BCI_0: u32 = 0;
1013 #[doc = "Internal logic is clocked as if bit clock was externally generated."]
1014 pub const BCI_1: u32 = 0x01;
1015 }
1016 }
1017 #[doc = "Bit Clock Swap"]
1018 pub mod BCS {
1019 pub const offset: u32 = 29;
1020 pub const mask: u32 = 0x01 << offset;
1021 pub mod R {}
1022 pub mod W {}
1023 pub mod RW {
1024 #[doc = "Use the normal bit clock source."]
1025 pub const BCS_0: u32 = 0;
1026 #[doc = "Swap the bit clock source."]
1027 pub const BCS_1: u32 = 0x01;
1028 }
1029 }
1030 #[doc = "Synchronous Mode"]
1031 pub mod SYNC {
1032 pub const offset: u32 = 30;
1033 pub const mask: u32 = 0x03 << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {
1037 #[doc = "Asynchronous mode."]
1038 pub const SYNC_0: u32 = 0;
1039 #[doc = "Synchronous with transmitter."]
1040 pub const SYNC_1: u32 = 0x01;
1041 }
1042 }
1043}
1044#[doc = "SAI Receive Configuration 3 Register"]
1045pub mod RCR3 {
1046 #[doc = "Word Flag Configuration"]
1047 pub mod WDFL {
1048 pub const offset: u32 = 0;
1049 pub const mask: u32 = 0x1f << offset;
1050 pub mod R {}
1051 pub mod W {}
1052 pub mod RW {}
1053 }
1054 #[doc = "Receive Channel Enable"]
1055 pub mod RCE {
1056 pub const offset: u32 = 16;
1057 pub const mask: u32 = 0x03 << offset;
1058 pub mod R {}
1059 pub mod W {}
1060 pub mod RW {}
1061 }
1062 #[doc = "Channel FIFO Reset"]
1063 pub mod CFR {
1064 pub const offset: u32 = 24;
1065 pub const mask: u32 = 0x03 << offset;
1066 pub mod R {}
1067 pub mod W {}
1068 pub mod RW {}
1069 }
1070}
1071#[doc = "SAI Receive Configuration 4 Register"]
1072pub mod RCR4 {
1073 #[doc = "Frame Sync Direction"]
1074 pub mod FSD {
1075 pub const offset: u32 = 0;
1076 pub const mask: u32 = 0x01 << offset;
1077 pub mod R {}
1078 pub mod W {}
1079 pub mod RW {
1080 #[doc = "Frame Sync is generated externally in Slave mode."]
1081 pub const FSD_0: u32 = 0;
1082 #[doc = "Frame Sync is generated internally in Master mode."]
1083 pub const FSD_1: u32 = 0x01;
1084 }
1085 }
1086 #[doc = "Frame Sync Polarity"]
1087 pub mod FSP {
1088 pub const offset: u32 = 1;
1089 pub const mask: u32 = 0x01 << offset;
1090 pub mod R {}
1091 pub mod W {}
1092 pub mod RW {
1093 #[doc = "Frame sync is active high."]
1094 pub const FSP_0: u32 = 0;
1095 #[doc = "Frame sync is active low."]
1096 pub const FSP_1: u32 = 0x01;
1097 }
1098 }
1099 #[doc = "On Demand Mode"]
1100 pub mod ONDEM {
1101 pub const offset: u32 = 2;
1102 pub const mask: u32 = 0x01 << offset;
1103 pub mod R {}
1104 pub mod W {}
1105 pub mod RW {
1106 #[doc = "Internal frame sync is generated continuously."]
1107 pub const ONDEM_0: u32 = 0;
1108 #[doc = "Internal frame sync is generated when the FIFO warning flag is clear."]
1109 pub const ONDEM_1: u32 = 0x01;
1110 }
1111 }
1112 #[doc = "Frame Sync Early"]
1113 pub mod FSE {
1114 pub const offset: u32 = 3;
1115 pub const mask: u32 = 0x01 << offset;
1116 pub mod R {}
1117 pub mod W {}
1118 pub mod RW {
1119 #[doc = "Frame sync asserts with the first bit of the frame."]
1120 pub const FSE_0: u32 = 0;
1121 #[doc = "Frame sync asserts one bit before the first bit of the frame."]
1122 pub const FSE_1: u32 = 0x01;
1123 }
1124 }
1125 #[doc = "MSB First"]
1126 pub mod MF {
1127 pub const offset: u32 = 4;
1128 pub const mask: u32 = 0x01 << offset;
1129 pub mod R {}
1130 pub mod W {}
1131 pub mod RW {
1132 #[doc = "LSB is received first."]
1133 pub const MF_0: u32 = 0;
1134 #[doc = "MSB is received first."]
1135 pub const MF_1: u32 = 0x01;
1136 }
1137 }
1138 #[doc = "Sync Width"]
1139 pub mod SYWD {
1140 pub const offset: u32 = 8;
1141 pub const mask: u32 = 0x1f << offset;
1142 pub mod R {}
1143 pub mod W {}
1144 pub mod RW {}
1145 }
1146 #[doc = "Frame Size"]
1147 pub mod FRSZ {
1148 pub const offset: u32 = 16;
1149 pub const mask: u32 = 0x1f << offset;
1150 pub mod R {}
1151 pub mod W {}
1152 pub mod RW {}
1153 }
1154 #[doc = "FIFO Packing Mode"]
1155 pub mod FPACK {
1156 pub const offset: u32 = 24;
1157 pub const mask: u32 = 0x03 << offset;
1158 pub mod R {}
1159 pub mod W {}
1160 pub mod RW {
1161 #[doc = "FIFO packing is disabled"]
1162 pub const FPACK_0: u32 = 0;
1163 #[doc = "8-bit FIFO packing is enabled"]
1164 pub const FPACK_2: u32 = 0x02;
1165 #[doc = "16-bit FIFO packing is enabled"]
1166 pub const FPACK_3: u32 = 0x03;
1167 }
1168 }
1169 #[doc = "FIFO Combine Mode"]
1170 pub mod FCOMB {
1171 pub const offset: u32 = 26;
1172 pub const mask: u32 = 0x03 << offset;
1173 pub mod R {}
1174 pub mod W {}
1175 pub mod RW {
1176 #[doc = "FIFO combine mode disabled."]
1177 pub const FCOMB_0: u32 = 0;
1178 #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers)."]
1179 pub const FCOMB_1: u32 = 0x01;
1180 #[doc = "FIFO combine mode enabled on FIFO reads (by software)."]
1181 pub const FCOMB_2: u32 = 0x02;
1182 #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software)."]
1183 pub const FCOMB_3: u32 = 0x03;
1184 }
1185 }
1186 #[doc = "FIFO Continue on Error"]
1187 pub mod FCONT {
1188 pub const offset: u32 = 28;
1189 pub const mask: u32 = 0x01 << offset;
1190 pub mod R {}
1191 pub mod W {}
1192 pub mod RW {
1193 #[doc = "On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared."]
1194 pub const FCONT_0: u32 = 0;
1195 #[doc = "On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared."]
1196 pub const FCONT_1: u32 = 0x01;
1197 }
1198 }
1199}
1200#[doc = "SAI Receive Configuration 5 Register"]
1201pub mod RCR5 {
1202 #[doc = "First Bit Shifted"]
1203 pub mod FBT {
1204 pub const offset: u32 = 8;
1205 pub const mask: u32 = 0x1f << offset;
1206 pub mod R {}
1207 pub mod W {}
1208 pub mod RW {}
1209 }
1210 #[doc = "Word 0 Width"]
1211 pub mod W0W {
1212 pub const offset: u32 = 16;
1213 pub const mask: u32 = 0x1f << offset;
1214 pub mod R {}
1215 pub mod W {}
1216 pub mod RW {}
1217 }
1218 #[doc = "Word N Width"]
1219 pub mod WNW {
1220 pub const offset: u32 = 24;
1221 pub const mask: u32 = 0x1f << offset;
1222 pub mod R {}
1223 pub mod W {}
1224 pub mod RW {}
1225 }
1226}
1227#[doc = "SAI Receive Data Register"]
1228pub mod RDR {
1229 #[doc = "Receive Data Register"]
1230 pub mod RDR {
1231 pub const offset: u32 = 0;
1232 pub const mask: u32 = 0xffff_ffff << offset;
1233 pub mod R {}
1234 pub mod W {}
1235 pub mod RW {}
1236 }
1237}
1238#[doc = "SAI Receive FIFO Register"]
1239pub mod RFR {
1240 #[doc = "Read FIFO Pointer"]
1241 pub mod RFP {
1242 pub const offset: u32 = 0;
1243 pub const mask: u32 = 0x3f << offset;
1244 pub mod R {}
1245 pub mod W {}
1246 pub mod RW {}
1247 }
1248 #[doc = "Receive Channel Pointer"]
1249 pub mod RCP {
1250 pub const offset: u32 = 15;
1251 pub const mask: u32 = 0x01 << offset;
1252 pub mod R {}
1253 pub mod W {}
1254 pub mod RW {
1255 #[doc = "No effect."]
1256 pub const RCP_0: u32 = 0;
1257 #[doc = "FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read."]
1258 pub const RCP_1: u32 = 0x01;
1259 }
1260 }
1261 #[doc = "Write FIFO Pointer"]
1262 pub mod WFP {
1263 pub const offset: u32 = 16;
1264 pub const mask: u32 = 0x3f << offset;
1265 pub mod R {}
1266 pub mod W {}
1267 pub mod RW {}
1268 }
1269}
1270#[doc = "SAI Receive Mask Register"]
1271pub mod RMR {
1272 #[doc = "Receive Word Mask"]
1273 pub mod RWM {
1274 pub const offset: u32 = 0;
1275 pub const mask: u32 = 0xffff_ffff << offset;
1276 pub mod R {}
1277 pub mod W {}
1278 pub mod RW {
1279 #[doc = "Word N is enabled."]
1280 pub const RWM_0: u32 = 0;
1281 #[doc = "Word N is masked."]
1282 pub const RWM_1: u32 = 0x01;
1283 }
1284 }
1285}