rp2040_pac/i2c0/
ic_fs_scl_lcnt.rs

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1#[doc = "Register `IC_FS_SCL_LCNT` reader"]
2pub type R = crate::R<IC_FS_SCL_LCNT_SPEC>;
3#[doc = "Register `IC_FS_SCL_LCNT` writer"]
4pub type W = crate::W<IC_FS_SCL_LCNT_SPEC>;
5#[doc = "Field `IC_FS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.  
6
7 This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.  
8
9 This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
10register being set to 0. Writes at other times have no effect.  
11
12 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."]
13pub type IC_FS_SCL_LCNT_R = crate::FieldReader<u16>;
14#[doc = "Field `IC_FS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.  
15
16 This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.  
17
18 This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
19register being set to 0. Writes at other times have no effect.  
20
21 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."]
22pub type IC_FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
23impl R {
24    #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.  
25
26 This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.  
27
28 This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
29register being set to 0. Writes at other times have no effect.  
30
31 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."]
32    #[inline(always)]
33    pub fn ic_fs_scl_lcnt(&self) -> IC_FS_SCL_LCNT_R {
34        IC_FS_SCL_LCNT_R::new((self.bits & 0xffff) as u16)
35    }
36}
37impl W {
38    #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.  
39
40 This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.  
41
42 This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
43register being set to 0. Writes at other times have no effect.  
44
45 The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."]
46    #[inline(always)]
47    #[must_use]
48    pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W<IC_FS_SCL_LCNT_SPEC> {
49        IC_FS_SCL_LCNT_W::new(self, 0)
50    }
51    #[doc = r" Writes raw bits to the register."]
52    #[doc = r""]
53    #[doc = r" # Safety"]
54    #[doc = r""]
55    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
58        self.bits = bits;
59        self
60    }
61}
62#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register  
63
64You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_lcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct IC_FS_SCL_LCNT_SPEC;
66impl crate::RegisterSpec for IC_FS_SCL_LCNT_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`ic_fs_scl_lcnt::R`](R) reader structure"]
70impl crate::Readable for IC_FS_SCL_LCNT_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`ic_fs_scl_lcnt::W`](W) writer structure"]
72impl crate::Writable for IC_FS_SCL_LCNT_SPEC {
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75}
76#[doc = "`reset()` method sets IC_FS_SCL_LCNT to value 0x0d"]
77impl crate::Resettable for IC_FS_SCL_LCNT_SPEC {
78    const RESET_VALUE: u32 = 0x0d;
79}
rp2040_pac/i2c0/ic_fs_scl_lcnt.rs

rp2040_pac/i2c0/
ic_fs_scl_lcnt.rs
