imxrt_ral/blocks/imxrt1011/
lpuart.rs
1#[doc = "LPUART"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Version ID Register"]
5 pub VERID: crate::RORegister<u32>,
6 #[doc = "Parameter Register"]
7 pub PARAM: crate::RORegister<u32>,
8 #[doc = "LPUART Global Register"]
9 pub GLOBAL: crate::RWRegister<u32>,
10 #[doc = "LPUART Pin Configuration Register"]
11 pub PINCFG: crate::RWRegister<u32>,
12 #[doc = "LPUART Baud Rate Register"]
13 pub BAUD: crate::RWRegister<u32>,
14 #[doc = "LPUART Status Register"]
15 pub STAT: crate::RWRegister<u32>,
16 #[doc = "LPUART Control Register"]
17 pub CTRL: crate::RWRegister<u32>,
18 #[doc = "LPUART Data Register"]
19 pub DATA: crate::RWRegister<u32>,
20 #[doc = "LPUART Match Address Register"]
21 pub MATCH: crate::RWRegister<u32>,
22 #[doc = "LPUART Modem IrDA Register"]
23 pub MODIR: crate::RWRegister<u32>,
24 #[doc = "LPUART FIFO Register"]
25 pub FIFO: crate::RWRegister<u32>,
26 #[doc = "LPUART Watermark Register"]
27 pub WATER: crate::RWRegister<u32>,
28}
29#[doc = "Version ID Register"]
30pub mod VERID {
31 #[doc = "Feature Identification Number"]
32 pub mod FEATURE {
33 pub const offset: u32 = 0;
34 pub const mask: u32 = 0xffff << offset;
35 pub mod R {}
36 pub mod W {}
37 pub mod RW {
38 #[doc = "Standard feature set."]
39 pub const FEATURE_1: u32 = 0x01;
40 #[doc = "Standard feature set with MODEM/IrDA support."]
41 pub const FEATURE_3: u32 = 0x03;
42 }
43 }
44 #[doc = "Minor Version Number"]
45 pub mod MINOR {
46 pub const offset: u32 = 16;
47 pub const mask: u32 = 0xff << offset;
48 pub mod R {}
49 pub mod W {}
50 pub mod RW {}
51 }
52 #[doc = "Major Version Number"]
53 pub mod MAJOR {
54 pub const offset: u32 = 24;
55 pub const mask: u32 = 0xff << offset;
56 pub mod R {}
57 pub mod W {}
58 pub mod RW {}
59 }
60}
61#[doc = "Parameter Register"]
62pub mod PARAM {
63 #[doc = "Transmit FIFO Size"]
64 pub mod TXFIFO {
65 pub const offset: u32 = 0;
66 pub const mask: u32 = 0xff << offset;
67 pub mod R {}
68 pub mod W {}
69 pub mod RW {}
70 }
71 #[doc = "Receive FIFO Size"]
72 pub mod RXFIFO {
73 pub const offset: u32 = 8;
74 pub const mask: u32 = 0xff << offset;
75 pub mod R {}
76 pub mod W {}
77 pub mod RW {}
78 }
79}
80#[doc = "LPUART Global Register"]
81pub mod GLOBAL {
82 #[doc = "Software Reset"]
83 pub mod RST {
84 pub const offset: u32 = 1;
85 pub const mask: u32 = 0x01 << offset;
86 pub mod R {}
87 pub mod W {}
88 pub mod RW {
89 #[doc = "Module is not reset."]
90 pub const RST_0: u32 = 0;
91 #[doc = "Module is reset."]
92 pub const RST_1: u32 = 0x01;
93 }
94 }
95}
96#[doc = "LPUART Pin Configuration Register"]
97pub mod PINCFG {
98 #[doc = "Trigger Select"]
99 pub mod TRGSEL {
100 pub const offset: u32 = 0;
101 pub const mask: u32 = 0x03 << offset;
102 pub mod R {}
103 pub mod W {}
104 pub mod RW {
105 #[doc = "Input trigger is disabled."]
106 pub const TRGSEL_0: u32 = 0;
107 #[doc = "Input trigger is used instead of RXD pin input."]
108 pub const TRGSEL_1: u32 = 0x01;
109 #[doc = "Input trigger is used instead of CTS_B pin input."]
110 pub const TRGSEL_2: u32 = 0x02;
111 #[doc = "Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger."]
112 pub const TRGSEL_3: u32 = 0x03;
113 }
114 }
115}
116#[doc = "LPUART Baud Rate Register"]
117pub mod BAUD {
118 #[doc = "Baud Rate Modulo Divisor."]
119 pub mod SBR {
120 pub const offset: u32 = 0;
121 pub const mask: u32 = 0x1fff << offset;
122 pub mod R {}
123 pub mod W {}
124 pub mod RW {}
125 }
126 #[doc = "Stop Bit Number Select"]
127 pub mod SBNS {
128 pub const offset: u32 = 13;
129 pub const mask: u32 = 0x01 << offset;
130 pub mod R {}
131 pub mod W {}
132 pub mod RW {
133 #[doc = "One stop bit."]
134 pub const SBNS_0: u32 = 0;
135 #[doc = "Two stop bits."]
136 pub const SBNS_1: u32 = 0x01;
137 }
138 }
139 #[doc = "RX Input Active Edge Interrupt Enable"]
140 pub mod RXEDGIE {
141 pub const offset: u32 = 14;
142 pub const mask: u32 = 0x01 << offset;
143 pub mod R {}
144 pub mod W {}
145 pub mod RW {
146 #[doc = "Hardware interrupts from STAT\\[RXEDGIF\\] are disabled."]
147 pub const RXEDGIE_0: u32 = 0;
148 #[doc = "Hardware interrupt is requested when STAT\\[RXEDGIF\\] flag is 1."]
149 pub const RXEDGIE_1: u32 = 0x01;
150 }
151 }
152 #[doc = "LIN Break Detect Interrupt Enable"]
153 pub mod LBKDIE {
154 pub const offset: u32 = 15;
155 pub const mask: u32 = 0x01 << offset;
156 pub mod R {}
157 pub mod W {}
158 pub mod RW {
159 #[doc = "Hardware interrupts from STAT\\[LBKDIF\\] flag are disabled (use polling)."]
160 pub const LBKDIE_0: u32 = 0;
161 #[doc = "Hardware interrupt requested when STAT\\[LBKDIF\\] flag is 1."]
162 pub const LBKDIE_1: u32 = 0x01;
163 }
164 }
165 #[doc = "Resynchronization Disable"]
166 pub mod RESYNCDIS {
167 pub const offset: u32 = 16;
168 pub const mask: u32 = 0x01 << offset;
169 pub mod R {}
170 pub mod W {}
171 pub mod RW {
172 #[doc = "Resynchronization during received data word is supported"]
173 pub const RESYNCDIS_0: u32 = 0;
174 #[doc = "Resynchronization during received data word is disabled"]
175 pub const RESYNCDIS_1: u32 = 0x01;
176 }
177 }
178 #[doc = "Both Edge Sampling"]
179 pub mod BOTHEDGE {
180 pub const offset: u32 = 17;
181 pub const mask: u32 = 0x01 << offset;
182 pub mod R {}
183 pub mod W {}
184 pub mod RW {
185 #[doc = "Receiver samples input data using the rising edge of the baud rate clock."]
186 pub const BOTHEDGE_0: u32 = 0;
187 #[doc = "Receiver samples input data using the rising and falling edge of the baud rate clock."]
188 pub const BOTHEDGE_1: u32 = 0x01;
189 }
190 }
191 #[doc = "Match Configuration"]
192 pub mod MATCFG {
193 pub const offset: u32 = 18;
194 pub const mask: u32 = 0x03 << offset;
195 pub mod R {}
196 pub mod W {}
197 pub mod RW {
198 #[doc = "Address Match Wakeup"]
199 pub const MATCFG_0: u32 = 0;
200 #[doc = "Idle Match Wakeup"]
201 pub const MATCFG_1: u32 = 0x01;
202 #[doc = "Match On and Match Off"]
203 pub const MATCFG_2: u32 = 0x02;
204 #[doc = "Enables RWU on Data Match and Match On/Off for transmitter CTS input"]
205 pub const MATCFG_3: u32 = 0x03;
206 }
207 }
208 #[doc = "Receiver Idle DMA Enable"]
209 pub mod RIDMAE {
210 pub const offset: u32 = 20;
211 pub const mask: u32 = 0x01 << offset;
212 pub mod R {}
213 pub mod W {}
214 pub mod RW {
215 #[doc = "DMA request disabled."]
216 pub const RIDMAE_0: u32 = 0;
217 #[doc = "DMA request enabled."]
218 pub const RIDMAE_1: u32 = 0x01;
219 }
220 }
221 #[doc = "Receiver Full DMA Enable"]
222 pub mod RDMAE {
223 pub const offset: u32 = 21;
224 pub const mask: u32 = 0x01 << offset;
225 pub mod R {}
226 pub mod W {}
227 pub mod RW {
228 #[doc = "DMA request disabled."]
229 pub const RDMAE_0: u32 = 0;
230 #[doc = "DMA request enabled."]
231 pub const RDMAE_1: u32 = 0x01;
232 }
233 }
234 #[doc = "Transmitter DMA Enable"]
235 pub mod TDMAE {
236 pub const offset: u32 = 23;
237 pub const mask: u32 = 0x01 << offset;
238 pub mod R {}
239 pub mod W {}
240 pub mod RW {
241 #[doc = "DMA request disabled."]
242 pub const TDMAE_0: u32 = 0;
243 #[doc = "DMA request enabled."]
244 pub const TDMAE_1: u32 = 0x01;
245 }
246 }
247 #[doc = "Oversampling Ratio"]
248 pub mod OSR {
249 pub const offset: u32 = 24;
250 pub const mask: u32 = 0x1f << offset;
251 pub mod R {}
252 pub mod W {}
253 pub mod RW {
254 #[doc = "Writing 0 to this field will result in an oversampling ratio of 16"]
255 pub const OSR_0: u32 = 0;
256 #[doc = "Oversampling ratio of 4, requires BOTHEDGE to be set."]
257 pub const OSR_3: u32 = 0x03;
258 #[doc = "Oversampling ratio of 5, requires BOTHEDGE to be set."]
259 pub const OSR_4: u32 = 0x04;
260 #[doc = "Oversampling ratio of 6, requires BOTHEDGE to be set."]
261 pub const OSR_5: u32 = 0x05;
262 #[doc = "Oversampling ratio of 7, requires BOTHEDGE to be set."]
263 pub const OSR_6: u32 = 0x06;
264 #[doc = "Oversampling ratio of 8."]
265 pub const OSR_7: u32 = 0x07;
266 #[doc = "Oversampling ratio of 9."]
267 pub const OSR_8: u32 = 0x08;
268 #[doc = "Oversampling ratio of 10."]
269 pub const OSR_9: u32 = 0x09;
270 #[doc = "Oversampling ratio of 11."]
271 pub const OSR_10: u32 = 0x0a;
272 #[doc = "Oversampling ratio of 12."]
273 pub const OSR_11: u32 = 0x0b;
274 #[doc = "Oversampling ratio of 13."]
275 pub const OSR_12: u32 = 0x0c;
276 #[doc = "Oversampling ratio of 14."]
277 pub const OSR_13: u32 = 0x0d;
278 #[doc = "Oversampling ratio of 15."]
279 pub const OSR_14: u32 = 0x0e;
280 #[doc = "Oversampling ratio of 16."]
281 pub const OSR_15: u32 = 0x0f;
282 #[doc = "Oversampling ratio of 17."]
283 pub const OSR_16: u32 = 0x10;
284 #[doc = "Oversampling ratio of 18."]
285 pub const OSR_17: u32 = 0x11;
286 #[doc = "Oversampling ratio of 19."]
287 pub const OSR_18: u32 = 0x12;
288 #[doc = "Oversampling ratio of 20."]
289 pub const OSR_19: u32 = 0x13;
290 #[doc = "Oversampling ratio of 21."]
291 pub const OSR_20: u32 = 0x14;
292 #[doc = "Oversampling ratio of 22."]
293 pub const OSR_21: u32 = 0x15;
294 #[doc = "Oversampling ratio of 23."]
295 pub const OSR_22: u32 = 0x16;
296 #[doc = "Oversampling ratio of 24."]
297 pub const OSR_23: u32 = 0x17;
298 #[doc = "Oversampling ratio of 25."]
299 pub const OSR_24: u32 = 0x18;
300 #[doc = "Oversampling ratio of 26."]
301 pub const OSR_25: u32 = 0x19;
302 #[doc = "Oversampling ratio of 27."]
303 pub const OSR_26: u32 = 0x1a;
304 #[doc = "Oversampling ratio of 28."]
305 pub const OSR_27: u32 = 0x1b;
306 #[doc = "Oversampling ratio of 29."]
307 pub const OSR_28: u32 = 0x1c;
308 #[doc = "Oversampling ratio of 30."]
309 pub const OSR_29: u32 = 0x1d;
310 #[doc = "Oversampling ratio of 31."]
311 pub const OSR_30: u32 = 0x1e;
312 #[doc = "Oversampling ratio of 32."]
313 pub const OSR_31: u32 = 0x1f;
314 }
315 }
316 #[doc = "10-bit Mode select"]
317 pub mod M10 {
318 pub const offset: u32 = 29;
319 pub const mask: u32 = 0x01 << offset;
320 pub mod R {}
321 pub mod W {}
322 pub mod RW {
323 #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters."]
324 pub const M10_0: u32 = 0;
325 #[doc = "Receiver and transmitter use 10-bit data characters."]
326 pub const M10_1: u32 = 0x01;
327 }
328 }
329 #[doc = "Match Address Mode Enable 2"]
330 pub mod MAEN2 {
331 pub const offset: u32 = 30;
332 pub const mask: u32 = 0x01 << offset;
333 pub mod R {}
334 pub mod W {}
335 pub mod RW {
336 #[doc = "Normal operation."]
337 pub const MAEN2_0: u32 = 0;
338 #[doc = "Enables automatic address matching or data matching mode for MATCH\\[MA2\\]."]
339 pub const MAEN2_1: u32 = 0x01;
340 }
341 }
342 #[doc = "Match Address Mode Enable 1"]
343 pub mod MAEN1 {
344 pub const offset: u32 = 31;
345 pub const mask: u32 = 0x01 << offset;
346 pub mod R {}
347 pub mod W {}
348 pub mod RW {
349 #[doc = "Normal operation."]
350 pub const MAEN1_0: u32 = 0;
351 #[doc = "Enables automatic address matching or data matching mode for MATCH\\[MA1\\]."]
352 pub const MAEN1_1: u32 = 0x01;
353 }
354 }
355}
356#[doc = "LPUART Status Register"]
357pub mod STAT {
358 #[doc = "Match 2 Flag"]
359 pub mod MA2F {
360 pub const offset: u32 = 14;
361 pub const mask: u32 = 0x01 << offset;
362 pub mod R {}
363 pub mod W {}
364 pub mod RW {
365 #[doc = "Received data is not equal to MA2"]
366 pub const MA2F_0: u32 = 0;
367 #[doc = "Received data is equal to MA2"]
368 pub const MA2F_1: u32 = 0x01;
369 }
370 }
371 #[doc = "Match 1 Flag"]
372 pub mod MA1F {
373 pub const offset: u32 = 15;
374 pub const mask: u32 = 0x01 << offset;
375 pub mod R {}
376 pub mod W {}
377 pub mod RW {
378 #[doc = "Received data is not equal to MA1"]
379 pub const MA1F_0: u32 = 0;
380 #[doc = "Received data is equal to MA1"]
381 pub const MA1F_1: u32 = 0x01;
382 }
383 }
384 #[doc = "Parity Error Flag"]
385 pub mod PF {
386 pub const offset: u32 = 16;
387 pub const mask: u32 = 0x01 << offset;
388 pub mod R {}
389 pub mod W {}
390 pub mod RW {
391 #[doc = "No parity error."]
392 pub const PF_0: u32 = 0;
393 #[doc = "Parity error."]
394 pub const PF_1: u32 = 0x01;
395 }
396 }
397 #[doc = "Framing Error Flag"]
398 pub mod FE {
399 pub const offset: u32 = 17;
400 pub const mask: u32 = 0x01 << offset;
401 pub mod R {}
402 pub mod W {}
403 pub mod RW {
404 #[doc = "No framing error detected. This does not guarantee the framing is correct."]
405 pub const FE_0: u32 = 0;
406 #[doc = "Framing error."]
407 pub const FE_1: u32 = 0x01;
408 }
409 }
410 #[doc = "Noise Flag"]
411 pub mod NF {
412 pub const offset: u32 = 18;
413 pub const mask: u32 = 0x01 << offset;
414 pub mod R {}
415 pub mod W {}
416 pub mod RW {
417 #[doc = "No noise detected."]
418 pub const NF_0: u32 = 0;
419 #[doc = "Noise detected in the received character in the DATA register."]
420 pub const NF_1: u32 = 0x01;
421 }
422 }
423 #[doc = "Receiver Overrun Flag"]
424 pub mod OR {
425 pub const offset: u32 = 19;
426 pub const mask: u32 = 0x01 << offset;
427 pub mod R {}
428 pub mod W {}
429 pub mod RW {
430 #[doc = "No overrun."]
431 pub const OR_0: u32 = 0;
432 #[doc = "Receive overrun (new LPUART data lost)."]
433 pub const OR_1: u32 = 0x01;
434 }
435 }
436 #[doc = "Idle Line Flag"]
437 pub mod IDLE {
438 pub const offset: u32 = 20;
439 pub const mask: u32 = 0x01 << offset;
440 pub mod R {}
441 pub mod W {}
442 pub mod RW {
443 #[doc = "No idle line detected."]
444 pub const IDLE_0: u32 = 0;
445 #[doc = "Idle line was detected."]
446 pub const IDLE_1: u32 = 0x01;
447 }
448 }
449 #[doc = "Receive Data Register Full Flag"]
450 pub mod RDRF {
451 pub const offset: u32 = 21;
452 pub const mask: u32 = 0x01 << offset;
453 pub mod R {}
454 pub mod W {}
455 pub mod RW {
456 #[doc = "Receive data buffer empty."]
457 pub const RDRF_0: u32 = 0;
458 #[doc = "Receive data buffer full."]
459 pub const RDRF_1: u32 = 0x01;
460 }
461 }
462 #[doc = "Transmission Complete Flag"]
463 pub mod TC {
464 pub const offset: u32 = 22;
465 pub const mask: u32 = 0x01 << offset;
466 pub mod R {}
467 pub mod W {}
468 pub mod RW {
469 #[doc = "Transmitter active (sending data, a preamble, or a break)."]
470 pub const TC_0: u32 = 0;
471 #[doc = "Transmitter idle (transmission activity complete)."]
472 pub const TC_1: u32 = 0x01;
473 }
474 }
475 #[doc = "Transmit Data Register Empty Flag"]
476 pub mod TDRE {
477 pub const offset: u32 = 23;
478 pub const mask: u32 = 0x01 << offset;
479 pub mod R {}
480 pub mod W {}
481 pub mod RW {
482 #[doc = "Transmit data buffer full."]
483 pub const TDRE_0: u32 = 0;
484 #[doc = "Transmit data buffer empty."]
485 pub const TDRE_1: u32 = 0x01;
486 }
487 }
488 #[doc = "Receiver Active Flag"]
489 pub mod RAF {
490 pub const offset: u32 = 24;
491 pub const mask: u32 = 0x01 << offset;
492 pub mod R {}
493 pub mod W {}
494 pub mod RW {
495 #[doc = "LPUART receiver idle waiting for a start bit."]
496 pub const RAF_0: u32 = 0;
497 #[doc = "LPUART receiver active (RXD input not idle)."]
498 pub const RAF_1: u32 = 0x01;
499 }
500 }
501 #[doc = "LIN Break Detection Enable"]
502 pub mod LBKDE {
503 pub const offset: u32 = 25;
504 pub const mask: u32 = 0x01 << offset;
505 pub mod R {}
506 pub mod W {}
507 pub mod RW {
508 #[doc = "LIN break detect is disabled, normal break character can be detected."]
509 pub const LBKDE_0: u32 = 0;
510 #[doc = "LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1)."]
511 pub const LBKDE_1: u32 = 0x01;
512 }
513 }
514 #[doc = "Break Character Generation Length"]
515 pub mod BRK13 {
516 pub const offset: u32 = 26;
517 pub const mask: u32 = 0x01 << offset;
518 pub mod R {}
519 pub mod W {}
520 pub mod RW {
521 #[doc = "Break character is transmitted with length of 9 to 13 bit times."]
522 pub const BRK13_0: u32 = 0;
523 #[doc = "Break character is transmitted with length of 12 to 15 bit times."]
524 pub const BRK13_1: u32 = 0x01;
525 }
526 }
527 #[doc = "Receive Wake Up Idle Detect"]
528 pub mod RWUID {
529 pub const offset: u32 = 27;
530 pub const mask: u32 = 0x01 << offset;
531 pub mod R {}
532 pub mod W {}
533 pub mod RW {
534 #[doc = "During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match."]
535 pub const RWUID_0: u32 = 0;
536 #[doc = "During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match."]
537 pub const RWUID_1: u32 = 0x01;
538 }
539 }
540 #[doc = "Receive Data Inversion"]
541 pub mod RXINV {
542 pub const offset: u32 = 28;
543 pub const mask: u32 = 0x01 << offset;
544 pub mod R {}
545 pub mod W {}
546 pub mod RW {
547 #[doc = "Receive data not inverted."]
548 pub const RXINV_0: u32 = 0;
549 #[doc = "Receive data inverted."]
550 pub const RXINV_1: u32 = 0x01;
551 }
552 }
553 #[doc = "MSB First"]
554 pub mod MSBF {
555 pub const offset: u32 = 29;
556 pub const mask: u32 = 0x01 << offset;
557 pub mod R {}
558 pub mod W {}
559 pub mod RW {
560 #[doc = "LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0."]
561 pub const MSBF_0: u32 = 0;
562 #[doc = "MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL\\[M\\], CTRL\\[PE\\] and BAUD\\[M10\\]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL\\[M\\] and CTRL\\[PE\\]."]
563 pub const MSBF_1: u32 = 0x01;
564 }
565 }
566 #[doc = "RXD Pin Active Edge Interrupt Flag"]
567 pub mod RXEDGIF {
568 pub const offset: u32 = 30;
569 pub const mask: u32 = 0x01 << offset;
570 pub mod R {}
571 pub mod W {}
572 pub mod RW {
573 #[doc = "No active edge on the receive pin has occurred."]
574 pub const RXEDGIF_0: u32 = 0;
575 #[doc = "An active edge on the receive pin has occurred."]
576 pub const RXEDGIF_1: u32 = 0x01;
577 }
578 }
579 #[doc = "LIN Break Detect Interrupt Flag"]
580 pub mod LBKDIF {
581 pub const offset: u32 = 31;
582 pub const mask: u32 = 0x01 << offset;
583 pub mod R {}
584 pub mod W {}
585 pub mod RW {
586 #[doc = "No LIN break character has been detected."]
587 pub const LBKDIF_0: u32 = 0;
588 #[doc = "LIN break character has been detected."]
589 pub const LBKDIF_1: u32 = 0x01;
590 }
591 }
592}
593#[doc = "LPUART Control Register"]
594pub mod CTRL {
595 #[doc = "Parity Type"]
596 pub mod PT {
597 pub const offset: u32 = 0;
598 pub const mask: u32 = 0x01 << offset;
599 pub mod R {}
600 pub mod W {}
601 pub mod RW {
602 #[doc = "Even parity."]
603 pub const PT_0: u32 = 0;
604 #[doc = "Odd parity."]
605 pub const PT_1: u32 = 0x01;
606 }
607 }
608 #[doc = "Parity Enable"]
609 pub mod PE {
610 pub const offset: u32 = 1;
611 pub const mask: u32 = 0x01 << offset;
612 pub mod R {}
613 pub mod W {}
614 pub mod RW {
615 #[doc = "No hardware parity generation or checking."]
616 pub const PE_0: u32 = 0;
617 #[doc = "Parity enabled."]
618 pub const PE_1: u32 = 0x01;
619 }
620 }
621 #[doc = "Idle Line Type Select"]
622 pub mod ILT {
623 pub const offset: u32 = 2;
624 pub const mask: u32 = 0x01 << offset;
625 pub mod R {}
626 pub mod W {}
627 pub mod RW {
628 #[doc = "Idle character bit count starts after start bit."]
629 pub const ILT_0: u32 = 0;
630 #[doc = "Idle character bit count starts after stop bit."]
631 pub const ILT_1: u32 = 0x01;
632 }
633 }
634 #[doc = "Receiver Wakeup Method Select"]
635 pub mod WAKE {
636 pub const offset: u32 = 3;
637 pub const mask: u32 = 0x01 << offset;
638 pub mod R {}
639 pub mod W {}
640 pub mod RW {
641 #[doc = "Configures RWU for idle-line wakeup."]
642 pub const WAKE_0: u32 = 0;
643 #[doc = "Configures RWU with address-mark wakeup."]
644 pub const WAKE_1: u32 = 0x01;
645 }
646 }
647 #[doc = "9-Bit or 8-Bit Mode Select"]
648 pub mod M {
649 pub const offset: u32 = 4;
650 pub const mask: u32 = 0x01 << offset;
651 pub mod R {}
652 pub mod W {}
653 pub mod RW {
654 #[doc = "Receiver and transmitter use 8-bit data characters."]
655 pub const M_0: u32 = 0;
656 #[doc = "Receiver and transmitter use 9-bit data characters."]
657 pub const M_1: u32 = 0x01;
658 }
659 }
660 #[doc = "Receiver Source Select"]
661 pub mod RSRC {
662 pub const offset: u32 = 5;
663 pub const mask: u32 = 0x01 << offset;
664 pub mod R {}
665 pub mod W {}
666 pub mod RW {
667 #[doc = "Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin."]
668 pub const RSRC_0: u32 = 0;
669 #[doc = "Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input."]
670 pub const RSRC_1: u32 = 0x01;
671 }
672 }
673 #[doc = "Doze Enable"]
674 pub mod DOZEEN {
675 pub const offset: u32 = 6;
676 pub const mask: u32 = 0x01 << offset;
677 pub mod R {}
678 pub mod W {}
679 pub mod RW {
680 #[doc = "LPUART is enabled in Doze mode."]
681 pub const DOZEEN_0: u32 = 0;
682 #[doc = "LPUART is disabled in Doze mode."]
683 pub const DOZEEN_1: u32 = 0x01;
684 }
685 }
686 #[doc = "Loop Mode Select"]
687 pub mod LOOPS {
688 pub const offset: u32 = 7;
689 pub const mask: u32 = 0x01 << offset;
690 pub mod R {}
691 pub mod W {}
692 pub mod RW {
693 #[doc = "Normal operation - RXD and TXD use separate pins."]
694 pub const LOOPS_0: u32 = 0;
695 #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."]
696 pub const LOOPS_1: u32 = 0x01;
697 }
698 }
699 #[doc = "Idle Configuration"]
700 pub mod IDLECFG {
701 pub const offset: u32 = 8;
702 pub const mask: u32 = 0x07 << offset;
703 pub mod R {}
704 pub mod W {}
705 pub mod RW {
706 #[doc = "1 idle character"]
707 pub const IDLECFG_0: u32 = 0;
708 #[doc = "2 idle characters"]
709 pub const IDLECFG_1: u32 = 0x01;
710 #[doc = "4 idle characters"]
711 pub const IDLECFG_2: u32 = 0x02;
712 #[doc = "8 idle characters"]
713 pub const IDLECFG_3: u32 = 0x03;
714 #[doc = "16 idle characters"]
715 pub const IDLECFG_4: u32 = 0x04;
716 #[doc = "32 idle characters"]
717 pub const IDLECFG_5: u32 = 0x05;
718 #[doc = "64 idle characters"]
719 pub const IDLECFG_6: u32 = 0x06;
720 #[doc = "128 idle characters"]
721 pub const IDLECFG_7: u32 = 0x07;
722 }
723 }
724 #[doc = "7-Bit Mode Select"]
725 pub mod M7 {
726 pub const offset: u32 = 11;
727 pub const mask: u32 = 0x01 << offset;
728 pub mod R {}
729 pub mod W {}
730 pub mod RW {
731 #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."]
732 pub const M7_0: u32 = 0;
733 #[doc = "Receiver and transmitter use 7-bit data characters."]
734 pub const M7_1: u32 = 0x01;
735 }
736 }
737 #[doc = "Match 2 Interrupt Enable"]
738 pub mod MA2IE {
739 pub const offset: u32 = 14;
740 pub const mask: u32 = 0x01 << offset;
741 pub mod R {}
742 pub mod W {}
743 pub mod RW {
744 #[doc = "MA2F interrupt disabled"]
745 pub const MA2IE_0: u32 = 0;
746 #[doc = "MA2F interrupt enabled"]
747 pub const MA2IE_1: u32 = 0x01;
748 }
749 }
750 #[doc = "Match 1 Interrupt Enable"]
751 pub mod MA1IE {
752 pub const offset: u32 = 15;
753 pub const mask: u32 = 0x01 << offset;
754 pub mod R {}
755 pub mod W {}
756 pub mod RW {
757 #[doc = "MA1F interrupt disabled"]
758 pub const MA1IE_0: u32 = 0;
759 #[doc = "MA1F interrupt enabled"]
760 pub const MA1IE_1: u32 = 0x01;
761 }
762 }
763 #[doc = "Send Break"]
764 pub mod SBK {
765 pub const offset: u32 = 16;
766 pub const mask: u32 = 0x01 << offset;
767 pub mod R {}
768 pub mod W {}
769 pub mod RW {
770 #[doc = "Normal transmitter operation."]
771 pub const SBK_0: u32 = 0;
772 #[doc = "Queue break character(s) to be sent."]
773 pub const SBK_1: u32 = 0x01;
774 }
775 }
776 #[doc = "Receiver Wakeup Control"]
777 pub mod RWU {
778 pub const offset: u32 = 17;
779 pub const mask: u32 = 0x01 << offset;
780 pub mod R {}
781 pub mod W {}
782 pub mod RW {
783 #[doc = "Normal receiver operation."]
784 pub const RWU_0: u32 = 0;
785 #[doc = "LPUART receiver in standby waiting for wakeup condition."]
786 pub const RWU_1: u32 = 0x01;
787 }
788 }
789 #[doc = "Receiver Enable"]
790 pub mod RE {
791 pub const offset: u32 = 18;
792 pub const mask: u32 = 0x01 << offset;
793 pub mod R {}
794 pub mod W {}
795 pub mod RW {
796 #[doc = "Receiver disabled."]
797 pub const RE_0: u32 = 0;
798 #[doc = "Receiver enabled."]
799 pub const RE_1: u32 = 0x01;
800 }
801 }
802 #[doc = "Transmitter Enable"]
803 pub mod TE {
804 pub const offset: u32 = 19;
805 pub const mask: u32 = 0x01 << offset;
806 pub mod R {}
807 pub mod W {}
808 pub mod RW {
809 #[doc = "Transmitter disabled."]
810 pub const TE_0: u32 = 0;
811 #[doc = "Transmitter enabled."]
812 pub const TE_1: u32 = 0x01;
813 }
814 }
815 #[doc = "Idle Line Interrupt Enable"]
816 pub mod ILIE {
817 pub const offset: u32 = 20;
818 pub const mask: u32 = 0x01 << offset;
819 pub mod R {}
820 pub mod W {}
821 pub mod RW {
822 #[doc = "Hardware interrupts from IDLE disabled; use polling."]
823 pub const ILIE_0: u32 = 0;
824 #[doc = "Hardware interrupt requested when IDLE flag is 1."]
825 pub const ILIE_1: u32 = 0x01;
826 }
827 }
828 #[doc = "Receiver Interrupt Enable"]
829 pub mod RIE {
830 pub const offset: u32 = 21;
831 pub const mask: u32 = 0x01 << offset;
832 pub mod R {}
833 pub mod W {}
834 pub mod RW {
835 #[doc = "Hardware interrupts from RDRF disabled; use polling."]
836 pub const RIE_0: u32 = 0;
837 #[doc = "Hardware interrupt requested when RDRF flag is 1."]
838 pub const RIE_1: u32 = 0x01;
839 }
840 }
841 #[doc = "Transmission Complete Interrupt Enable for"]
842 pub mod TCIE {
843 pub const offset: u32 = 22;
844 pub const mask: u32 = 0x01 << offset;
845 pub mod R {}
846 pub mod W {}
847 pub mod RW {
848 #[doc = "Hardware interrupts from TC disabled; use polling."]
849 pub const TCIE_0: u32 = 0;
850 #[doc = "Hardware interrupt requested when TC flag is 1."]
851 pub const TCIE_1: u32 = 0x01;
852 }
853 }
854 #[doc = "Transmit Interrupt Enable"]
855 pub mod TIE {
856 pub const offset: u32 = 23;
857 pub const mask: u32 = 0x01 << offset;
858 pub mod R {}
859 pub mod W {}
860 pub mod RW {
861 #[doc = "Hardware interrupts from TDRE disabled; use polling."]
862 pub const TIE_0: u32 = 0;
863 #[doc = "Hardware interrupt requested when TDRE flag is 1."]
864 pub const TIE_1: u32 = 0x01;
865 }
866 }
867 #[doc = "Parity Error Interrupt Enable"]
868 pub mod PEIE {
869 pub const offset: u32 = 24;
870 pub const mask: u32 = 0x01 << offset;
871 pub mod R {}
872 pub mod W {}
873 pub mod RW {
874 #[doc = "PF interrupts disabled; use polling)."]
875 pub const PEIE_0: u32 = 0;
876 #[doc = "Hardware interrupt requested when PF is set."]
877 pub const PEIE_1: u32 = 0x01;
878 }
879 }
880 #[doc = "Framing Error Interrupt Enable"]
881 pub mod FEIE {
882 pub const offset: u32 = 25;
883 pub const mask: u32 = 0x01 << offset;
884 pub mod R {}
885 pub mod W {}
886 pub mod RW {
887 #[doc = "FE interrupts disabled; use polling."]
888 pub const FEIE_0: u32 = 0;
889 #[doc = "Hardware interrupt requested when FE is set."]
890 pub const FEIE_1: u32 = 0x01;
891 }
892 }
893 #[doc = "Noise Error Interrupt Enable"]
894 pub mod NEIE {
895 pub const offset: u32 = 26;
896 pub const mask: u32 = 0x01 << offset;
897 pub mod R {}
898 pub mod W {}
899 pub mod RW {
900 #[doc = "NF interrupts disabled; use polling."]
901 pub const NEIE_0: u32 = 0;
902 #[doc = "Hardware interrupt requested when NF is set."]
903 pub const NEIE_1: u32 = 0x01;
904 }
905 }
906 #[doc = "Overrun Interrupt Enable"]
907 pub mod ORIE {
908 pub const offset: u32 = 27;
909 pub const mask: u32 = 0x01 << offset;
910 pub mod R {}
911 pub mod W {}
912 pub mod RW {
913 #[doc = "OR interrupts disabled; use polling."]
914 pub const ORIE_0: u32 = 0;
915 #[doc = "Hardware interrupt requested when OR is set."]
916 pub const ORIE_1: u32 = 0x01;
917 }
918 }
919 #[doc = "Transmit Data Inversion"]
920 pub mod TXINV {
921 pub const offset: u32 = 28;
922 pub const mask: u32 = 0x01 << offset;
923 pub mod R {}
924 pub mod W {}
925 pub mod RW {
926 #[doc = "Transmit data not inverted."]
927 pub const TXINV_0: u32 = 0;
928 #[doc = "Transmit data inverted."]
929 pub const TXINV_1: u32 = 0x01;
930 }
931 }
932 #[doc = "TXD Pin Direction in Single-Wire Mode"]
933 pub mod TXDIR {
934 pub const offset: u32 = 29;
935 pub const mask: u32 = 0x01 << offset;
936 pub mod R {}
937 pub mod W {}
938 pub mod RW {
939 #[doc = "TXD pin is an input in single-wire mode."]
940 pub const TXDIR_0: u32 = 0;
941 #[doc = "TXD pin is an output in single-wire mode."]
942 pub const TXDIR_1: u32 = 0x01;
943 }
944 }
945 #[doc = "Receive Bit 9 / Transmit Bit 8"]
946 pub mod R9T8 {
947 pub const offset: u32 = 30;
948 pub const mask: u32 = 0x01 << offset;
949 pub mod R {}
950 pub mod W {}
951 pub mod RW {}
952 }
953 #[doc = "Receive Bit 8 / Transmit Bit 9"]
954 pub mod R8T9 {
955 pub const offset: u32 = 31;
956 pub const mask: u32 = 0x01 << offset;
957 pub mod R {}
958 pub mod W {}
959 pub mod RW {}
960 }
961}
962#[doc = "LPUART Data Register"]
963pub mod DATA {
964 #[doc = "R0T0"]
965 pub mod R0T0 {
966 pub const offset: u32 = 0;
967 pub const mask: u32 = 0x01 << offset;
968 pub mod R {}
969 pub mod W {}
970 pub mod RW {}
971 }
972 #[doc = "R1T1"]
973 pub mod R1T1 {
974 pub const offset: u32 = 1;
975 pub const mask: u32 = 0x01 << offset;
976 pub mod R {}
977 pub mod W {}
978 pub mod RW {}
979 }
980 #[doc = "R2T2"]
981 pub mod R2T2 {
982 pub const offset: u32 = 2;
983 pub const mask: u32 = 0x01 << offset;
984 pub mod R {}
985 pub mod W {}
986 pub mod RW {}
987 }
988 #[doc = "R3T3"]
989 pub mod R3T3 {
990 pub const offset: u32 = 3;
991 pub const mask: u32 = 0x01 << offset;
992 pub mod R {}
993 pub mod W {}
994 pub mod RW {}
995 }
996 #[doc = "R4T4"]
997 pub mod R4T4 {
998 pub const offset: u32 = 4;
999 pub const mask: u32 = 0x01 << offset;
1000 pub mod R {}
1001 pub mod W {}
1002 pub mod RW {}
1003 }
1004 #[doc = "R5T5"]
1005 pub mod R5T5 {
1006 pub const offset: u32 = 5;
1007 pub const mask: u32 = 0x01 << offset;
1008 pub mod R {}
1009 pub mod W {}
1010 pub mod RW {}
1011 }
1012 #[doc = "R6T6"]
1013 pub mod R6T6 {
1014 pub const offset: u32 = 6;
1015 pub const mask: u32 = 0x01 << offset;
1016 pub mod R {}
1017 pub mod W {}
1018 pub mod RW {}
1019 }
1020 #[doc = "R7T7"]
1021 pub mod R7T7 {
1022 pub const offset: u32 = 7;
1023 pub const mask: u32 = 0x01 << offset;
1024 pub mod R {}
1025 pub mod W {}
1026 pub mod RW {}
1027 }
1028 #[doc = "R8T8"]
1029 pub mod R8T8 {
1030 pub const offset: u32 = 8;
1031 pub const mask: u32 = 0x01 << offset;
1032 pub mod R {}
1033 pub mod W {}
1034 pub mod RW {}
1035 }
1036 #[doc = "R9T9"]
1037 pub mod R9T9 {
1038 pub const offset: u32 = 9;
1039 pub const mask: u32 = 0x01 << offset;
1040 pub mod R {}
1041 pub mod W {}
1042 pub mod RW {}
1043 }
1044 #[doc = "Idle Line"]
1045 pub mod IDLINE {
1046 pub const offset: u32 = 11;
1047 pub const mask: u32 = 0x01 << offset;
1048 pub mod R {}
1049 pub mod W {}
1050 pub mod RW {
1051 #[doc = "Receiver was not idle before receiving this character."]
1052 pub const IDLINE_0: u32 = 0;
1053 #[doc = "Receiver was idle before receiving this character."]
1054 pub const IDLINE_1: u32 = 0x01;
1055 }
1056 }
1057 #[doc = "Receive Buffer Empty"]
1058 pub mod RXEMPT {
1059 pub const offset: u32 = 12;
1060 pub const mask: u32 = 0x01 << offset;
1061 pub mod R {}
1062 pub mod W {}
1063 pub mod RW {
1064 #[doc = "Receive buffer contains valid data."]
1065 pub const RXEMPT_0: u32 = 0;
1066 #[doc = "Receive buffer is empty, data returned on read is not valid."]
1067 pub const RXEMPT_1: u32 = 0x01;
1068 }
1069 }
1070 #[doc = "Frame Error / Transmit Special Character"]
1071 pub mod FRETSC {
1072 pub const offset: u32 = 13;
1073 pub const mask: u32 = 0x01 << offset;
1074 pub mod R {}
1075 pub mod W {}
1076 pub mod RW {
1077 #[doc = "The dataword was received without a frame error on read, or transmit a normal character on write."]
1078 pub const FRETSC_0: u32 = 0;
1079 #[doc = "The dataword was received with a frame error, or transmit an idle or break character on transmit."]
1080 pub const FRETSC_1: u32 = 0x01;
1081 }
1082 }
1083 #[doc = "PARITYE"]
1084 pub mod PARITYE {
1085 pub const offset: u32 = 14;
1086 pub const mask: u32 = 0x01 << offset;
1087 pub mod R {}
1088 pub mod W {}
1089 pub mod RW {
1090 #[doc = "The dataword was received without a parity error."]
1091 pub const PARITYE_0: u32 = 0;
1092 #[doc = "The dataword was received with a parity error."]
1093 pub const PARITYE_1: u32 = 0x01;
1094 }
1095 }
1096 #[doc = "NOISY"]
1097 pub mod NOISY {
1098 pub const offset: u32 = 15;
1099 pub const mask: u32 = 0x01 << offset;
1100 pub mod R {}
1101 pub mod W {}
1102 pub mod RW {
1103 #[doc = "The dataword was received without noise."]
1104 pub const NOISY_0: u32 = 0;
1105 #[doc = "The data was received with noise."]
1106 pub const NOISY_1: u32 = 0x01;
1107 }
1108 }
1109}
1110#[doc = "LPUART Match Address Register"]
1111pub mod MATCH {
1112 #[doc = "Match Address 1"]
1113 pub mod MA1 {
1114 pub const offset: u32 = 0;
1115 pub const mask: u32 = 0x03ff << offset;
1116 pub mod R {}
1117 pub mod W {}
1118 pub mod RW {}
1119 }
1120 #[doc = "Match Address 2"]
1121 pub mod MA2 {
1122 pub const offset: u32 = 16;
1123 pub const mask: u32 = 0x03ff << offset;
1124 pub mod R {}
1125 pub mod W {}
1126 pub mod RW {}
1127 }
1128}
1129#[doc = "LPUART Modem IrDA Register"]
1130pub mod MODIR {
1131 #[doc = "Transmitter clear-to-send enable"]
1132 pub mod TXCTSE {
1133 pub const offset: u32 = 0;
1134 pub const mask: u32 = 0x01 << offset;
1135 pub mod R {}
1136 pub mod W {}
1137 pub mod RW {
1138 #[doc = "CTS has no effect on the transmitter."]
1139 pub const TXCTSE_0: u32 = 0;
1140 #[doc = "Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission."]
1141 pub const TXCTSE_1: u32 = 0x01;
1142 }
1143 }
1144 #[doc = "Transmitter request-to-send enable"]
1145 pub mod TXRTSE {
1146 pub const offset: u32 = 1;
1147 pub const mask: u32 = 0x01 << offset;
1148 pub mod R {}
1149 pub mod W {}
1150 pub mod RW {
1151 #[doc = "The transmitter has no effect on RTS."]
1152 pub const TXRTSE_0: u32 = 0;
1153 #[doc = "When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit."]
1154 pub const TXRTSE_1: u32 = 0x01;
1155 }
1156 }
1157 #[doc = "Transmitter request-to-send polarity"]
1158 pub mod TXRTSPOL {
1159 pub const offset: u32 = 2;
1160 pub const mask: u32 = 0x01 << offset;
1161 pub mod R {}
1162 pub mod W {}
1163 pub mod RW {
1164 #[doc = "Transmitter RTS is active low."]
1165 pub const TXRTSPOL_0: u32 = 0;
1166 #[doc = "Transmitter RTS is active high."]
1167 pub const TXRTSPOL_1: u32 = 0x01;
1168 }
1169 }
1170 #[doc = "Receiver request-to-send enable"]
1171 pub mod RXRTSE {
1172 pub const offset: u32 = 3;
1173 pub const mask: u32 = 0x01 << offset;
1174 pub mod R {}
1175 pub mod W {}
1176 pub mod RW {
1177 #[doc = "The receiver has no effect on RTS."]
1178 pub const RXRTSE_0: u32 = 0;
1179 #[doc = "RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full."]
1180 pub const RXRTSE_1: u32 = 0x01;
1181 }
1182 }
1183 #[doc = "Transmit CTS Configuration"]
1184 pub mod TXCTSC {
1185 pub const offset: u32 = 4;
1186 pub const mask: u32 = 0x01 << offset;
1187 pub mod R {}
1188 pub mod W {}
1189 pub mod RW {
1190 #[doc = "CTS input is sampled at the start of each character."]
1191 pub const TXCTSC_0: u32 = 0;
1192 #[doc = "CTS input is sampled when the transmitter is idle."]
1193 pub const TXCTSC_1: u32 = 0x01;
1194 }
1195 }
1196 #[doc = "Transmit CTS Source"]
1197 pub mod TXCTSSRC {
1198 pub const offset: u32 = 5;
1199 pub const mask: u32 = 0x01 << offset;
1200 pub mod R {}
1201 pub mod W {}
1202 pub mod RW {
1203 #[doc = "CTS input is the CTS_B pin."]
1204 pub const TXCTSSRC_0: u32 = 0;
1205 #[doc = "CTS input is the inverted Receiver Match result."]
1206 pub const TXCTSSRC_1: u32 = 0x01;
1207 }
1208 }
1209 #[doc = "Receive RTS Configuration"]
1210 pub mod RTSWATER {
1211 pub const offset: u32 = 8;
1212 pub const mask: u32 = 0x03 << offset;
1213 pub mod R {}
1214 pub mod W {}
1215 pub mod RW {}
1216 }
1217 #[doc = "Transmitter narrow pulse"]
1218 pub mod TNP {
1219 pub const offset: u32 = 16;
1220 pub const mask: u32 = 0x03 << offset;
1221 pub mod R {}
1222 pub mod W {}
1223 pub mod RW {
1224 #[doc = "1/OSR."]
1225 pub const TNP_0: u32 = 0;
1226 #[doc = "2/OSR."]
1227 pub const TNP_1: u32 = 0x01;
1228 #[doc = "3/OSR."]
1229 pub const TNP_2: u32 = 0x02;
1230 #[doc = "4/OSR."]
1231 pub const TNP_3: u32 = 0x03;
1232 }
1233 }
1234 #[doc = "Infrared enable"]
1235 pub mod IREN {
1236 pub const offset: u32 = 18;
1237 pub const mask: u32 = 0x01 << offset;
1238 pub mod R {}
1239 pub mod W {}
1240 pub mod RW {
1241 #[doc = "IR disabled."]
1242 pub const IREN_0: u32 = 0;
1243 #[doc = "IR enabled."]
1244 pub const IREN_1: u32 = 0x01;
1245 }
1246 }
1247}
1248#[doc = "LPUART FIFO Register"]
1249pub mod FIFO {
1250 #[doc = "Receive FIFO Buffer Depth"]
1251 pub mod RXFIFOSIZE {
1252 pub const offset: u32 = 0;
1253 pub const mask: u32 = 0x07 << offset;
1254 pub mod R {}
1255 pub mod W {}
1256 pub mod RW {
1257 #[doc = "Receive FIFO/Buffer depth = 1 dataword."]
1258 pub const RXFIFOSIZE_0: u32 = 0;
1259 #[doc = "Receive FIFO/Buffer depth = 4 datawords."]
1260 pub const RXFIFOSIZE_1: u32 = 0x01;
1261 #[doc = "Receive FIFO/Buffer depth = 8 datawords."]
1262 pub const RXFIFOSIZE_2: u32 = 0x02;
1263 #[doc = "Receive FIFO/Buffer depth = 16 datawords."]
1264 pub const RXFIFOSIZE_3: u32 = 0x03;
1265 #[doc = "Receive FIFO/Buffer depth = 32 datawords."]
1266 pub const RXFIFOSIZE_4: u32 = 0x04;
1267 #[doc = "Receive FIFO/Buffer depth = 64 datawords."]
1268 pub const RXFIFOSIZE_5: u32 = 0x05;
1269 #[doc = "Receive FIFO/Buffer depth = 128 datawords."]
1270 pub const RXFIFOSIZE_6: u32 = 0x06;
1271 #[doc = "Receive FIFO/Buffer depth = 256 datawords."]
1272 pub const RXFIFOSIZE_7: u32 = 0x07;
1273 }
1274 }
1275 #[doc = "Receive FIFO Enable"]
1276 pub mod RXFE {
1277 pub const offset: u32 = 3;
1278 pub const mask: u32 = 0x01 << offset;
1279 pub mod R {}
1280 pub mod W {}
1281 pub mod RW {
1282 #[doc = "Receive FIFO is not enabled. Buffer is depth 1."]
1283 pub const RXFE_0: u32 = 0;
1284 #[doc = "Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE."]
1285 pub const RXFE_1: u32 = 0x01;
1286 }
1287 }
1288 #[doc = "Transmit FIFO Buffer Depth"]
1289 pub mod TXFIFOSIZE {
1290 pub const offset: u32 = 4;
1291 pub const mask: u32 = 0x07 << offset;
1292 pub mod R {}
1293 pub mod W {}
1294 pub mod RW {
1295 #[doc = "Transmit FIFO/Buffer depth = 1 dataword."]
1296 pub const TXFIFOSIZE_0: u32 = 0;
1297 #[doc = "Transmit FIFO/Buffer depth = 4 datawords."]
1298 pub const TXFIFOSIZE_1: u32 = 0x01;
1299 #[doc = "Transmit FIFO/Buffer depth = 8 datawords."]
1300 pub const TXFIFOSIZE_2: u32 = 0x02;
1301 #[doc = "Transmit FIFO/Buffer depth = 16 datawords."]
1302 pub const TXFIFOSIZE_3: u32 = 0x03;
1303 #[doc = "Transmit FIFO/Buffer depth = 32 datawords."]
1304 pub const TXFIFOSIZE_4: u32 = 0x04;
1305 #[doc = "Transmit FIFO/Buffer depth = 64 datawords."]
1306 pub const TXFIFOSIZE_5: u32 = 0x05;
1307 #[doc = "Transmit FIFO/Buffer depth = 128 datawords."]
1308 pub const TXFIFOSIZE_6: u32 = 0x06;
1309 #[doc = "Transmit FIFO/Buffer depth = 256 datawords"]
1310 pub const TXFIFOSIZE_7: u32 = 0x07;
1311 }
1312 }
1313 #[doc = "Transmit FIFO Enable"]
1314 pub mod TXFE {
1315 pub const offset: u32 = 7;
1316 pub const mask: u32 = 0x01 << offset;
1317 pub mod R {}
1318 pub mod W {}
1319 pub mod RW {
1320 #[doc = "Transmit FIFO is not enabled. Buffer is depth 1."]
1321 pub const TXFE_0: u32 = 0;
1322 #[doc = "Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE."]
1323 pub const TXFE_1: u32 = 0x01;
1324 }
1325 }
1326 #[doc = "Receive FIFO Underflow Interrupt Enable"]
1327 pub mod RXUFE {
1328 pub const offset: u32 = 8;
1329 pub const mask: u32 = 0x01 << offset;
1330 pub mod R {}
1331 pub mod W {}
1332 pub mod RW {
1333 #[doc = "RXUF flag does not generate an interrupt to the host."]
1334 pub const RXUFE_0: u32 = 0;
1335 #[doc = "RXUF flag generates an interrupt to the host."]
1336 pub const RXUFE_1: u32 = 0x01;
1337 }
1338 }
1339 #[doc = "Transmit FIFO Overflow Interrupt Enable"]
1340 pub mod TXOFE {
1341 pub const offset: u32 = 9;
1342 pub const mask: u32 = 0x01 << offset;
1343 pub mod R {}
1344 pub mod W {}
1345 pub mod RW {
1346 #[doc = "TXOF flag does not generate an interrupt to the host."]
1347 pub const TXOFE_0: u32 = 0;
1348 #[doc = "TXOF flag generates an interrupt to the host."]
1349 pub const TXOFE_1: u32 = 0x01;
1350 }
1351 }
1352 #[doc = "Receiver Idle Empty Enable"]
1353 pub mod RXIDEN {
1354 pub const offset: u32 = 10;
1355 pub const mask: u32 = 0x07 << offset;
1356 pub mod R {}
1357 pub mod W {}
1358 pub mod RW {
1359 #[doc = "Disable RDRF assertion due to partially filled FIFO when receiver is idle."]
1360 pub const RXIDEN_0: u32 = 0;
1361 #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character."]
1362 pub const RXIDEN_1: u32 = 0x01;
1363 #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters."]
1364 pub const RXIDEN_2: u32 = 0x02;
1365 #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters."]
1366 pub const RXIDEN_3: u32 = 0x03;
1367 #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters."]
1368 pub const RXIDEN_4: u32 = 0x04;
1369 #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters."]
1370 pub const RXIDEN_5: u32 = 0x05;
1371 #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters."]
1372 pub const RXIDEN_6: u32 = 0x06;
1373 #[doc = "Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters."]
1374 pub const RXIDEN_7: u32 = 0x07;
1375 }
1376 }
1377 #[doc = "Receive FIFO/Buffer Flush"]
1378 pub mod RXFLUSH {
1379 pub const offset: u32 = 14;
1380 pub const mask: u32 = 0x01 << offset;
1381 pub mod R {}
1382 pub mod W {}
1383 pub mod RW {
1384 #[doc = "No flush operation occurs."]
1385 pub const RXFLUSH_0: u32 = 0;
1386 #[doc = "All data in the receive FIFO/buffer is cleared out."]
1387 pub const RXFLUSH_1: u32 = 0x01;
1388 }
1389 }
1390 #[doc = "Transmit FIFO/Buffer Flush"]
1391 pub mod TXFLUSH {
1392 pub const offset: u32 = 15;
1393 pub const mask: u32 = 0x01 << offset;
1394 pub mod R {}
1395 pub mod W {}
1396 pub mod RW {
1397 #[doc = "No flush operation occurs."]
1398 pub const TXFLUSH_0: u32 = 0;
1399 #[doc = "All data in the transmit FIFO/Buffer is cleared out."]
1400 pub const TXFLUSH_1: u32 = 0x01;
1401 }
1402 }
1403 #[doc = "Receiver Buffer Underflow Flag"]
1404 pub mod RXUF {
1405 pub const offset: u32 = 16;
1406 pub const mask: u32 = 0x01 << offset;
1407 pub mod R {}
1408 pub mod W {}
1409 pub mod RW {
1410 #[doc = "No receive buffer underflow has occurred since the last time the flag was cleared."]
1411 pub const RXUF_0: u32 = 0;
1412 #[doc = "At least one receive buffer underflow has occurred since the last time the flag was cleared."]
1413 pub const RXUF_1: u32 = 0x01;
1414 }
1415 }
1416 #[doc = "Transmitter Buffer Overflow Flag"]
1417 pub mod TXOF {
1418 pub const offset: u32 = 17;
1419 pub const mask: u32 = 0x01 << offset;
1420 pub mod R {}
1421 pub mod W {}
1422 pub mod RW {
1423 #[doc = "No transmit buffer overflow has occurred since the last time the flag was cleared."]
1424 pub const TXOF_0: u32 = 0;
1425 #[doc = "At least one transmit buffer overflow has occurred since the last time the flag was cleared."]
1426 pub const TXOF_1: u32 = 0x01;
1427 }
1428 }
1429 #[doc = "Receive Buffer/FIFO Empty"]
1430 pub mod RXEMPT {
1431 pub const offset: u32 = 22;
1432 pub const mask: u32 = 0x01 << offset;
1433 pub mod R {}
1434 pub mod W {}
1435 pub mod RW {
1436 #[doc = "Receive buffer is not empty."]
1437 pub const RXEMPT_0: u32 = 0;
1438 #[doc = "Receive buffer is empty."]
1439 pub const RXEMPT_1: u32 = 0x01;
1440 }
1441 }
1442 #[doc = "Transmit Buffer/FIFO Empty"]
1443 pub mod TXEMPT {
1444 pub const offset: u32 = 23;
1445 pub const mask: u32 = 0x01 << offset;
1446 pub mod R {}
1447 pub mod W {}
1448 pub mod RW {
1449 #[doc = "Transmit buffer is not empty."]
1450 pub const TXEMPT_0: u32 = 0;
1451 #[doc = "Transmit buffer is empty."]
1452 pub const TXEMPT_1: u32 = 0x01;
1453 }
1454 }
1455}
1456#[doc = "LPUART Watermark Register"]
1457pub mod WATER {
1458 #[doc = "Transmit Watermark"]
1459 pub mod TXWATER {
1460 pub const offset: u32 = 0;
1461 pub const mask: u32 = 0x03 << offset;
1462 pub mod R {}
1463 pub mod W {}
1464 pub mod RW {}
1465 }
1466 #[doc = "Transmit Counter"]
1467 pub mod TXCOUNT {
1468 pub const offset: u32 = 8;
1469 pub const mask: u32 = 0x07 << offset;
1470 pub mod R {}
1471 pub mod W {}
1472 pub mod RW {}
1473 }
1474 #[doc = "Receive Watermark"]
1475 pub mod RXWATER {
1476 pub const offset: u32 = 16;
1477 pub const mask: u32 = 0x03 << offset;
1478 pub mod R {}
1479 pub mod W {}
1480 pub mod RW {}
1481 }
1482 #[doc = "Receive Counter"]
1483 pub mod RXCOUNT {
1484 pub const offset: u32 = 24;
1485 pub const mask: u32 = 0x07 << offset;
1486 pub mod R {}
1487 pub mod W {}
1488 pub mod RW {}
1489 }
1490}