rp2040_pac/io_bank0/gpio/
gpio_ctrl.rs

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1#[doc = "Register `GPIO_CTRL` reader"]
2pub type R = crate::R<GPIO_CTRL_SPEC>;
3#[doc = "Register `GPIO_CTRL` writer"]
4pub type W = crate::W<GPIO_CTRL_SPEC>;
5#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."]
6pub type FUNCSEL_R = crate::FieldReader<FUNCSEL_A>;
7#[doc = "0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins.  
8
9Value on reset: 31"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum FUNCSEL_A {
13    #[doc = "0: Connect to JTAG peripheral"]
14    JTAG = 0,
15    #[doc = "1: Connect to matching SPI peripheral"]
16    SPI = 1,
17    #[doc = "2: Connect to matching UART peripheral"]
18    UART = 2,
19    #[doc = "3: Connect to matching I2C peripheral"]
20    I2C = 3,
21    #[doc = "4: Connect to matching PWM peripheral"]
22    PWM = 4,
23    #[doc = "5: Use as a GPIO pin (connect to SIO peripheral)"]
24    SIO = 5,
25    #[doc = "6: Connect to PIO0 peripheral"]
26    PIO0 = 6,
27    #[doc = "7: Connect to PIO1 peripheral"]
28    PIO1 = 7,
29    #[doc = "8: Connect to Clock peripheral"]
30    CLOCK = 8,
31    #[doc = "9: Connect to USB peripheral"]
32    USB = 9,
33    #[doc = "31: Connect to nothing"]
34    NULL = 31,
35}
36impl From<FUNCSEL_A> for u8 {
37    #[inline(always)]
38    fn from(variant: FUNCSEL_A) -> Self {
39        variant as _
40    }
41}
42impl crate::FieldSpec for FUNCSEL_A {
43    type Ux = u8;
44}
45impl FUNCSEL_R {
46    #[doc = "Get enumerated values variant"]
47    #[inline(always)]
48    pub const fn variant(&self) -> Option<FUNCSEL_A> {
49        match self.bits {
50            0 => Some(FUNCSEL_A::JTAG),
51            1 => Some(FUNCSEL_A::SPI),
52            2 => Some(FUNCSEL_A::UART),
53            3 => Some(FUNCSEL_A::I2C),
54            4 => Some(FUNCSEL_A::PWM),
55            5 => Some(FUNCSEL_A::SIO),
56            6 => Some(FUNCSEL_A::PIO0),
57            7 => Some(FUNCSEL_A::PIO1),
58            8 => Some(FUNCSEL_A::CLOCK),
59            9 => Some(FUNCSEL_A::USB),
60            31 => Some(FUNCSEL_A::NULL),
61            _ => None,
62        }
63    }
64    #[doc = "Connect to JTAG peripheral"]
65    #[inline(always)]
66    pub fn is_jtag(&self) -> bool {
67        *self == FUNCSEL_A::JTAG
68    }
69    #[doc = "Connect to matching SPI peripheral"]
70    #[inline(always)]
71    pub fn is_spi(&self) -> bool {
72        *self == FUNCSEL_A::SPI
73    }
74    #[doc = "Connect to matching UART peripheral"]
75    #[inline(always)]
76    pub fn is_uart(&self) -> bool {
77        *self == FUNCSEL_A::UART
78    }
79    #[doc = "Connect to matching I2C peripheral"]
80    #[inline(always)]
81    pub fn is_i2c(&self) -> bool {
82        *self == FUNCSEL_A::I2C
83    }
84    #[doc = "Connect to matching PWM peripheral"]
85    #[inline(always)]
86    pub fn is_pwm(&self) -> bool {
87        *self == FUNCSEL_A::PWM
88    }
89    #[doc = "Use as a GPIO pin (connect to SIO peripheral)"]
90    #[inline(always)]
91    pub fn is_sio(&self) -> bool {
92        *self == FUNCSEL_A::SIO
93    }
94    #[doc = "Connect to PIO0 peripheral"]
95    #[inline(always)]
96    pub fn is_pio0(&self) -> bool {
97        *self == FUNCSEL_A::PIO0
98    }
99    #[doc = "Connect to PIO1 peripheral"]
100    #[inline(always)]
101    pub fn is_pio1(&self) -> bool {
102        *self == FUNCSEL_A::PIO1
103    }
104    #[doc = "Connect to Clock peripheral"]
105    #[inline(always)]
106    pub fn is_clock(&self) -> bool {
107        *self == FUNCSEL_A::CLOCK
108    }
109    #[doc = "Connect to USB peripheral"]
110    #[inline(always)]
111    pub fn is_usb(&self) -> bool {
112        *self == FUNCSEL_A::USB
113    }
114    #[doc = "Connect to nothing"]
115    #[inline(always)]
116    pub fn is_null(&self) -> bool {
117        *self == FUNCSEL_A::NULL
118    }
119}
120#[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."]
121pub type FUNCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, FUNCSEL_A>;
122impl<'a, REG> FUNCSEL_W<'a, REG>
123where
124    REG: crate::Writable + crate::RegisterSpec,
125    REG::Ux: From<u8>,
126{
127    #[doc = "Connect to JTAG peripheral"]
128    #[inline(always)]
129    pub fn jtag(self) -> &'a mut crate::W<REG> {
130        self.variant(FUNCSEL_A::JTAG)
131    }
132    #[doc = "Connect to matching SPI peripheral"]
133    #[inline(always)]
134    pub fn spi(self) -> &'a mut crate::W<REG> {
135        self.variant(FUNCSEL_A::SPI)
136    }
137    #[doc = "Connect to matching UART peripheral"]
138    #[inline(always)]
139    pub fn uart(self) -> &'a mut crate::W<REG> {
140        self.variant(FUNCSEL_A::UART)
141    }
142    #[doc = "Connect to matching I2C peripheral"]
143    #[inline(always)]
144    pub fn i2c(self) -> &'a mut crate::W<REG> {
145        self.variant(FUNCSEL_A::I2C)
146    }
147    #[doc = "Connect to matching PWM peripheral"]
148    #[inline(always)]
149    pub fn pwm(self) -> &'a mut crate::W<REG> {
150        self.variant(FUNCSEL_A::PWM)
151    }
152    #[doc = "Use as a GPIO pin (connect to SIO peripheral)"]
153    #[inline(always)]
154    pub fn sio(self) -> &'a mut crate::W<REG> {
155        self.variant(FUNCSEL_A::SIO)
156    }
157    #[doc = "Connect to PIO0 peripheral"]
158    #[inline(always)]
159    pub fn pio0(self) -> &'a mut crate::W<REG> {
160        self.variant(FUNCSEL_A::PIO0)
161    }
162    #[doc = "Connect to PIO1 peripheral"]
163    #[inline(always)]
164    pub fn pio1(self) -> &'a mut crate::W<REG> {
165        self.variant(FUNCSEL_A::PIO1)
166    }
167    #[doc = "Connect to Clock peripheral"]
168    #[inline(always)]
169    pub fn clock(self) -> &'a mut crate::W<REG> {
170        self.variant(FUNCSEL_A::CLOCK)
171    }
172    #[doc = "Connect to USB peripheral"]
173    #[inline(always)]
174    pub fn usb(self) -> &'a mut crate::W<REG> {
175        self.variant(FUNCSEL_A::USB)
176    }
177    #[doc = "Connect to nothing"]
178    #[inline(always)]
179    pub fn null(self) -> &'a mut crate::W<REG> {
180        self.variant(FUNCSEL_A::NULL)
181    }
182}
183#[doc = "Field `OUTOVER` reader - "]
184pub type OUTOVER_R = crate::FieldReader<OUTOVER_A>;
185#[doc = "  
186
187Value on reset: 0"]
188#[derive(Clone, Copy, Debug, PartialEq, Eq)]
189#[repr(u8)]
190pub enum OUTOVER_A {
191    #[doc = "0: drive output from peripheral signal selected by funcsel"]
192    NORMAL = 0,
193    #[doc = "1: drive output from inverse of peripheral signal selected by funcsel"]
194    INVERT = 1,
195    #[doc = "2: drive output low"]
196    LOW = 2,
197    #[doc = "3: drive output high"]
198    HIGH = 3,
199}
200impl From<OUTOVER_A> for u8 {
201    #[inline(always)]
202    fn from(variant: OUTOVER_A) -> Self {
203        variant as _
204    }
205}
206impl crate::FieldSpec for OUTOVER_A {
207    type Ux = u8;
208}
209impl OUTOVER_R {
210    #[doc = "Get enumerated values variant"]
211    #[inline(always)]
212    pub const fn variant(&self) -> OUTOVER_A {
213        match self.bits {
214            0 => OUTOVER_A::NORMAL,
215            1 => OUTOVER_A::INVERT,
216            2 => OUTOVER_A::LOW,
217            3 => OUTOVER_A::HIGH,
218            _ => unreachable!(),
219        }
220    }
221    #[doc = "drive output from peripheral signal selected by funcsel"]
222    #[inline(always)]
223    pub fn is_normal(&self) -> bool {
224        *self == OUTOVER_A::NORMAL
225    }
226    #[doc = "drive output from inverse of peripheral signal selected by funcsel"]
227    #[inline(always)]
228    pub fn is_invert(&self) -> bool {
229        *self == OUTOVER_A::INVERT
230    }
231    #[doc = "drive output low"]
232    #[inline(always)]
233    pub fn is_low(&self) -> bool {
234        *self == OUTOVER_A::LOW
235    }
236    #[doc = "drive output high"]
237    #[inline(always)]
238    pub fn is_high(&self) -> bool {
239        *self == OUTOVER_A::HIGH
240    }
241}
242#[doc = "Field `OUTOVER` writer - "]
243pub type OUTOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OUTOVER_A>;
244impl<'a, REG> OUTOVER_W<'a, REG>
245where
246    REG: crate::Writable + crate::RegisterSpec,
247    REG::Ux: From<u8>,
248{
249    #[doc = "drive output from peripheral signal selected by funcsel"]
250    #[inline(always)]
251    pub fn normal(self) -> &'a mut crate::W<REG> {
252        self.variant(OUTOVER_A::NORMAL)
253    }
254    #[doc = "drive output from inverse of peripheral signal selected by funcsel"]
255    #[inline(always)]
256    pub fn invert(self) -> &'a mut crate::W<REG> {
257        self.variant(OUTOVER_A::INVERT)
258    }
259    #[doc = "drive output low"]
260    #[inline(always)]
261    pub fn low(self) -> &'a mut crate::W<REG> {
262        self.variant(OUTOVER_A::LOW)
263    }
264    #[doc = "drive output high"]
265    #[inline(always)]
266    pub fn high(self) -> &'a mut crate::W<REG> {
267        self.variant(OUTOVER_A::HIGH)
268    }
269}
270#[doc = "Field `OEOVER` reader - "]
271pub type OEOVER_R = crate::FieldReader<OEOVER_A>;
272#[doc = "  
273
274Value on reset: 0"]
275#[derive(Clone, Copy, Debug, PartialEq, Eq)]
276#[repr(u8)]
277pub enum OEOVER_A {
278    #[doc = "0: drive output enable from peripheral signal selected by funcsel"]
279    NORMAL = 0,
280    #[doc = "1: drive output enable from inverse of peripheral signal selected by funcsel"]
281    INVERT = 1,
282    #[doc = "2: disable output"]
283    DISABLE = 2,
284    #[doc = "3: enable output"]
285    ENABLE = 3,
286}
287impl From<OEOVER_A> for u8 {
288    #[inline(always)]
289    fn from(variant: OEOVER_A) -> Self {
290        variant as _
291    }
292}
293impl crate::FieldSpec for OEOVER_A {
294    type Ux = u8;
295}
296impl OEOVER_R {
297    #[doc = "Get enumerated values variant"]
298    #[inline(always)]
299    pub const fn variant(&self) -> OEOVER_A {
300        match self.bits {
301            0 => OEOVER_A::NORMAL,
302            1 => OEOVER_A::INVERT,
303            2 => OEOVER_A::DISABLE,
304            3 => OEOVER_A::ENABLE,
305            _ => unreachable!(),
306        }
307    }
308    #[doc = "drive output enable from peripheral signal selected by funcsel"]
309    #[inline(always)]
310    pub fn is_normal(&self) -> bool {
311        *self == OEOVER_A::NORMAL
312    }
313    #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"]
314    #[inline(always)]
315    pub fn is_invert(&self) -> bool {
316        *self == OEOVER_A::INVERT
317    }
318    #[doc = "disable output"]
319    #[inline(always)]
320    pub fn is_disable(&self) -> bool {
321        *self == OEOVER_A::DISABLE
322    }
323    #[doc = "enable output"]
324    #[inline(always)]
325    pub fn is_enable(&self) -> bool {
326        *self == OEOVER_A::ENABLE
327    }
328}
329#[doc = "Field `OEOVER` writer - "]
330pub type OEOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OEOVER_A>;
331impl<'a, REG> OEOVER_W<'a, REG>
332where
333    REG: crate::Writable + crate::RegisterSpec,
334    REG::Ux: From<u8>,
335{
336    #[doc = "drive output enable from peripheral signal selected by funcsel"]
337    #[inline(always)]
338    pub fn normal(self) -> &'a mut crate::W<REG> {
339        self.variant(OEOVER_A::NORMAL)
340    }
341    #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"]
342    #[inline(always)]
343    pub fn invert(self) -> &'a mut crate::W<REG> {
344        self.variant(OEOVER_A::INVERT)
345    }
346    #[doc = "disable output"]
347    #[inline(always)]
348    pub fn disable(self) -> &'a mut crate::W<REG> {
349        self.variant(OEOVER_A::DISABLE)
350    }
351    #[doc = "enable output"]
352    #[inline(always)]
353    pub fn enable(self) -> &'a mut crate::W<REG> {
354        self.variant(OEOVER_A::ENABLE)
355    }
356}
357#[doc = "Field `INOVER` reader - "]
358pub type INOVER_R = crate::FieldReader<INOVER_A>;
359#[doc = "  
360
361Value on reset: 0"]
362#[derive(Clone, Copy, Debug, PartialEq, Eq)]
363#[repr(u8)]
364pub enum INOVER_A {
365    #[doc = "0: don't invert the peri input"]
366    NORMAL = 0,
367    #[doc = "1: invert the peri input"]
368    INVERT = 1,
369    #[doc = "2: drive peri input low"]
370    LOW = 2,
371    #[doc = "3: drive peri input high"]
372    HIGH = 3,
373}
374impl From<INOVER_A> for u8 {
375    #[inline(always)]
376    fn from(variant: INOVER_A) -> Self {
377        variant as _
378    }
379}
380impl crate::FieldSpec for INOVER_A {
381    type Ux = u8;
382}
383impl INOVER_R {
384    #[doc = "Get enumerated values variant"]
385    #[inline(always)]
386    pub const fn variant(&self) -> INOVER_A {
387        match self.bits {
388            0 => INOVER_A::NORMAL,
389            1 => INOVER_A::INVERT,
390            2 => INOVER_A::LOW,
391            3 => INOVER_A::HIGH,
392            _ => unreachable!(),
393        }
394    }
395    #[doc = "don't invert the peri input"]
396    #[inline(always)]
397    pub fn is_normal(&self) -> bool {
398        *self == INOVER_A::NORMAL
399    }
400    #[doc = "invert the peri input"]
401    #[inline(always)]
402    pub fn is_invert(&self) -> bool {
403        *self == INOVER_A::INVERT
404    }
405    #[doc = "drive peri input low"]
406    #[inline(always)]
407    pub fn is_low(&self) -> bool {
408        *self == INOVER_A::LOW
409    }
410    #[doc = "drive peri input high"]
411    #[inline(always)]
412    pub fn is_high(&self) -> bool {
413        *self == INOVER_A::HIGH
414    }
415}
416#[doc = "Field `INOVER` writer - "]
417pub type INOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INOVER_A>;
418impl<'a, REG> INOVER_W<'a, REG>
419where
420    REG: crate::Writable + crate::RegisterSpec,
421    REG::Ux: From<u8>,
422{
423    #[doc = "don't invert the peri input"]
424    #[inline(always)]
425    pub fn normal(self) -> &'a mut crate::W<REG> {
426        self.variant(INOVER_A::NORMAL)
427    }
428    #[doc = "invert the peri input"]
429    #[inline(always)]
430    pub fn invert(self) -> &'a mut crate::W<REG> {
431        self.variant(INOVER_A::INVERT)
432    }
433    #[doc = "drive peri input low"]
434    #[inline(always)]
435    pub fn low(self) -> &'a mut crate::W<REG> {
436        self.variant(INOVER_A::LOW)
437    }
438    #[doc = "drive peri input high"]
439    #[inline(always)]
440    pub fn high(self) -> &'a mut crate::W<REG> {
441        self.variant(INOVER_A::HIGH)
442    }
443}
444#[doc = "Field `IRQOVER` reader - "]
445pub type IRQOVER_R = crate::FieldReader<IRQOVER_A>;
446#[doc = "  
447
448Value on reset: 0"]
449#[derive(Clone, Copy, Debug, PartialEq, Eq)]
450#[repr(u8)]
451pub enum IRQOVER_A {
452    #[doc = "0: don't invert the interrupt"]
453    NORMAL = 0,
454    #[doc = "1: invert the interrupt"]
455    INVERT = 1,
456    #[doc = "2: drive interrupt low"]
457    LOW = 2,
458    #[doc = "3: drive interrupt high"]
459    HIGH = 3,
460}
461impl From<IRQOVER_A> for u8 {
462    #[inline(always)]
463    fn from(variant: IRQOVER_A) -> Self {
464        variant as _
465    }
466}
467impl crate::FieldSpec for IRQOVER_A {
468    type Ux = u8;
469}
470impl IRQOVER_R {
471    #[doc = "Get enumerated values variant"]
472    #[inline(always)]
473    pub const fn variant(&self) -> IRQOVER_A {
474        match self.bits {
475            0 => IRQOVER_A::NORMAL,
476            1 => IRQOVER_A::INVERT,
477            2 => IRQOVER_A::LOW,
478            3 => IRQOVER_A::HIGH,
479            _ => unreachable!(),
480        }
481    }
482    #[doc = "don't invert the interrupt"]
483    #[inline(always)]
484    pub fn is_normal(&self) -> bool {
485        *self == IRQOVER_A::NORMAL
486    }
487    #[doc = "invert the interrupt"]
488    #[inline(always)]
489    pub fn is_invert(&self) -> bool {
490        *self == IRQOVER_A::INVERT
491    }
492    #[doc = "drive interrupt low"]
493    #[inline(always)]
494    pub fn is_low(&self) -> bool {
495        *self == IRQOVER_A::LOW
496    }
497    #[doc = "drive interrupt high"]
498    #[inline(always)]
499    pub fn is_high(&self) -> bool {
500        *self == IRQOVER_A::HIGH
501    }
502}
503#[doc = "Field `IRQOVER` writer - "]
504pub type IRQOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IRQOVER_A>;
505impl<'a, REG> IRQOVER_W<'a, REG>
506where
507    REG: crate::Writable + crate::RegisterSpec,
508    REG::Ux: From<u8>,
509{
510    #[doc = "don't invert the interrupt"]
511    #[inline(always)]
512    pub fn normal(self) -> &'a mut crate::W<REG> {
513        self.variant(IRQOVER_A::NORMAL)
514    }
515    #[doc = "invert the interrupt"]
516    #[inline(always)]
517    pub fn invert(self) -> &'a mut crate::W<REG> {
518        self.variant(IRQOVER_A::INVERT)
519    }
520    #[doc = "drive interrupt low"]
521    #[inline(always)]
522    pub fn low(self) -> &'a mut crate::W<REG> {
523        self.variant(IRQOVER_A::LOW)
524    }
525    #[doc = "drive interrupt high"]
526    #[inline(always)]
527    pub fn high(self) -> &'a mut crate::W<REG> {
528        self.variant(IRQOVER_A::HIGH)
529    }
530}
531impl R {
532    #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."]
533    #[inline(always)]
534    pub fn funcsel(&self) -> FUNCSEL_R {
535        FUNCSEL_R::new((self.bits & 0x1f) as u8)
536    }
537    #[doc = "Bits 8:9"]
538    #[inline(always)]
539    pub fn outover(&self) -> OUTOVER_R {
540        OUTOVER_R::new(((self.bits >> 8) & 3) as u8)
541    }
542    #[doc = "Bits 12:13"]
543    #[inline(always)]
544    pub fn oeover(&self) -> OEOVER_R {
545        OEOVER_R::new(((self.bits >> 12) & 3) as u8)
546    }
547    #[doc = "Bits 16:17"]
548    #[inline(always)]
549    pub fn inover(&self) -> INOVER_R {
550        INOVER_R::new(((self.bits >> 16) & 3) as u8)
551    }
552    #[doc = "Bits 28:29"]
553    #[inline(always)]
554    pub fn irqover(&self) -> IRQOVER_R {
555        IRQOVER_R::new(((self.bits >> 28) & 3) as u8)
556    }
557}
558impl W {
559    #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."]
560    #[inline(always)]
561    #[must_use]
562    pub fn funcsel(&mut self) -> FUNCSEL_W<GPIO_CTRL_SPEC> {
563        FUNCSEL_W::new(self, 0)
564    }
565    #[doc = "Bits 8:9"]
566    #[inline(always)]
567    #[must_use]
568    pub fn outover(&mut self) -> OUTOVER_W<GPIO_CTRL_SPEC> {
569        OUTOVER_W::new(self, 8)
570    }
571    #[doc = "Bits 12:13"]
572    #[inline(always)]
573    #[must_use]
574    pub fn oeover(&mut self) -> OEOVER_W<GPIO_CTRL_SPEC> {
575        OEOVER_W::new(self, 12)
576    }
577    #[doc = "Bits 16:17"]
578    #[inline(always)]
579    #[must_use]
580    pub fn inover(&mut self) -> INOVER_W<GPIO_CTRL_SPEC> {
581        INOVER_W::new(self, 16)
582    }
583    #[doc = "Bits 28:29"]
584    #[inline(always)]
585    #[must_use]
586    pub fn irqover(&mut self) -> IRQOVER_W<GPIO_CTRL_SPEC> {
587        IRQOVER_W::new(self, 28)
588    }
589    #[doc = r" Writes raw bits to the register."]
590    #[doc = r""]
591    #[doc = r" # Safety"]
592    #[doc = r""]
593    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
594    #[inline(always)]
595    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
596        self.bits = bits;
597        self
598    }
599}
600#[doc = "GPIO control including function select and overrides.  
601
602You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
603pub struct GPIO_CTRL_SPEC;
604impl crate::RegisterSpec for GPIO_CTRL_SPEC {
605    type Ux = u32;
606}
607#[doc = "`read()` method returns [`gpio_ctrl::R`](R) reader structure"]
608impl crate::Readable for GPIO_CTRL_SPEC {}
609#[doc = "`write(|w| ..)` method takes [`gpio_ctrl::W`](W) writer structure"]
610impl crate::Writable for GPIO_CTRL_SPEC {
611    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
612    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
613}
614#[doc = "`reset()` method sets GPIO_CTRL to value 0x1f"]
615impl crate::Resettable for GPIO_CTRL_SPEC {
616    const RESET_VALUE: u32 = 0x1f;
617}
rp2040_pac/io_bank0/gpio/gpio_ctrl.rs

rp2040_pac/io_bank0/gpio/
gpio_ctrl.rs
