rp2040_pac/
timer.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    timehw: TIMEHW,
5    timelw: TIMELW,
6    timehr: TIMEHR,
7    timelr: TIMELR,
8    alarm0: ALARM0,
9    alarm1: ALARM1,
10    alarm2: ALARM2,
11    alarm3: ALARM3,
12    armed: ARMED,
13    timerawh: TIMERAWH,
14    timerawl: TIMERAWL,
15    dbgpause: DBGPAUSE,
16    pause: PAUSE,
17    intr: INTR,
18    inte: INTE,
19    intf: INTF,
20    ints: INTS,
21}
22impl RegisterBlock {
23    #[doc = "0x00 - Write to bits 63:32 of time  
24 always write timelw before timehw"]
25    #[inline(always)]
26    pub const fn timehw(&self) -> &TIMEHW {
27        &self.timehw
28    }
29    #[doc = "0x04 - Write to bits 31:0 of time  
30 writes do not get copied to time until timehw is written"]
31    #[inline(always)]
32    pub const fn timelw(&self) -> &TIMELW {
33        &self.timelw
34    }
35    #[doc = "0x08 - Read from bits 63:32 of time  
36 always read timelr before timehr"]
37    #[inline(always)]
38    pub const fn timehr(&self) -> &TIMEHR {
39        &self.timehr
40    }
41    #[doc = "0x0c - Read from bits 31:0 of time"]
42    #[inline(always)]
43    pub const fn timelr(&self) -> &TIMELR {
44        &self.timelr
45    }
46    #[doc = "0x10 - Arm alarm 0, and configure the time it will fire.  
47 Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.  
48 The alarm will disarm itself once it fires, and can  
49 be disarmed early using the ARMED status register."]
50    #[inline(always)]
51    pub const fn alarm0(&self) -> &ALARM0 {
52        &self.alarm0
53    }
54    #[doc = "0x14 - Arm alarm 1, and configure the time it will fire.  
55 Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.  
56 The alarm will disarm itself once it fires, and can  
57 be disarmed early using the ARMED status register."]
58    #[inline(always)]
59    pub const fn alarm1(&self) -> &ALARM1 {
60        &self.alarm1
61    }
62    #[doc = "0x18 - Arm alarm 2, and configure the time it will fire.  
63 Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.  
64 The alarm will disarm itself once it fires, and can  
65 be disarmed early using the ARMED status register."]
66    #[inline(always)]
67    pub const fn alarm2(&self) -> &ALARM2 {
68        &self.alarm2
69    }
70    #[doc = "0x1c - Arm alarm 3, and configure the time it will fire.  
71 Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.  
72 The alarm will disarm itself once it fires, and can  
73 be disarmed early using the ARMED status register."]
74    #[inline(always)]
75    pub const fn alarm3(&self) -> &ALARM3 {
76        &self.alarm3
77    }
78    #[doc = "0x20 - Indicates the armed/disarmed status of each alarm.  
79 A write to the corresponding ALARMx register arms the alarm.  
80 Alarms automatically disarm upon firing, but writing ones here  
81 will disarm immediately without waiting to fire."]
82    #[inline(always)]
83    pub const fn armed(&self) -> &ARMED {
84        &self.armed
85    }
86    #[doc = "0x24 - Raw read from bits 63:32 of time (no side effects)"]
87    #[inline(always)]
88    pub const fn timerawh(&self) -> &TIMERAWH {
89        &self.timerawh
90    }
91    #[doc = "0x28 - Raw read from bits 31:0 of time (no side effects)"]
92    #[inline(always)]
93    pub const fn timerawl(&self) -> &TIMERAWL {
94        &self.timerawl
95    }
96    #[doc = "0x2c - Set bits high to enable pause when the corresponding debug ports are active"]
97    #[inline(always)]
98    pub const fn dbgpause(&self) -> &DBGPAUSE {
99        &self.dbgpause
100    }
101    #[doc = "0x30 - Set high to pause the timer"]
102    #[inline(always)]
103    pub const fn pause(&self) -> &PAUSE {
104        &self.pause
105    }
106    #[doc = "0x34 - Raw Interrupts"]
107    #[inline(always)]
108    pub const fn intr(&self) -> &INTR {
109        &self.intr
110    }
111    #[doc = "0x38 - Interrupt Enable"]
112    #[inline(always)]
113    pub const fn inte(&self) -> &INTE {
114        &self.inte
115    }
116    #[doc = "0x3c - Interrupt Force"]
117    #[inline(always)]
118    pub const fn intf(&self) -> &INTF {
119        &self.intf
120    }
121    #[doc = "0x40 - Interrupt status after masking &amp; forcing"]
122    #[inline(always)]
123    pub const fn ints(&self) -> &INTS {
124        &self.ints
125    }
126}
127#[doc = "TIMEHW (w) register accessor: Write to bits 63:32 of time  
128 always write timelw before timehw  
129
130You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
131
132For information about available fields see [`mod@timehw`]
133module"]
134pub type TIMEHW = crate::Reg<timehw::TIMEHW_SPEC>;
135#[doc = "Write to bits 63:32 of time  
136 always write timelw before timehw"]
137pub mod timehw;
138#[doc = "TIMELW (w) register accessor: Write to bits 31:0 of time  
139 writes do not get copied to time until timehw is written  
140
141You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
142
143For information about available fields see [`mod@timelw`]
144module"]
145pub type TIMELW = crate::Reg<timelw::TIMELW_SPEC>;
146#[doc = "Write to bits 31:0 of time  
147 writes do not get copied to time until timehw is written"]
148pub mod timelw;
149#[doc = "TIMEHR (r) register accessor: Read from bits 63:32 of time  
150 always read timelr before timehr  
151
152You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
153
154For information about available fields see [`mod@timehr`]
155module"]
156pub type TIMEHR = crate::Reg<timehr::TIMEHR_SPEC>;
157#[doc = "Read from bits 63:32 of time  
158 always read timelr before timehr"]
159pub mod timehr;
160#[doc = "TIMELR (r) register accessor: Read from bits 31:0 of time  
161
162You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
163
164For information about available fields see [`mod@timelr`]
165module"]
166pub type TIMELR = crate::Reg<timelr::TIMELR_SPEC>;
167#[doc = "Read from bits 31:0 of time"]
168pub mod timelr;
169#[doc = "ALARM0 (rw) register accessor: Arm alarm 0, and configure the time it will fire.  
170 Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.  
171 The alarm will disarm itself once it fires, and can  
172 be disarmed early using the ARMED status register.  
173
174You can [`read`](crate::generic::Reg::read) this register and get [`alarm0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
175
176For information about available fields see [`mod@alarm0`]
177module"]
178pub type ALARM0 = crate::Reg<alarm0::ALARM0_SPEC>;
179#[doc = "Arm alarm 0, and configure the time it will fire.  
180 Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.  
181 The alarm will disarm itself once it fires, and can  
182 be disarmed early using the ARMED status register."]
183pub mod alarm0;
184#[doc = "ALARM1 (rw) register accessor: Arm alarm 1, and configure the time it will fire.  
185 Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.  
186 The alarm will disarm itself once it fires, and can  
187 be disarmed early using the ARMED status register.  
188
189You can [`read`](crate::generic::Reg::read) this register and get [`alarm1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
190
191For information about available fields see [`mod@alarm1`]
192module"]
193pub type ALARM1 = crate::Reg<alarm1::ALARM1_SPEC>;
194#[doc = "Arm alarm 1, and configure the time it will fire.  
195 Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.  
196 The alarm will disarm itself once it fires, and can  
197 be disarmed early using the ARMED status register."]
198pub mod alarm1;
199#[doc = "ALARM2 (rw) register accessor: Arm alarm 2, and configure the time it will fire.  
200 Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.  
201 The alarm will disarm itself once it fires, and can  
202 be disarmed early using the ARMED status register.  
203
204You can [`read`](crate::generic::Reg::read) this register and get [`alarm2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
205
206For information about available fields see [`mod@alarm2`]
207module"]
208pub type ALARM2 = crate::Reg<alarm2::ALARM2_SPEC>;
209#[doc = "Arm alarm 2, and configure the time it will fire.  
210 Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.  
211 The alarm will disarm itself once it fires, and can  
212 be disarmed early using the ARMED status register."]
213pub mod alarm2;
214#[doc = "ALARM3 (rw) register accessor: Arm alarm 3, and configure the time it will fire.  
215 Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.  
216 The alarm will disarm itself once it fires, and can  
217 be disarmed early using the ARMED status register.  
218
219You can [`read`](crate::generic::Reg::read) this register and get [`alarm3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
220
221For information about available fields see [`mod@alarm3`]
222module"]
223pub type ALARM3 = crate::Reg<alarm3::ALARM3_SPEC>;
224#[doc = "Arm alarm 3, and configure the time it will fire.  
225 Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.  
226 The alarm will disarm itself once it fires, and can  
227 be disarmed early using the ARMED status register."]
228pub mod alarm3;
229#[doc = "ARMED (rw) register accessor: Indicates the armed/disarmed status of each alarm.  
230 A write to the corresponding ALARMx register arms the alarm.  
231 Alarms automatically disarm upon firing, but writing ones here  
232 will disarm immediately without waiting to fire.  
233
234You can [`read`](crate::generic::Reg::read) this register and get [`armed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`armed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
235
236For information about available fields see [`mod@armed`]
237module"]
238pub type ARMED = crate::Reg<armed::ARMED_SPEC>;
239#[doc = "Indicates the armed/disarmed status of each alarm.  
240 A write to the corresponding ALARMx register arms the alarm.  
241 Alarms automatically disarm upon firing, but writing ones here  
242 will disarm immediately without waiting to fire."]
243pub mod armed;
244#[doc = "TIMERAWH (r) register accessor: Raw read from bits 63:32 of time (no side effects)  
245
246You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
247
248For information about available fields see [`mod@timerawh`]
249module"]
250pub type TIMERAWH = crate::Reg<timerawh::TIMERAWH_SPEC>;
251#[doc = "Raw read from bits 63:32 of time (no side effects)"]
252pub mod timerawh;
253#[doc = "TIMERAWL (r) register accessor: Raw read from bits 31:0 of time (no side effects)  
254
255You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
256
257For information about available fields see [`mod@timerawl`]
258module"]
259pub type TIMERAWL = crate::Reg<timerawl::TIMERAWL_SPEC>;
260#[doc = "Raw read from bits 31:0 of time (no side effects)"]
261pub mod timerawl;
262#[doc = "DBGPAUSE (rw) register accessor: Set bits high to enable pause when the corresponding debug ports are active  
263
264You can [`read`](crate::generic::Reg::read) this register and get [`dbgpause::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgpause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
265
266For information about available fields see [`mod@dbgpause`]
267module"]
268pub type DBGPAUSE = crate::Reg<dbgpause::DBGPAUSE_SPEC>;
269#[doc = "Set bits high to enable pause when the corresponding debug ports are active"]
270pub mod dbgpause;
271#[doc = "PAUSE (rw) register accessor: Set high to pause the timer  
272
273You can [`read`](crate::generic::Reg::read) this register and get [`pause::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
274
275For information about available fields see [`mod@pause`]
276module"]
277pub type PAUSE = crate::Reg<pause::PAUSE_SPEC>;
278#[doc = "Set high to pause the timer"]
279pub mod pause;
280#[doc = "INTR (rw) register accessor: Raw Interrupts  
281
282You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
283
284For information about available fields see [`mod@intr`]
285module"]
286pub type INTR = crate::Reg<intr::INTR_SPEC>;
287#[doc = "Raw Interrupts"]
288pub mod intr;
289#[doc = "INTE (rw) register accessor: Interrupt Enable  
290
291You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
292
293For information about available fields see [`mod@inte`]
294module"]
295pub type INTE = crate::Reg<inte::INTE_SPEC>;
296#[doc = "Interrupt Enable"]
297pub mod inte;
298#[doc = "INTF (rw) register accessor: Interrupt Force  
299
300You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
301
302For information about available fields see [`mod@intf`]
303module"]
304pub type INTF = crate::Reg<intf::INTF_SPEC>;
305#[doc = "Interrupt Force"]
306pub mod intf;
307#[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
308
309You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
310
311For information about available fields see [`mod@ints`]
312module"]
313pub type INTS = crate::Reg<ints::INTS_SPEC>;
314#[doc = "Interrupt status after masking &amp; forcing"]
315pub mod ints;
rp2040_pac/timer.rs

rp2040_pac/
timer.rs
