rp2040_pac/
pwm.rs

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1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    ch: [CH; 8],
5    en: EN,
6    intr: INTR,
7    inte: INTE,
8    intf: INTF,
9    ints: INTS,
10}
11impl RegisterBlock {
12    #[doc = "0x00..0xa0 - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"]
13    #[inline(always)]
14    pub const fn ch(&self, n: usize) -> &CH {
15        &self.ch[n]
16    }
17    #[doc = "Iterator for array of:"]
18    #[doc = "0x00..0xa0 - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"]
19    #[inline(always)]
20    pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
21        self.ch.iter()
22    }
23    #[doc = "0xa0 - This register aliases the CSR_EN bits for all channels.  
24 Writing to this register allows multiple channels to be enabled  
25 or disabled simultaneously, so they can run in perfect sync.  
26 For each channel, there is only one physical EN register bit,  
27 which can be accessed through here or CHx_CSR."]
28    #[inline(always)]
29    pub const fn en(&self) -> &EN {
30        &self.en
31    }
32    #[doc = "0xa4 - Raw Interrupts"]
33    #[inline(always)]
34    pub const fn intr(&self) -> &INTR {
35        &self.intr
36    }
37    #[doc = "0xa8 - Interrupt Enable"]
38    #[inline(always)]
39    pub const fn inte(&self) -> &INTE {
40        &self.inte
41    }
42    #[doc = "0xac - Interrupt Force"]
43    #[inline(always)]
44    pub const fn intf(&self) -> &INTF {
45        &self.intf
46    }
47    #[doc = "0xb0 - Interrupt status after masking &amp; forcing"]
48    #[inline(always)]
49    pub const fn ints(&self) -> &INTS {
50        &self.ints
51    }
52}
53#[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"]
54pub use self::ch::CH;
55#[doc = r"Cluster"]
56#[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"]
57pub mod ch;
58#[doc = "EN (rw) register accessor: This register aliases the CSR_EN bits for all channels.  
59 Writing to this register allows multiple channels to be enabled  
60 or disabled simultaneously, so they can run in perfect sync.  
61 For each channel, there is only one physical EN register bit,  
62 which can be accessed through here or CHx_CSR.  
63
64You can [`read`](crate::generic::Reg::read) this register and get [`en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
65
66For information about available fields see [`mod@en`]
67module"]
68pub type EN = crate::Reg<en::EN_SPEC>;
69#[doc = "This register aliases the CSR_EN bits for all channels.  
70 Writing to this register allows multiple channels to be enabled  
71 or disabled simultaneously, so they can run in perfect sync.  
72 For each channel, there is only one physical EN register bit,  
73 which can be accessed through here or CHx_CSR."]
74pub mod en;
75#[doc = "INTR (rw) register accessor: Raw Interrupts  
76
77You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
78
79For information about available fields see [`mod@intr`]
80module"]
81pub type INTR = crate::Reg<intr::INTR_SPEC>;
82#[doc = "Raw Interrupts"]
83pub mod intr;
84#[doc = "INTE (rw) register accessor: Interrupt Enable  
85
86You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
87
88For information about available fields see [`mod@inte`]
89module"]
90pub type INTE = crate::Reg<inte::INTE_SPEC>;
91#[doc = "Interrupt Enable"]
92pub mod inte;
93#[doc = "INTF (rw) register accessor: Interrupt Force  
94
95You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
96
97For information about available fields see [`mod@intf`]
98module"]
99pub type INTF = crate::Reg<intf::INTF_SPEC>;
100#[doc = "Interrupt Force"]
101pub mod intf;
102#[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
103
104You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
105
106For information about available fields see [`mod@ints`]
107module"]
108pub type INTS = crate::Reg<ints::INTS_SPEC>;
109#[doc = "Interrupt status after masking &amp; forcing"]
110pub mod ints;
rp2040_pac/pwm.rs

rp2040_pac/
pwm.rs
