1#[doc = "DMA"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Control Register"]
5 pub CR: crate::RWRegister<u32>,
6 #[doc = "Error Status Register"]
7 pub ES: crate::RORegister<u32>,
8 _reserved0: [u8; 0x04],
9 #[doc = "Enable Request Register"]
10 pub ERQ: crate::RWRegister<u32>,
11 _reserved1: [u8; 0x04],
12 #[doc = "Enable Error Interrupt Register"]
13 pub EEI: crate::RWRegister<u32>,
14 #[doc = "Clear Enable Error Interrupt Register"]
15 pub CEEI: crate::RWRegister<u8>,
16 #[doc = "Set Enable Error Interrupt Register"]
17 pub SEEI: crate::RWRegister<u8>,
18 #[doc = "Clear Enable Request Register"]
19 pub CERQ: crate::RWRegister<u8>,
20 #[doc = "Set Enable Request Register"]
21 pub SERQ: crate::RWRegister<u8>,
22 #[doc = "Clear DONE Status Bit Register"]
23 pub CDNE: crate::RWRegister<u8>,
24 #[doc = "Set START Bit Register"]
25 pub SSRT: crate::RWRegister<u8>,
26 #[doc = "Clear Error Register"]
27 pub CERR: crate::RWRegister<u8>,
28 #[doc = "Clear Interrupt Request Register"]
29 pub CINT: crate::RWRegister<u8>,
30 _reserved2: [u8; 0x04],
31 #[doc = "Interrupt Request Register"]
32 pub INT: crate::RWRegister<u32>,
33 _reserved3: [u8; 0x04],
34 #[doc = "Error Register"]
35 pub ERR: crate::RWRegister<u32>,
36 _reserved4: [u8; 0x04],
37 #[doc = "Hardware Request Status Register"]
38 pub HRS: crate::RORegister<u32>,
39 _reserved5: [u8; 0x0c],
40 #[doc = "Enable Asynchronous Request in Stop Register"]
41 pub EARS: crate::RWRegister<u32>,
42 _reserved6: [u8; 0xb8],
43 #[doc = "Channel Priority Register"]
44 pub DCHPRI3: crate::RWRegister<u8>,
45 #[doc = "Channel Priority Register"]
46 pub DCHPRI2: crate::RWRegister<u8>,
47 #[doc = "Channel Priority Register"]
48 pub DCHPRI1: crate::RWRegister<u8>,
49 #[doc = "Channel Priority Register"]
50 pub DCHPRI0: crate::RWRegister<u8>,
51 #[doc = "Channel Priority Register"]
52 pub DCHPRI7: crate::RWRegister<u8>,
53 #[doc = "Channel Priority Register"]
54 pub DCHPRI6: crate::RWRegister<u8>,
55 #[doc = "Channel Priority Register"]
56 pub DCHPRI5: crate::RWRegister<u8>,
57 #[doc = "Channel Priority Register"]
58 pub DCHPRI4: crate::RWRegister<u8>,
59 #[doc = "Channel Priority Register"]
60 pub DCHPRI11: crate::RWRegister<u8>,
61 #[doc = "Channel Priority Register"]
62 pub DCHPRI10: crate::RWRegister<u8>,
63 #[doc = "Channel Priority Register"]
64 pub DCHPRI9: crate::RWRegister<u8>,
65 #[doc = "Channel Priority Register"]
66 pub DCHPRI8: crate::RWRegister<u8>,
67 #[doc = "Channel Priority Register"]
68 pub DCHPRI15: crate::RWRegister<u8>,
69 #[doc = "Channel Priority Register"]
70 pub DCHPRI14: crate::RWRegister<u8>,
71 #[doc = "Channel Priority Register"]
72 pub DCHPRI13: crate::RWRegister<u8>,
73 #[doc = "Channel Priority Register"]
74 pub DCHPRI12: crate::RWRegister<u8>,
75 _reserved7: [u8; 0x0ef0],
76 #[doc = "Cluster TCD%s, containing TCD*_SADDR, TCD*_SOFF, TCD*_ATTR, TCD*_NBYTES_MLNO, TCD*_NBYTES_MLOFFNO, TCD*_NBYTES_MLOFFYES, TCD*_SLAST, TCD*_DADDR, TCD*_DOFF, TCD*_CITER_ELINKNO, TCD*_CITER_ELINKYES, TCD*_DLASTSGA, TCD*_CSR, TCD*_BITER_ELINKNO, TCD*_BITER_ELINKYES"]
77 pub TCD: [tcd::RegisterBlock; 16usize],
78}
79#[doc = "Control Register"]
80pub mod CR {
81 #[doc = "Enable Debug"]
82 pub mod EDBG {
83 pub const offset: u32 = 1;
84 pub const mask: u32 = 0x01 << offset;
85 pub mod R {}
86 pub mod W {}
87 pub mod RW {
88 #[doc = "When in debug mode, the DMA continues to operate."]
89 pub const EDBG_0: u32 = 0;
90 #[doc = "When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared."]
91 pub const EDBG_1: u32 = 0x01;
92 }
93 }
94 #[doc = "Enable Round Robin Channel Arbitration"]
95 pub mod ERCA {
96 pub const offset: u32 = 2;
97 pub const mask: u32 = 0x01 << offset;
98 pub mod R {}
99 pub mod W {}
100 pub mod RW {
101 #[doc = "Fixed priority arbitration is used for channel selection ."]
102 pub const ERCA_0: u32 = 0;
103 #[doc = "Round robin arbitration is used for channel selection ."]
104 pub const ERCA_1: u32 = 0x01;
105 }
106 }
107 #[doc = "Halt On Error"]
108 pub mod HOE {
109 pub const offset: u32 = 4;
110 pub const mask: u32 = 0x01 << offset;
111 pub mod R {}
112 pub mod W {}
113 pub mod RW {
114 #[doc = "Normal operation"]
115 pub const HOE_0: u32 = 0;
116 #[doc = "Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared."]
117 pub const HOE_1: u32 = 0x01;
118 }
119 }
120 #[doc = "Halt DMA Operations"]
121 pub mod HALT {
122 pub const offset: u32 = 5;
123 pub const mask: u32 = 0x01 << offset;
124 pub mod R {}
125 pub mod W {}
126 pub mod RW {
127 #[doc = "Normal operation"]
128 pub const HALT_0: u32 = 0;
129 #[doc = "Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared."]
130 pub const HALT_1: u32 = 0x01;
131 }
132 }
133 #[doc = "Continuous Link Mode"]
134 pub mod CLM {
135 pub const offset: u32 = 6;
136 pub const mask: u32 = 0x01 << offset;
137 pub mod R {}
138 pub mod W {}
139 pub mod RW {
140 #[doc = "A minor loop channel link made to itself goes through channel arbitration before being activated again."]
141 pub const CLM_0: u32 = 0;
142 #[doc = "A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop."]
143 pub const CLM_1: u32 = 0x01;
144 }
145 }
146 #[doc = "Enable Minor Loop Mapping"]
147 pub mod EMLM {
148 pub const offset: u32 = 7;
149 pub const mask: u32 = 0x01 << offset;
150 pub mod R {}
151 pub mod W {}
152 pub mod RW {
153 #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."]
154 pub const EMLM_0: u32 = 0;
155 #[doc = "Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled."]
156 pub const EMLM_1: u32 = 0x01;
157 }
158 }
159 #[doc = "Error Cancel Transfer"]
160 pub mod ECX {
161 pub const offset: u32 = 16;
162 pub const mask: u32 = 0x01 << offset;
163 pub mod R {}
164 pub mod W {}
165 pub mod RW {
166 #[doc = "Normal operation"]
167 pub const ECX_0: u32 = 0;
168 #[doc = "Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt."]
169 pub const ECX_1: u32 = 0x01;
170 }
171 }
172 #[doc = "Cancel Transfer"]
173 pub mod CX {
174 pub const offset: u32 = 17;
175 pub const mask: u32 = 0x01 << offset;
176 pub mod R {}
177 pub mod W {}
178 pub mod RW {
179 #[doc = "Normal operation"]
180 pub const CX_0: u32 = 0;
181 #[doc = "Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed."]
182 pub const CX_1: u32 = 0x01;
183 }
184 }
185 #[doc = "DMA Active Status"]
186 pub mod ACTIVE {
187 pub const offset: u32 = 31;
188 pub const mask: u32 = 0x01 << offset;
189 pub mod R {}
190 pub mod W {}
191 pub mod RW {
192 #[doc = "eDMA is idle."]
193 pub const ACTIVE_0: u32 = 0;
194 #[doc = "eDMA is executing a channel."]
195 pub const ACTIVE_1: u32 = 0x01;
196 }
197 }
198}
199#[doc = "Error Status Register"]
200pub mod ES {
201 #[doc = "Destination Bus Error"]
202 pub mod DBE {
203 pub const offset: u32 = 0;
204 pub const mask: u32 = 0x01 << offset;
205 pub mod R {}
206 pub mod W {}
207 pub mod RW {
208 #[doc = "No destination bus error"]
209 pub const DBE_0: u32 = 0;
210 #[doc = "The last recorded error was a bus error on a destination write"]
211 pub const DBE_1: u32 = 0x01;
212 }
213 }
214 #[doc = "Source Bus Error"]
215 pub mod SBE {
216 pub const offset: u32 = 1;
217 pub const mask: u32 = 0x01 << offset;
218 pub mod R {}
219 pub mod W {}
220 pub mod RW {
221 #[doc = "No source bus error"]
222 pub const SBE_0: u32 = 0;
223 #[doc = "The last recorded error was a bus error on a source read"]
224 pub const SBE_1: u32 = 0x01;
225 }
226 }
227 #[doc = "Scatter/Gather Configuration Error"]
228 pub mod SGE {
229 pub const offset: u32 = 2;
230 pub const mask: u32 = 0x01 << offset;
231 pub mod R {}
232 pub mod W {}
233 pub mod RW {
234 #[doc = "No scatter/gather configuration error"]
235 pub const SGE_0: u32 = 0;
236 #[doc = "The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR\\[ESG\\] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary."]
237 pub const SGE_1: u32 = 0x01;
238 }
239 }
240 #[doc = "NBYTES/CITER Configuration Error"]
241 pub mod NCE {
242 pub const offset: u32 = 3;
243 pub const mask: u32 = 0x01 << offset;
244 pub mod R {}
245 pub mod W {}
246 pub mod RW {
247 #[doc = "No NBYTES/CITER configuration error"]
248 pub const NCE_0: u32 = 0;
249 #[doc = "The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR\\[SSIZE\\] and TCDn_ATTR\\[DSIZE\\], or TCDn_CITER\\[CITER\\] is equal to zero, or TCDn_CITER\\[ELINK\\] is not equal to TCDn_BITER\\[ELINK\\]"]
250 pub const NCE_1: u32 = 0x01;
251 }
252 }
253 #[doc = "Destination Offset Error"]
254 pub mod DOE {
255 pub const offset: u32 = 4;
256 pub const mask: u32 = 0x01 << offset;
257 pub mod R {}
258 pub mod W {}
259 pub mod RW {
260 #[doc = "No destination offset configuration error"]
261 pub const DOE_0: u32 = 0;
262 #[doc = "The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR\\[DSIZE\\]."]
263 pub const DOE_1: u32 = 0x01;
264 }
265 }
266 #[doc = "Destination Address Error"]
267 pub mod DAE {
268 pub const offset: u32 = 5;
269 pub const mask: u32 = 0x01 << offset;
270 pub mod R {}
271 pub mod W {}
272 pub mod RW {
273 #[doc = "No destination address configuration error"]
274 pub const DAE_0: u32 = 0;
275 #[doc = "The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR\\[DSIZE\\]."]
276 pub const DAE_1: u32 = 0x01;
277 }
278 }
279 #[doc = "Source Offset Error"]
280 pub mod SOE {
281 pub const offset: u32 = 6;
282 pub const mask: u32 = 0x01 << offset;
283 pub mod R {}
284 pub mod W {}
285 pub mod RW {
286 #[doc = "No source offset configuration error"]
287 pub const SOE_0: u32 = 0;
288 #[doc = "The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR\\[SSIZE\\]."]
289 pub const SOE_1: u32 = 0x01;
290 }
291 }
292 #[doc = "Source Address Error"]
293 pub mod SAE {
294 pub const offset: u32 = 7;
295 pub const mask: u32 = 0x01 << offset;
296 pub mod R {}
297 pub mod W {}
298 pub mod RW {
299 #[doc = "No source address configuration error."]
300 pub const SAE_0: u32 = 0;
301 #[doc = "The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR\\[SSIZE\\]."]
302 pub const SAE_1: u32 = 0x01;
303 }
304 }
305 #[doc = "Error Channel Number or Canceled Channel Number"]
306 pub mod ERRCHN {
307 pub const offset: u32 = 8;
308 pub const mask: u32 = 0x0f << offset;
309 pub mod R {}
310 pub mod W {}
311 pub mod RW {}
312 }
313 #[doc = "Channel Priority Error"]
314 pub mod CPE {
315 pub const offset: u32 = 14;
316 pub const mask: u32 = 0x01 << offset;
317 pub mod R {}
318 pub mod W {}
319 pub mod RW {
320 #[doc = "No channel priority error"]
321 pub const CPE_0: u32 = 0;
322 #[doc = "The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique."]
323 pub const CPE_1: u32 = 0x01;
324 }
325 }
326 #[doc = "Transfer Canceled"]
327 pub mod ECX {
328 pub const offset: u32 = 16;
329 pub const mask: u32 = 0x01 << offset;
330 pub mod R {}
331 pub mod W {}
332 pub mod RW {
333 #[doc = "No canceled transfers"]
334 pub const ECX_0: u32 = 0;
335 #[doc = "The last recorded entry was a canceled transfer by the error cancel transfer input"]
336 pub const ECX_1: u32 = 0x01;
337 }
338 }
339 #[doc = "VLD"]
340 pub mod VLD {
341 pub const offset: u32 = 31;
342 pub const mask: u32 = 0x01 << offset;
343 pub mod R {}
344 pub mod W {}
345 pub mod RW {
346 #[doc = "No ERR bits are set."]
347 pub const VLD_0: u32 = 0;
348 #[doc = "At least one ERR bit is set indicating a valid error exists that has not been cleared."]
349 pub const VLD_1: u32 = 0x01;
350 }
351 }
352}
353#[doc = "Enable Request Register"]
354pub mod ERQ {
355 #[doc = "Enable DMA Request 0"]
356 pub mod ERQ0 {
357 pub const offset: u32 = 0;
358 pub const mask: u32 = 0x01 << offset;
359 pub mod R {}
360 pub mod W {}
361 pub mod RW {
362 #[doc = "The DMA request signal for the corresponding channel is disabled"]
363 pub const ERQ0_0: u32 = 0;
364 #[doc = "The DMA request signal for the corresponding channel is enabled"]
365 pub const ERQ0_1: u32 = 0x01;
366 }
367 }
368 #[doc = "Enable DMA Request 1"]
369 pub mod ERQ1 {
370 pub const offset: u32 = 1;
371 pub const mask: u32 = 0x01 << offset;
372 pub mod R {}
373 pub mod W {}
374 pub mod RW {
375 #[doc = "The DMA request signal for the corresponding channel is disabled"]
376 pub const ERQ1_0: u32 = 0;
377 #[doc = "The DMA request signal for the corresponding channel is enabled"]
378 pub const ERQ1_1: u32 = 0x01;
379 }
380 }
381 #[doc = "Enable DMA Request 2"]
382 pub mod ERQ2 {
383 pub const offset: u32 = 2;
384 pub const mask: u32 = 0x01 << offset;
385 pub mod R {}
386 pub mod W {}
387 pub mod RW {
388 #[doc = "The DMA request signal for the corresponding channel is disabled"]
389 pub const ERQ2_0: u32 = 0;
390 #[doc = "The DMA request signal for the corresponding channel is enabled"]
391 pub const ERQ2_1: u32 = 0x01;
392 }
393 }
394 #[doc = "Enable DMA Request 3"]
395 pub mod ERQ3 {
396 pub const offset: u32 = 3;
397 pub const mask: u32 = 0x01 << offset;
398 pub mod R {}
399 pub mod W {}
400 pub mod RW {
401 #[doc = "The DMA request signal for the corresponding channel is disabled"]
402 pub const ERQ3_0: u32 = 0;
403 #[doc = "The DMA request signal for the corresponding channel is enabled"]
404 pub const ERQ3_1: u32 = 0x01;
405 }
406 }
407 #[doc = "Enable DMA Request 4"]
408 pub mod ERQ4 {
409 pub const offset: u32 = 4;
410 pub const mask: u32 = 0x01 << offset;
411 pub mod R {}
412 pub mod W {}
413 pub mod RW {
414 #[doc = "The DMA request signal for the corresponding channel is disabled"]
415 pub const ERQ4_0: u32 = 0;
416 #[doc = "The DMA request signal for the corresponding channel is enabled"]
417 pub const ERQ4_1: u32 = 0x01;
418 }
419 }
420 #[doc = "Enable DMA Request 5"]
421 pub mod ERQ5 {
422 pub const offset: u32 = 5;
423 pub const mask: u32 = 0x01 << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {
427 #[doc = "The DMA request signal for the corresponding channel is disabled"]
428 pub const ERQ5_0: u32 = 0;
429 #[doc = "The DMA request signal for the corresponding channel is enabled"]
430 pub const ERQ5_1: u32 = 0x01;
431 }
432 }
433 #[doc = "Enable DMA Request 6"]
434 pub mod ERQ6 {
435 pub const offset: u32 = 6;
436 pub const mask: u32 = 0x01 << offset;
437 pub mod R {}
438 pub mod W {}
439 pub mod RW {
440 #[doc = "The DMA request signal for the corresponding channel is disabled"]
441 pub const ERQ6_0: u32 = 0;
442 #[doc = "The DMA request signal for the corresponding channel is enabled"]
443 pub const ERQ6_1: u32 = 0x01;
444 }
445 }
446 #[doc = "Enable DMA Request 7"]
447 pub mod ERQ7 {
448 pub const offset: u32 = 7;
449 pub const mask: u32 = 0x01 << offset;
450 pub mod R {}
451 pub mod W {}
452 pub mod RW {
453 #[doc = "The DMA request signal for the corresponding channel is disabled"]
454 pub const ERQ7_0: u32 = 0;
455 #[doc = "The DMA request signal for the corresponding channel is enabled"]
456 pub const ERQ7_1: u32 = 0x01;
457 }
458 }
459 #[doc = "Enable DMA Request 8"]
460 pub mod ERQ8 {
461 pub const offset: u32 = 8;
462 pub const mask: u32 = 0x01 << offset;
463 pub mod R {}
464 pub mod W {}
465 pub mod RW {
466 #[doc = "The DMA request signal for the corresponding channel is disabled"]
467 pub const ERQ8_0: u32 = 0;
468 #[doc = "The DMA request signal for the corresponding channel is enabled"]
469 pub const ERQ8_1: u32 = 0x01;
470 }
471 }
472 #[doc = "Enable DMA Request 9"]
473 pub mod ERQ9 {
474 pub const offset: u32 = 9;
475 pub const mask: u32 = 0x01 << offset;
476 pub mod R {}
477 pub mod W {}
478 pub mod RW {
479 #[doc = "The DMA request signal for the corresponding channel is disabled"]
480 pub const ERQ9_0: u32 = 0;
481 #[doc = "The DMA request signal for the corresponding channel is enabled"]
482 pub const ERQ9_1: u32 = 0x01;
483 }
484 }
485 #[doc = "Enable DMA Request 10"]
486 pub mod ERQ10 {
487 pub const offset: u32 = 10;
488 pub const mask: u32 = 0x01 << offset;
489 pub mod R {}
490 pub mod W {}
491 pub mod RW {
492 #[doc = "The DMA request signal for the corresponding channel is disabled"]
493 pub const ERQ10_0: u32 = 0;
494 #[doc = "The DMA request signal for the corresponding channel is enabled"]
495 pub const ERQ10_1: u32 = 0x01;
496 }
497 }
498 #[doc = "Enable DMA Request 11"]
499 pub mod ERQ11 {
500 pub const offset: u32 = 11;
501 pub const mask: u32 = 0x01 << offset;
502 pub mod R {}
503 pub mod W {}
504 pub mod RW {
505 #[doc = "The DMA request signal for the corresponding channel is disabled"]
506 pub const ERQ11_0: u32 = 0;
507 #[doc = "The DMA request signal for the corresponding channel is enabled"]
508 pub const ERQ11_1: u32 = 0x01;
509 }
510 }
511 #[doc = "Enable DMA Request 12"]
512 pub mod ERQ12 {
513 pub const offset: u32 = 12;
514 pub const mask: u32 = 0x01 << offset;
515 pub mod R {}
516 pub mod W {}
517 pub mod RW {
518 #[doc = "The DMA request signal for the corresponding channel is disabled"]
519 pub const ERQ12_0: u32 = 0;
520 #[doc = "The DMA request signal for the corresponding channel is enabled"]
521 pub const ERQ12_1: u32 = 0x01;
522 }
523 }
524 #[doc = "Enable DMA Request 13"]
525 pub mod ERQ13 {
526 pub const offset: u32 = 13;
527 pub const mask: u32 = 0x01 << offset;
528 pub mod R {}
529 pub mod W {}
530 pub mod RW {
531 #[doc = "The DMA request signal for the corresponding channel is disabled"]
532 pub const ERQ13_0: u32 = 0;
533 #[doc = "The DMA request signal for the corresponding channel is enabled"]
534 pub const ERQ13_1: u32 = 0x01;
535 }
536 }
537 #[doc = "Enable DMA Request 14"]
538 pub mod ERQ14 {
539 pub const offset: u32 = 14;
540 pub const mask: u32 = 0x01 << offset;
541 pub mod R {}
542 pub mod W {}
543 pub mod RW {
544 #[doc = "The DMA request signal for the corresponding channel is disabled"]
545 pub const ERQ14_0: u32 = 0;
546 #[doc = "The DMA request signal for the corresponding channel is enabled"]
547 pub const ERQ14_1: u32 = 0x01;
548 }
549 }
550 #[doc = "Enable DMA Request 15"]
551 pub mod ERQ15 {
552 pub const offset: u32 = 15;
553 pub const mask: u32 = 0x01 << offset;
554 pub mod R {}
555 pub mod W {}
556 pub mod RW {
557 #[doc = "The DMA request signal for the corresponding channel is disabled"]
558 pub const ERQ15_0: u32 = 0;
559 #[doc = "The DMA request signal for the corresponding channel is enabled"]
560 pub const ERQ15_1: u32 = 0x01;
561 }
562 }
563}
564#[doc = "Enable Error Interrupt Register"]
565pub mod EEI {
566 #[doc = "Enable Error Interrupt 0"]
567 pub mod EEI0 {
568 pub const offset: u32 = 0;
569 pub const mask: u32 = 0x01 << offset;
570 pub mod R {}
571 pub mod W {}
572 pub mod RW {
573 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
574 pub const EEI0_0: u32 = 0;
575 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
576 pub const EEI0_1: u32 = 0x01;
577 }
578 }
579 #[doc = "Enable Error Interrupt 1"]
580 pub mod EEI1 {
581 pub const offset: u32 = 1;
582 pub const mask: u32 = 0x01 << offset;
583 pub mod R {}
584 pub mod W {}
585 pub mod RW {
586 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
587 pub const EEI1_0: u32 = 0;
588 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
589 pub const EEI1_1: u32 = 0x01;
590 }
591 }
592 #[doc = "Enable Error Interrupt 2"]
593 pub mod EEI2 {
594 pub const offset: u32 = 2;
595 pub const mask: u32 = 0x01 << offset;
596 pub mod R {}
597 pub mod W {}
598 pub mod RW {
599 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
600 pub const EEI2_0: u32 = 0;
601 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
602 pub const EEI2_1: u32 = 0x01;
603 }
604 }
605 #[doc = "Enable Error Interrupt 3"]
606 pub mod EEI3 {
607 pub const offset: u32 = 3;
608 pub const mask: u32 = 0x01 << offset;
609 pub mod R {}
610 pub mod W {}
611 pub mod RW {
612 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
613 pub const EEI3_0: u32 = 0;
614 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
615 pub const EEI3_1: u32 = 0x01;
616 }
617 }
618 #[doc = "Enable Error Interrupt 4"]
619 pub mod EEI4 {
620 pub const offset: u32 = 4;
621 pub const mask: u32 = 0x01 << offset;
622 pub mod R {}
623 pub mod W {}
624 pub mod RW {
625 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
626 pub const EEI4_0: u32 = 0;
627 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
628 pub const EEI4_1: u32 = 0x01;
629 }
630 }
631 #[doc = "Enable Error Interrupt 5"]
632 pub mod EEI5 {
633 pub const offset: u32 = 5;
634 pub const mask: u32 = 0x01 << offset;
635 pub mod R {}
636 pub mod W {}
637 pub mod RW {
638 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
639 pub const EEI5_0: u32 = 0;
640 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
641 pub const EEI5_1: u32 = 0x01;
642 }
643 }
644 #[doc = "Enable Error Interrupt 6"]
645 pub mod EEI6 {
646 pub const offset: u32 = 6;
647 pub const mask: u32 = 0x01 << offset;
648 pub mod R {}
649 pub mod W {}
650 pub mod RW {
651 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
652 pub const EEI6_0: u32 = 0;
653 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
654 pub const EEI6_1: u32 = 0x01;
655 }
656 }
657 #[doc = "Enable Error Interrupt 7"]
658 pub mod EEI7 {
659 pub const offset: u32 = 7;
660 pub const mask: u32 = 0x01 << offset;
661 pub mod R {}
662 pub mod W {}
663 pub mod RW {
664 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
665 pub const EEI7_0: u32 = 0;
666 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
667 pub const EEI7_1: u32 = 0x01;
668 }
669 }
670 #[doc = "Enable Error Interrupt 8"]
671 pub mod EEI8 {
672 pub const offset: u32 = 8;
673 pub const mask: u32 = 0x01 << offset;
674 pub mod R {}
675 pub mod W {}
676 pub mod RW {
677 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
678 pub const EEI8_0: u32 = 0;
679 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
680 pub const EEI8_1: u32 = 0x01;
681 }
682 }
683 #[doc = "Enable Error Interrupt 9"]
684 pub mod EEI9 {
685 pub const offset: u32 = 9;
686 pub const mask: u32 = 0x01 << offset;
687 pub mod R {}
688 pub mod W {}
689 pub mod RW {
690 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
691 pub const EEI9_0: u32 = 0;
692 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
693 pub const EEI9_1: u32 = 0x01;
694 }
695 }
696 #[doc = "Enable Error Interrupt 10"]
697 pub mod EEI10 {
698 pub const offset: u32 = 10;
699 pub const mask: u32 = 0x01 << offset;
700 pub mod R {}
701 pub mod W {}
702 pub mod RW {
703 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
704 pub const EEI10_0: u32 = 0;
705 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
706 pub const EEI10_1: u32 = 0x01;
707 }
708 }
709 #[doc = "Enable Error Interrupt 11"]
710 pub mod EEI11 {
711 pub const offset: u32 = 11;
712 pub const mask: u32 = 0x01 << offset;
713 pub mod R {}
714 pub mod W {}
715 pub mod RW {
716 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
717 pub const EEI11_0: u32 = 0;
718 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
719 pub const EEI11_1: u32 = 0x01;
720 }
721 }
722 #[doc = "Enable Error Interrupt 12"]
723 pub mod EEI12 {
724 pub const offset: u32 = 12;
725 pub const mask: u32 = 0x01 << offset;
726 pub mod R {}
727 pub mod W {}
728 pub mod RW {
729 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
730 pub const EEI12_0: u32 = 0;
731 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
732 pub const EEI12_1: u32 = 0x01;
733 }
734 }
735 #[doc = "Enable Error Interrupt 13"]
736 pub mod EEI13 {
737 pub const offset: u32 = 13;
738 pub const mask: u32 = 0x01 << offset;
739 pub mod R {}
740 pub mod W {}
741 pub mod RW {
742 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
743 pub const EEI13_0: u32 = 0;
744 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
745 pub const EEI13_1: u32 = 0x01;
746 }
747 }
748 #[doc = "Enable Error Interrupt 14"]
749 pub mod EEI14 {
750 pub const offset: u32 = 14;
751 pub const mask: u32 = 0x01 << offset;
752 pub mod R {}
753 pub mod W {}
754 pub mod RW {
755 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
756 pub const EEI14_0: u32 = 0;
757 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
758 pub const EEI14_1: u32 = 0x01;
759 }
760 }
761 #[doc = "Enable Error Interrupt 15"]
762 pub mod EEI15 {
763 pub const offset: u32 = 15;
764 pub const mask: u32 = 0x01 << offset;
765 pub mod R {}
766 pub mod W {}
767 pub mod RW {
768 #[doc = "The error signal for corresponding channel does not generate an error interrupt"]
769 pub const EEI15_0: u32 = 0;
770 #[doc = "The assertion of the error signal for corresponding channel generates an error interrupt request"]
771 pub const EEI15_1: u32 = 0x01;
772 }
773 }
774}
775#[doc = "Clear Enable Error Interrupt Register"]
776pub mod CEEI {
777 #[doc = "Clear Enable Error Interrupt"]
778 pub mod CEEI {
779 pub const offset: u8 = 0;
780 pub const mask: u8 = 0x0f << offset;
781 pub mod R {}
782 pub mod W {}
783 pub mod RW {}
784 }
785 #[doc = "Clear All Enable Error Interrupts"]
786 pub mod CAEE {
787 pub const offset: u8 = 6;
788 pub const mask: u8 = 0x01 << offset;
789 pub mod R {}
790 pub mod W {}
791 pub mod RW {
792 #[doc = "Clear only the EEI bit specified in the CEEI field"]
793 pub const CAEE_0: u8 = 0;
794 #[doc = "Clear all bits in EEI"]
795 pub const CAEE_1: u8 = 0x01;
796 }
797 }
798 #[doc = "No Op enable"]
799 pub mod NOP {
800 pub const offset: u8 = 7;
801 pub const mask: u8 = 0x01 << offset;
802 pub mod R {}
803 pub mod W {}
804 pub mod RW {
805 #[doc = "Normal operation"]
806 pub const NOP_0: u8 = 0;
807 #[doc = "No operation, ignore the other bits in this register"]
808 pub const NOP_1: u8 = 0x01;
809 }
810 }
811}
812#[doc = "Set Enable Error Interrupt Register"]
813pub mod SEEI {
814 #[doc = "Set Enable Error Interrupt"]
815 pub mod SEEI {
816 pub const offset: u8 = 0;
817 pub const mask: u8 = 0x0f << offset;
818 pub mod R {}
819 pub mod W {}
820 pub mod RW {}
821 }
822 #[doc = "Sets All Enable Error Interrupts"]
823 pub mod SAEE {
824 pub const offset: u8 = 6;
825 pub const mask: u8 = 0x01 << offset;
826 pub mod R {}
827 pub mod W {}
828 pub mod RW {
829 #[doc = "Set only the EEI bit specified in the SEEI field."]
830 pub const SAEE_0: u8 = 0;
831 #[doc = "Sets all bits in EEI"]
832 pub const SAEE_1: u8 = 0x01;
833 }
834 }
835 #[doc = "No Op enable"]
836 pub mod NOP {
837 pub const offset: u8 = 7;
838 pub const mask: u8 = 0x01 << offset;
839 pub mod R {}
840 pub mod W {}
841 pub mod RW {
842 #[doc = "Normal operation"]
843 pub const NOP_0: u8 = 0;
844 #[doc = "No operation, ignore the other bits in this register"]
845 pub const NOP_1: u8 = 0x01;
846 }
847 }
848}
849#[doc = "Clear Enable Request Register"]
850pub mod CERQ {
851 #[doc = "Clear Enable Request"]
852 pub mod CERQ {
853 pub const offset: u8 = 0;
854 pub const mask: u8 = 0x0f << offset;
855 pub mod R {}
856 pub mod W {}
857 pub mod RW {}
858 }
859 #[doc = "Clear All Enable Requests"]
860 pub mod CAER {
861 pub const offset: u8 = 6;
862 pub const mask: u8 = 0x01 << offset;
863 pub mod R {}
864 pub mod W {}
865 pub mod RW {
866 #[doc = "Clear only the ERQ bit specified in the CERQ field"]
867 pub const CAER_0: u8 = 0;
868 #[doc = "Clear all bits in ERQ"]
869 pub const CAER_1: u8 = 0x01;
870 }
871 }
872 #[doc = "No Op enable"]
873 pub mod NOP {
874 pub const offset: u8 = 7;
875 pub const mask: u8 = 0x01 << offset;
876 pub mod R {}
877 pub mod W {}
878 pub mod RW {
879 #[doc = "Normal operation"]
880 pub const NOP_0: u8 = 0;
881 #[doc = "No operation, ignore the other bits in this register"]
882 pub const NOP_1: u8 = 0x01;
883 }
884 }
885}
886#[doc = "Set Enable Request Register"]
887pub mod SERQ {
888 #[doc = "Set Enable Request"]
889 pub mod SERQ {
890 pub const offset: u8 = 0;
891 pub const mask: u8 = 0x0f << offset;
892 pub mod R {}
893 pub mod W {}
894 pub mod RW {}
895 }
896 #[doc = "Set All Enable Requests"]
897 pub mod SAER {
898 pub const offset: u8 = 6;
899 pub const mask: u8 = 0x01 << offset;
900 pub mod R {}
901 pub mod W {}
902 pub mod RW {
903 #[doc = "Set only the ERQ bit specified in the SERQ field"]
904 pub const SAER_0: u8 = 0;
905 #[doc = "Set all bits in ERQ"]
906 pub const SAER_1: u8 = 0x01;
907 }
908 }
909 #[doc = "No Op enable"]
910 pub mod NOP {
911 pub const offset: u8 = 7;
912 pub const mask: u8 = 0x01 << offset;
913 pub mod R {}
914 pub mod W {}
915 pub mod RW {
916 #[doc = "Normal operation"]
917 pub const NOP_0: u8 = 0;
918 #[doc = "No operation, ignore the other bits in this register"]
919 pub const NOP_1: u8 = 0x01;
920 }
921 }
922}
923#[doc = "Clear DONE Status Bit Register"]
924pub mod CDNE {
925 #[doc = "Clear DONE Bit"]
926 pub mod CDNE {
927 pub const offset: u8 = 0;
928 pub const mask: u8 = 0x0f << offset;
929 pub mod R {}
930 pub mod W {}
931 pub mod RW {}
932 }
933 #[doc = "Clears All DONE Bits"]
934 pub mod CADN {
935 pub const offset: u8 = 6;
936 pub const mask: u8 = 0x01 << offset;
937 pub mod R {}
938 pub mod W {}
939 pub mod RW {
940 #[doc = "Clears only the TCDn_CSR\\[DONE\\] bit specified in the CDNE field"]
941 pub const CADN_0: u8 = 0;
942 #[doc = "Clears all bits in TCDn_CSR\\[DONE\\]"]
943 pub const CADN_1: u8 = 0x01;
944 }
945 }
946 #[doc = "No Op enable"]
947 pub mod NOP {
948 pub const offset: u8 = 7;
949 pub const mask: u8 = 0x01 << offset;
950 pub mod R {}
951 pub mod W {}
952 pub mod RW {
953 #[doc = "Normal operation"]
954 pub const NOP_0: u8 = 0;
955 #[doc = "No operation, ignore the other bits in this register"]
956 pub const NOP_1: u8 = 0x01;
957 }
958 }
959}
960#[doc = "Set START Bit Register"]
961pub mod SSRT {
962 #[doc = "Set START Bit"]
963 pub mod SSRT {
964 pub const offset: u8 = 0;
965 pub const mask: u8 = 0x0f << offset;
966 pub mod R {}
967 pub mod W {}
968 pub mod RW {}
969 }
970 #[doc = "Set All START Bits (activates all channels)"]
971 pub mod SAST {
972 pub const offset: u8 = 6;
973 pub const mask: u8 = 0x01 << offset;
974 pub mod R {}
975 pub mod W {}
976 pub mod RW {
977 #[doc = "Set only the TCDn_CSR\\[START\\] bit specified in the SSRT field"]
978 pub const SAST_0: u8 = 0;
979 #[doc = "Set all bits in TCDn_CSR\\[START\\]"]
980 pub const SAST_1: u8 = 0x01;
981 }
982 }
983 #[doc = "No Op enable"]
984 pub mod NOP {
985 pub const offset: u8 = 7;
986 pub const mask: u8 = 0x01 << offset;
987 pub mod R {}
988 pub mod W {}
989 pub mod RW {
990 #[doc = "Normal operation"]
991 pub const NOP_0: u8 = 0;
992 #[doc = "No operation, ignore the other bits in this register"]
993 pub const NOP_1: u8 = 0x01;
994 }
995 }
996}
997#[doc = "Clear Error Register"]
998pub mod CERR {
999 #[doc = "Clear Error Indicator"]
1000 pub mod CERR {
1001 pub const offset: u8 = 0;
1002 pub const mask: u8 = 0x0f << offset;
1003 pub mod R {}
1004 pub mod W {}
1005 pub mod RW {}
1006 }
1007 #[doc = "Clear All Error Indicators"]
1008 pub mod CAEI {
1009 pub const offset: u8 = 6;
1010 pub const mask: u8 = 0x01 << offset;
1011 pub mod R {}
1012 pub mod W {}
1013 pub mod RW {
1014 #[doc = "Clear only the ERR bit specified in the CERR field"]
1015 pub const CAEI_0: u8 = 0;
1016 #[doc = "Clear all bits in ERR"]
1017 pub const CAEI_1: u8 = 0x01;
1018 }
1019 }
1020 #[doc = "No Op enable"]
1021 pub mod NOP {
1022 pub const offset: u8 = 7;
1023 pub const mask: u8 = 0x01 << offset;
1024 pub mod R {}
1025 pub mod W {}
1026 pub mod RW {
1027 #[doc = "Normal operation"]
1028 pub const NOP_0: u8 = 0;
1029 #[doc = "No operation, ignore the other bits in this register"]
1030 pub const NOP_1: u8 = 0x01;
1031 }
1032 }
1033}
1034#[doc = "Clear Interrupt Request Register"]
1035pub mod CINT {
1036 #[doc = "Clear Interrupt Request"]
1037 pub mod CINT {
1038 pub const offset: u8 = 0;
1039 pub const mask: u8 = 0x0f << offset;
1040 pub mod R {}
1041 pub mod W {}
1042 pub mod RW {}
1043 }
1044 #[doc = "Clear All Interrupt Requests"]
1045 pub mod CAIR {
1046 pub const offset: u8 = 6;
1047 pub const mask: u8 = 0x01 << offset;
1048 pub mod R {}
1049 pub mod W {}
1050 pub mod RW {
1051 #[doc = "Clear only the INT bit specified in the CINT field"]
1052 pub const CAIR_0: u8 = 0;
1053 #[doc = "Clear all bits in INT"]
1054 pub const CAIR_1: u8 = 0x01;
1055 }
1056 }
1057 #[doc = "No Op enable"]
1058 pub mod NOP {
1059 pub const offset: u8 = 7;
1060 pub const mask: u8 = 0x01 << offset;
1061 pub mod R {}
1062 pub mod W {}
1063 pub mod RW {
1064 #[doc = "Normal operation"]
1065 pub const NOP_0: u8 = 0;
1066 #[doc = "No operation, ignore the other bits in this register"]
1067 pub const NOP_1: u8 = 0x01;
1068 }
1069 }
1070}
1071#[doc = "Interrupt Request Register"]
1072pub mod INT {
1073 #[doc = "Interrupt Request 0"]
1074 pub mod INT0 {
1075 pub const offset: u32 = 0;
1076 pub const mask: u32 = 0x01 << offset;
1077 pub mod R {}
1078 pub mod W {}
1079 pub mod RW {
1080 #[doc = "The interrupt request for corresponding channel is cleared"]
1081 pub const INT0_0: u32 = 0;
1082 #[doc = "The interrupt request for corresponding channel is active"]
1083 pub const INT0_1: u32 = 0x01;
1084 }
1085 }
1086 #[doc = "Interrupt Request 1"]
1087 pub mod INT1 {
1088 pub const offset: u32 = 1;
1089 pub const mask: u32 = 0x01 << offset;
1090 pub mod R {}
1091 pub mod W {}
1092 pub mod RW {
1093 #[doc = "The interrupt request for corresponding channel is cleared"]
1094 pub const INT1_0: u32 = 0;
1095 #[doc = "The interrupt request for corresponding channel is active"]
1096 pub const INT1_1: u32 = 0x01;
1097 }
1098 }
1099 #[doc = "Interrupt Request 2"]
1100 pub mod INT2 {
1101 pub const offset: u32 = 2;
1102 pub const mask: u32 = 0x01 << offset;
1103 pub mod R {}
1104 pub mod W {}
1105 pub mod RW {
1106 #[doc = "The interrupt request for corresponding channel is cleared"]
1107 pub const INT2_0: u32 = 0;
1108 #[doc = "The interrupt request for corresponding channel is active"]
1109 pub const INT2_1: u32 = 0x01;
1110 }
1111 }
1112 #[doc = "Interrupt Request 3"]
1113 pub mod INT3 {
1114 pub const offset: u32 = 3;
1115 pub const mask: u32 = 0x01 << offset;
1116 pub mod R {}
1117 pub mod W {}
1118 pub mod RW {
1119 #[doc = "The interrupt request for corresponding channel is cleared"]
1120 pub const INT3_0: u32 = 0;
1121 #[doc = "The interrupt request for corresponding channel is active"]
1122 pub const INT3_1: u32 = 0x01;
1123 }
1124 }
1125 #[doc = "Interrupt Request 4"]
1126 pub mod INT4 {
1127 pub const offset: u32 = 4;
1128 pub const mask: u32 = 0x01 << offset;
1129 pub mod R {}
1130 pub mod W {}
1131 pub mod RW {
1132 #[doc = "The interrupt request for corresponding channel is cleared"]
1133 pub const INT4_0: u32 = 0;
1134 #[doc = "The interrupt request for corresponding channel is active"]
1135 pub const INT4_1: u32 = 0x01;
1136 }
1137 }
1138 #[doc = "Interrupt Request 5"]
1139 pub mod INT5 {
1140 pub const offset: u32 = 5;
1141 pub const mask: u32 = 0x01 << offset;
1142 pub mod R {}
1143 pub mod W {}
1144 pub mod RW {
1145 #[doc = "The interrupt request for corresponding channel is cleared"]
1146 pub const INT5_0: u32 = 0;
1147 #[doc = "The interrupt request for corresponding channel is active"]
1148 pub const INT5_1: u32 = 0x01;
1149 }
1150 }
1151 #[doc = "Interrupt Request 6"]
1152 pub mod INT6 {
1153 pub const offset: u32 = 6;
1154 pub const mask: u32 = 0x01 << offset;
1155 pub mod R {}
1156 pub mod W {}
1157 pub mod RW {
1158 #[doc = "The interrupt request for corresponding channel is cleared"]
1159 pub const INT6_0: u32 = 0;
1160 #[doc = "The interrupt request for corresponding channel is active"]
1161 pub const INT6_1: u32 = 0x01;
1162 }
1163 }
1164 #[doc = "Interrupt Request 7"]
1165 pub mod INT7 {
1166 pub const offset: u32 = 7;
1167 pub const mask: u32 = 0x01 << offset;
1168 pub mod R {}
1169 pub mod W {}
1170 pub mod RW {
1171 #[doc = "The interrupt request for corresponding channel is cleared"]
1172 pub const INT7_0: u32 = 0;
1173 #[doc = "The interrupt request for corresponding channel is active"]
1174 pub const INT7_1: u32 = 0x01;
1175 }
1176 }
1177 #[doc = "Interrupt Request 8"]
1178 pub mod INT8 {
1179 pub const offset: u32 = 8;
1180 pub const mask: u32 = 0x01 << offset;
1181 pub mod R {}
1182 pub mod W {}
1183 pub mod RW {
1184 #[doc = "The interrupt request for corresponding channel is cleared"]
1185 pub const INT8_0: u32 = 0;
1186 #[doc = "The interrupt request for corresponding channel is active"]
1187 pub const INT8_1: u32 = 0x01;
1188 }
1189 }
1190 #[doc = "Interrupt Request 9"]
1191 pub mod INT9 {
1192 pub const offset: u32 = 9;
1193 pub const mask: u32 = 0x01 << offset;
1194 pub mod R {}
1195 pub mod W {}
1196 pub mod RW {
1197 #[doc = "The interrupt request for corresponding channel is cleared"]
1198 pub const INT9_0: u32 = 0;
1199 #[doc = "The interrupt request for corresponding channel is active"]
1200 pub const INT9_1: u32 = 0x01;
1201 }
1202 }
1203 #[doc = "Interrupt Request 10"]
1204 pub mod INT10 {
1205 pub const offset: u32 = 10;
1206 pub const mask: u32 = 0x01 << offset;
1207 pub mod R {}
1208 pub mod W {}
1209 pub mod RW {
1210 #[doc = "The interrupt request for corresponding channel is cleared"]
1211 pub const INT10_0: u32 = 0;
1212 #[doc = "The interrupt request for corresponding channel is active"]
1213 pub const INT10_1: u32 = 0x01;
1214 }
1215 }
1216 #[doc = "Interrupt Request 11"]
1217 pub mod INT11 {
1218 pub const offset: u32 = 11;
1219 pub const mask: u32 = 0x01 << offset;
1220 pub mod R {}
1221 pub mod W {}
1222 pub mod RW {
1223 #[doc = "The interrupt request for corresponding channel is cleared"]
1224 pub const INT11_0: u32 = 0;
1225 #[doc = "The interrupt request for corresponding channel is active"]
1226 pub const INT11_1: u32 = 0x01;
1227 }
1228 }
1229 #[doc = "Interrupt Request 12"]
1230 pub mod INT12 {
1231 pub const offset: u32 = 12;
1232 pub const mask: u32 = 0x01 << offset;
1233 pub mod R {}
1234 pub mod W {}
1235 pub mod RW {
1236 #[doc = "The interrupt request for corresponding channel is cleared"]
1237 pub const INT12_0: u32 = 0;
1238 #[doc = "The interrupt request for corresponding channel is active"]
1239 pub const INT12_1: u32 = 0x01;
1240 }
1241 }
1242 #[doc = "Interrupt Request 13"]
1243 pub mod INT13 {
1244 pub const offset: u32 = 13;
1245 pub const mask: u32 = 0x01 << offset;
1246 pub mod R {}
1247 pub mod W {}
1248 pub mod RW {
1249 #[doc = "The interrupt request for corresponding channel is cleared"]
1250 pub const INT13_0: u32 = 0;
1251 #[doc = "The interrupt request for corresponding channel is active"]
1252 pub const INT13_1: u32 = 0x01;
1253 }
1254 }
1255 #[doc = "Interrupt Request 14"]
1256 pub mod INT14 {
1257 pub const offset: u32 = 14;
1258 pub const mask: u32 = 0x01 << offset;
1259 pub mod R {}
1260 pub mod W {}
1261 pub mod RW {
1262 #[doc = "The interrupt request for corresponding channel is cleared"]
1263 pub const INT14_0: u32 = 0;
1264 #[doc = "The interrupt request for corresponding channel is active"]
1265 pub const INT14_1: u32 = 0x01;
1266 }
1267 }
1268 #[doc = "Interrupt Request 15"]
1269 pub mod INT15 {
1270 pub const offset: u32 = 15;
1271 pub const mask: u32 = 0x01 << offset;
1272 pub mod R {}
1273 pub mod W {}
1274 pub mod RW {
1275 #[doc = "The interrupt request for corresponding channel is cleared"]
1276 pub const INT15_0: u32 = 0;
1277 #[doc = "The interrupt request for corresponding channel is active"]
1278 pub const INT15_1: u32 = 0x01;
1279 }
1280 }
1281}
1282#[doc = "Error Register"]
1283pub mod ERR {
1284 #[doc = "Error In Channel 0"]
1285 pub mod ERR0 {
1286 pub const offset: u32 = 0;
1287 pub const mask: u32 = 0x01 << offset;
1288 pub mod R {}
1289 pub mod W {}
1290 pub mod RW {
1291 #[doc = "An error in this channel has not occurred"]
1292 pub const ERR0_0: u32 = 0;
1293 #[doc = "An error in this channel has occurred"]
1294 pub const ERR0_1: u32 = 0x01;
1295 }
1296 }
1297 #[doc = "Error In Channel 1"]
1298 pub mod ERR1 {
1299 pub const offset: u32 = 1;
1300 pub const mask: u32 = 0x01 << offset;
1301 pub mod R {}
1302 pub mod W {}
1303 pub mod RW {
1304 #[doc = "An error in this channel has not occurred"]
1305 pub const ERR1_0: u32 = 0;
1306 #[doc = "An error in this channel has occurred"]
1307 pub const ERR1_1: u32 = 0x01;
1308 }
1309 }
1310 #[doc = "Error In Channel 2"]
1311 pub mod ERR2 {
1312 pub const offset: u32 = 2;
1313 pub const mask: u32 = 0x01 << offset;
1314 pub mod R {}
1315 pub mod W {}
1316 pub mod RW {
1317 #[doc = "An error in this channel has not occurred"]
1318 pub const ERR2_0: u32 = 0;
1319 #[doc = "An error in this channel has occurred"]
1320 pub const ERR2_1: u32 = 0x01;
1321 }
1322 }
1323 #[doc = "Error In Channel 3"]
1324 pub mod ERR3 {
1325 pub const offset: u32 = 3;
1326 pub const mask: u32 = 0x01 << offset;
1327 pub mod R {}
1328 pub mod W {}
1329 pub mod RW {
1330 #[doc = "An error in this channel has not occurred"]
1331 pub const ERR3_0: u32 = 0;
1332 #[doc = "An error in this channel has occurred"]
1333 pub const ERR3_1: u32 = 0x01;
1334 }
1335 }
1336 #[doc = "Error In Channel 4"]
1337 pub mod ERR4 {
1338 pub const offset: u32 = 4;
1339 pub const mask: u32 = 0x01 << offset;
1340 pub mod R {}
1341 pub mod W {}
1342 pub mod RW {
1343 #[doc = "An error in this channel has not occurred"]
1344 pub const ERR4_0: u32 = 0;
1345 #[doc = "An error in this channel has occurred"]
1346 pub const ERR4_1: u32 = 0x01;
1347 }
1348 }
1349 #[doc = "Error In Channel 5"]
1350 pub mod ERR5 {
1351 pub const offset: u32 = 5;
1352 pub const mask: u32 = 0x01 << offset;
1353 pub mod R {}
1354 pub mod W {}
1355 pub mod RW {
1356 #[doc = "An error in this channel has not occurred"]
1357 pub const ERR5_0: u32 = 0;
1358 #[doc = "An error in this channel has occurred"]
1359 pub const ERR5_1: u32 = 0x01;
1360 }
1361 }
1362 #[doc = "Error In Channel 6"]
1363 pub mod ERR6 {
1364 pub const offset: u32 = 6;
1365 pub const mask: u32 = 0x01 << offset;
1366 pub mod R {}
1367 pub mod W {}
1368 pub mod RW {
1369 #[doc = "An error in this channel has not occurred"]
1370 pub const ERR6_0: u32 = 0;
1371 #[doc = "An error in this channel has occurred"]
1372 pub const ERR6_1: u32 = 0x01;
1373 }
1374 }
1375 #[doc = "Error In Channel 7"]
1376 pub mod ERR7 {
1377 pub const offset: u32 = 7;
1378 pub const mask: u32 = 0x01 << offset;
1379 pub mod R {}
1380 pub mod W {}
1381 pub mod RW {
1382 #[doc = "An error in this channel has not occurred"]
1383 pub const ERR7_0: u32 = 0;
1384 #[doc = "An error in this channel has occurred"]
1385 pub const ERR7_1: u32 = 0x01;
1386 }
1387 }
1388 #[doc = "Error In Channel 8"]
1389 pub mod ERR8 {
1390 pub const offset: u32 = 8;
1391 pub const mask: u32 = 0x01 << offset;
1392 pub mod R {}
1393 pub mod W {}
1394 pub mod RW {
1395 #[doc = "An error in this channel has not occurred"]
1396 pub const ERR8_0: u32 = 0;
1397 #[doc = "An error in this channel has occurred"]
1398 pub const ERR8_1: u32 = 0x01;
1399 }
1400 }
1401 #[doc = "Error In Channel 9"]
1402 pub mod ERR9 {
1403 pub const offset: u32 = 9;
1404 pub const mask: u32 = 0x01 << offset;
1405 pub mod R {}
1406 pub mod W {}
1407 pub mod RW {
1408 #[doc = "An error in this channel has not occurred"]
1409 pub const ERR9_0: u32 = 0;
1410 #[doc = "An error in this channel has occurred"]
1411 pub const ERR9_1: u32 = 0x01;
1412 }
1413 }
1414 #[doc = "Error In Channel 10"]
1415 pub mod ERR10 {
1416 pub const offset: u32 = 10;
1417 pub const mask: u32 = 0x01 << offset;
1418 pub mod R {}
1419 pub mod W {}
1420 pub mod RW {
1421 #[doc = "An error in this channel has not occurred"]
1422 pub const ERR10_0: u32 = 0;
1423 #[doc = "An error in this channel has occurred"]
1424 pub const ERR10_1: u32 = 0x01;
1425 }
1426 }
1427 #[doc = "Error In Channel 11"]
1428 pub mod ERR11 {
1429 pub const offset: u32 = 11;
1430 pub const mask: u32 = 0x01 << offset;
1431 pub mod R {}
1432 pub mod W {}
1433 pub mod RW {
1434 #[doc = "An error in this channel has not occurred"]
1435 pub const ERR11_0: u32 = 0;
1436 #[doc = "An error in this channel has occurred"]
1437 pub const ERR11_1: u32 = 0x01;
1438 }
1439 }
1440 #[doc = "Error In Channel 12"]
1441 pub mod ERR12 {
1442 pub const offset: u32 = 12;
1443 pub const mask: u32 = 0x01 << offset;
1444 pub mod R {}
1445 pub mod W {}
1446 pub mod RW {
1447 #[doc = "An error in this channel has not occurred"]
1448 pub const ERR12_0: u32 = 0;
1449 #[doc = "An error in this channel has occurred"]
1450 pub const ERR12_1: u32 = 0x01;
1451 }
1452 }
1453 #[doc = "Error In Channel 13"]
1454 pub mod ERR13 {
1455 pub const offset: u32 = 13;
1456 pub const mask: u32 = 0x01 << offset;
1457 pub mod R {}
1458 pub mod W {}
1459 pub mod RW {
1460 #[doc = "An error in this channel has not occurred"]
1461 pub const ERR13_0: u32 = 0;
1462 #[doc = "An error in this channel has occurred"]
1463 pub const ERR13_1: u32 = 0x01;
1464 }
1465 }
1466 #[doc = "Error In Channel 14"]
1467 pub mod ERR14 {
1468 pub const offset: u32 = 14;
1469 pub const mask: u32 = 0x01 << offset;
1470 pub mod R {}
1471 pub mod W {}
1472 pub mod RW {
1473 #[doc = "An error in this channel has not occurred"]
1474 pub const ERR14_0: u32 = 0;
1475 #[doc = "An error in this channel has occurred"]
1476 pub const ERR14_1: u32 = 0x01;
1477 }
1478 }
1479 #[doc = "Error In Channel 15"]
1480 pub mod ERR15 {
1481 pub const offset: u32 = 15;
1482 pub const mask: u32 = 0x01 << offset;
1483 pub mod R {}
1484 pub mod W {}
1485 pub mod RW {
1486 #[doc = "An error in this channel has not occurred"]
1487 pub const ERR15_0: u32 = 0;
1488 #[doc = "An error in this channel has occurred"]
1489 pub const ERR15_1: u32 = 0x01;
1490 }
1491 }
1492}
1493#[doc = "Hardware Request Status Register"]
1494pub mod HRS {
1495 #[doc = "Hardware Request Status Channel 0"]
1496 pub mod HRS0 {
1497 pub const offset: u32 = 0;
1498 pub const mask: u32 = 0x01 << offset;
1499 pub mod R {}
1500 pub mod W {}
1501 pub mod RW {
1502 #[doc = "A hardware service request for channel 0 is not present"]
1503 pub const HRS0_0: u32 = 0;
1504 #[doc = "A hardware service request for channel 0 is present"]
1505 pub const HRS0_1: u32 = 0x01;
1506 }
1507 }
1508 #[doc = "Hardware Request Status Channel 1"]
1509 pub mod HRS1 {
1510 pub const offset: u32 = 1;
1511 pub const mask: u32 = 0x01 << offset;
1512 pub mod R {}
1513 pub mod W {}
1514 pub mod RW {
1515 #[doc = "A hardware service request for channel 1 is not present"]
1516 pub const HRS1_0: u32 = 0;
1517 #[doc = "A hardware service request for channel 1 is present"]
1518 pub const HRS1_1: u32 = 0x01;
1519 }
1520 }
1521 #[doc = "Hardware Request Status Channel 2"]
1522 pub mod HRS2 {
1523 pub const offset: u32 = 2;
1524 pub const mask: u32 = 0x01 << offset;
1525 pub mod R {}
1526 pub mod W {}
1527 pub mod RW {
1528 #[doc = "A hardware service request for channel 2 is not present"]
1529 pub const HRS2_0: u32 = 0;
1530 #[doc = "A hardware service request for channel 2 is present"]
1531 pub const HRS2_1: u32 = 0x01;
1532 }
1533 }
1534 #[doc = "Hardware Request Status Channel 3"]
1535 pub mod HRS3 {
1536 pub const offset: u32 = 3;
1537 pub const mask: u32 = 0x01 << offset;
1538 pub mod R {}
1539 pub mod W {}
1540 pub mod RW {
1541 #[doc = "A hardware service request for channel 3 is not present"]
1542 pub const HRS3_0: u32 = 0;
1543 #[doc = "A hardware service request for channel 3 is present"]
1544 pub const HRS3_1: u32 = 0x01;
1545 }
1546 }
1547 #[doc = "Hardware Request Status Channel 4"]
1548 pub mod HRS4 {
1549 pub const offset: u32 = 4;
1550 pub const mask: u32 = 0x01 << offset;
1551 pub mod R {}
1552 pub mod W {}
1553 pub mod RW {
1554 #[doc = "A hardware service request for channel 4 is not present"]
1555 pub const HRS4_0: u32 = 0;
1556 #[doc = "A hardware service request for channel 4 is present"]
1557 pub const HRS4_1: u32 = 0x01;
1558 }
1559 }
1560 #[doc = "Hardware Request Status Channel 5"]
1561 pub mod HRS5 {
1562 pub const offset: u32 = 5;
1563 pub const mask: u32 = 0x01 << offset;
1564 pub mod R {}
1565 pub mod W {}
1566 pub mod RW {
1567 #[doc = "A hardware service request for channel 5 is not present"]
1568 pub const HRS5_0: u32 = 0;
1569 #[doc = "A hardware service request for channel 5 is present"]
1570 pub const HRS5_1: u32 = 0x01;
1571 }
1572 }
1573 #[doc = "Hardware Request Status Channel 6"]
1574 pub mod HRS6 {
1575 pub const offset: u32 = 6;
1576 pub const mask: u32 = 0x01 << offset;
1577 pub mod R {}
1578 pub mod W {}
1579 pub mod RW {
1580 #[doc = "A hardware service request for channel 6 is not present"]
1581 pub const HRS6_0: u32 = 0;
1582 #[doc = "A hardware service request for channel 6 is present"]
1583 pub const HRS6_1: u32 = 0x01;
1584 }
1585 }
1586 #[doc = "Hardware Request Status Channel 7"]
1587 pub mod HRS7 {
1588 pub const offset: u32 = 7;
1589 pub const mask: u32 = 0x01 << offset;
1590 pub mod R {}
1591 pub mod W {}
1592 pub mod RW {
1593 #[doc = "A hardware service request for channel 7 is not present"]
1594 pub const HRS7_0: u32 = 0;
1595 #[doc = "A hardware service request for channel 7 is present"]
1596 pub const HRS7_1: u32 = 0x01;
1597 }
1598 }
1599 #[doc = "Hardware Request Status Channel 8"]
1600 pub mod HRS8 {
1601 pub const offset: u32 = 8;
1602 pub const mask: u32 = 0x01 << offset;
1603 pub mod R {}
1604 pub mod W {}
1605 pub mod RW {
1606 #[doc = "A hardware service request for channel 8 is not present"]
1607 pub const HRS8_0: u32 = 0;
1608 #[doc = "A hardware service request for channel 8 is present"]
1609 pub const HRS8_1: u32 = 0x01;
1610 }
1611 }
1612 #[doc = "Hardware Request Status Channel 9"]
1613 pub mod HRS9 {
1614 pub const offset: u32 = 9;
1615 pub const mask: u32 = 0x01 << offset;
1616 pub mod R {}
1617 pub mod W {}
1618 pub mod RW {
1619 #[doc = "A hardware service request for channel 9 is not present"]
1620 pub const HRS9_0: u32 = 0;
1621 #[doc = "A hardware service request for channel 9 is present"]
1622 pub const HRS9_1: u32 = 0x01;
1623 }
1624 }
1625 #[doc = "Hardware Request Status Channel 10"]
1626 pub mod HRS10 {
1627 pub const offset: u32 = 10;
1628 pub const mask: u32 = 0x01 << offset;
1629 pub mod R {}
1630 pub mod W {}
1631 pub mod RW {
1632 #[doc = "A hardware service request for channel 10 is not present"]
1633 pub const HRS10_0: u32 = 0;
1634 #[doc = "A hardware service request for channel 10 is present"]
1635 pub const HRS10_1: u32 = 0x01;
1636 }
1637 }
1638 #[doc = "Hardware Request Status Channel 11"]
1639 pub mod HRS11 {
1640 pub const offset: u32 = 11;
1641 pub const mask: u32 = 0x01 << offset;
1642 pub mod R {}
1643 pub mod W {}
1644 pub mod RW {
1645 #[doc = "A hardware service request for channel 11 is not present"]
1646 pub const HRS11_0: u32 = 0;
1647 #[doc = "A hardware service request for channel 11 is present"]
1648 pub const HRS11_1: u32 = 0x01;
1649 }
1650 }
1651 #[doc = "Hardware Request Status Channel 12"]
1652 pub mod HRS12 {
1653 pub const offset: u32 = 12;
1654 pub const mask: u32 = 0x01 << offset;
1655 pub mod R {}
1656 pub mod W {}
1657 pub mod RW {
1658 #[doc = "A hardware service request for channel 12 is not present"]
1659 pub const HRS12_0: u32 = 0;
1660 #[doc = "A hardware service request for channel 12 is present"]
1661 pub const HRS12_1: u32 = 0x01;
1662 }
1663 }
1664 #[doc = "Hardware Request Status Channel 13"]
1665 pub mod HRS13 {
1666 pub const offset: u32 = 13;
1667 pub const mask: u32 = 0x01 << offset;
1668 pub mod R {}
1669 pub mod W {}
1670 pub mod RW {
1671 #[doc = "A hardware service request for channel 13 is not present"]
1672 pub const HRS13_0: u32 = 0;
1673 #[doc = "A hardware service request for channel 13 is present"]
1674 pub const HRS13_1: u32 = 0x01;
1675 }
1676 }
1677 #[doc = "Hardware Request Status Channel 14"]
1678 pub mod HRS14 {
1679 pub const offset: u32 = 14;
1680 pub const mask: u32 = 0x01 << offset;
1681 pub mod R {}
1682 pub mod W {}
1683 pub mod RW {
1684 #[doc = "A hardware service request for channel 14 is not present"]
1685 pub const HRS14_0: u32 = 0;
1686 #[doc = "A hardware service request for channel 14 is present"]
1687 pub const HRS14_1: u32 = 0x01;
1688 }
1689 }
1690 #[doc = "Hardware Request Status Channel 15"]
1691 pub mod HRS15 {
1692 pub const offset: u32 = 15;
1693 pub const mask: u32 = 0x01 << offset;
1694 pub mod R {}
1695 pub mod W {}
1696 pub mod RW {
1697 #[doc = "A hardware service request for channel 15 is not present"]
1698 pub const HRS15_0: u32 = 0;
1699 #[doc = "A hardware service request for channel 15 is present"]
1700 pub const HRS15_1: u32 = 0x01;
1701 }
1702 }
1703}
1704#[doc = "Enable Asynchronous Request in Stop Register"]
1705pub mod EARS {
1706 #[doc = "Enable asynchronous DMA request in stop mode for channel 0."]
1707 pub mod EDREQ_0 {
1708 pub const offset: u32 = 0;
1709 pub const mask: u32 = 0x01 << offset;
1710 pub mod R {}
1711 pub mod W {}
1712 pub mod RW {
1713 #[doc = "Disable asynchronous DMA request for channel 0."]
1714 pub const EDREQ_0_0: u32 = 0;
1715 #[doc = "Enable asynchronous DMA request for channel 0."]
1716 pub const EDREQ_0_1: u32 = 0x01;
1717 }
1718 }
1719 #[doc = "Enable asynchronous DMA request in stop mode for channel 1."]
1720 pub mod EDREQ_1 {
1721 pub const offset: u32 = 1;
1722 pub const mask: u32 = 0x01 << offset;
1723 pub mod R {}
1724 pub mod W {}
1725 pub mod RW {
1726 #[doc = "Disable asynchronous DMA request for channel 1"]
1727 pub const EDREQ_1_0: u32 = 0;
1728 #[doc = "Enable asynchronous DMA request for channel 1."]
1729 pub const EDREQ_1_1: u32 = 0x01;
1730 }
1731 }
1732 #[doc = "Enable asynchronous DMA request in stop mode for channel 2."]
1733 pub mod EDREQ_2 {
1734 pub const offset: u32 = 2;
1735 pub const mask: u32 = 0x01 << offset;
1736 pub mod R {}
1737 pub mod W {}
1738 pub mod RW {
1739 #[doc = "Disable asynchronous DMA request for channel 2."]
1740 pub const EDREQ_2_0: u32 = 0;
1741 #[doc = "Enable asynchronous DMA request for channel 2."]
1742 pub const EDREQ_2_1: u32 = 0x01;
1743 }
1744 }
1745 #[doc = "Enable asynchronous DMA request in stop mode for channel 3."]
1746 pub mod EDREQ_3 {
1747 pub const offset: u32 = 3;
1748 pub const mask: u32 = 0x01 << offset;
1749 pub mod R {}
1750 pub mod W {}
1751 pub mod RW {
1752 #[doc = "Disable asynchronous DMA request for channel 3."]
1753 pub const EDREQ_3_0: u32 = 0;
1754 #[doc = "Enable asynchronous DMA request for channel 3."]
1755 pub const EDREQ_3_1: u32 = 0x01;
1756 }
1757 }
1758 #[doc = "Enable asynchronous DMA request in stop mode for channel 4"]
1759 pub mod EDREQ_4 {
1760 pub const offset: u32 = 4;
1761 pub const mask: u32 = 0x01 << offset;
1762 pub mod R {}
1763 pub mod W {}
1764 pub mod RW {
1765 #[doc = "Disable asynchronous DMA request for channel 4."]
1766 pub const EDREQ_4_0: u32 = 0;
1767 #[doc = "Enable asynchronous DMA request for channel 4."]
1768 pub const EDREQ_4_1: u32 = 0x01;
1769 }
1770 }
1771 #[doc = "Enable asynchronous DMA request in stop mode for channel 5"]
1772 pub mod EDREQ_5 {
1773 pub const offset: u32 = 5;
1774 pub const mask: u32 = 0x01 << offset;
1775 pub mod R {}
1776 pub mod W {}
1777 pub mod RW {
1778 #[doc = "Disable asynchronous DMA request for channel 5."]
1779 pub const EDREQ_5_0: u32 = 0;
1780 #[doc = "Enable asynchronous DMA request for channel 5."]
1781 pub const EDREQ_5_1: u32 = 0x01;
1782 }
1783 }
1784 #[doc = "Enable asynchronous DMA request in stop mode for channel 6"]
1785 pub mod EDREQ_6 {
1786 pub const offset: u32 = 6;
1787 pub const mask: u32 = 0x01 << offset;
1788 pub mod R {}
1789 pub mod W {}
1790 pub mod RW {
1791 #[doc = "Disable asynchronous DMA request for channel 6."]
1792 pub const EDREQ_6_0: u32 = 0;
1793 #[doc = "Enable asynchronous DMA request for channel 6."]
1794 pub const EDREQ_6_1: u32 = 0x01;
1795 }
1796 }
1797 #[doc = "Enable asynchronous DMA request in stop mode for channel 7"]
1798 pub mod EDREQ_7 {
1799 pub const offset: u32 = 7;
1800 pub const mask: u32 = 0x01 << offset;
1801 pub mod R {}
1802 pub mod W {}
1803 pub mod RW {
1804 #[doc = "Disable asynchronous DMA request for channel 7."]
1805 pub const EDREQ_7_0: u32 = 0;
1806 #[doc = "Enable asynchronous DMA request for channel 7."]
1807 pub const EDREQ_7_1: u32 = 0x01;
1808 }
1809 }
1810 #[doc = "Enable asynchronous DMA request in stop mode for channel 8"]
1811 pub mod EDREQ_8 {
1812 pub const offset: u32 = 8;
1813 pub const mask: u32 = 0x01 << offset;
1814 pub mod R {}
1815 pub mod W {}
1816 pub mod RW {
1817 #[doc = "Disable asynchronous DMA request for channel 8."]
1818 pub const EDREQ_8_0: u32 = 0;
1819 #[doc = "Enable asynchronous DMA request for channel 8."]
1820 pub const EDREQ_8_1: u32 = 0x01;
1821 }
1822 }
1823 #[doc = "Enable asynchronous DMA request in stop mode for channel 9"]
1824 pub mod EDREQ_9 {
1825 pub const offset: u32 = 9;
1826 pub const mask: u32 = 0x01 << offset;
1827 pub mod R {}
1828 pub mod W {}
1829 pub mod RW {
1830 #[doc = "Disable asynchronous DMA request for channel 9."]
1831 pub const EDREQ_9_0: u32 = 0;
1832 #[doc = "Enable asynchronous DMA request for channel 9."]
1833 pub const EDREQ_9_1: u32 = 0x01;
1834 }
1835 }
1836 #[doc = "Enable asynchronous DMA request in stop mode for channel 10"]
1837 pub mod EDREQ_10 {
1838 pub const offset: u32 = 10;
1839 pub const mask: u32 = 0x01 << offset;
1840 pub mod R {}
1841 pub mod W {}
1842 pub mod RW {
1843 #[doc = "Disable asynchronous DMA request for channel 10."]
1844 pub const EDREQ_10_0: u32 = 0;
1845 #[doc = "Enable asynchronous DMA request for channel 10."]
1846 pub const EDREQ_10_1: u32 = 0x01;
1847 }
1848 }
1849 #[doc = "Enable asynchronous DMA request in stop mode for channel 11"]
1850 pub mod EDREQ_11 {
1851 pub const offset: u32 = 11;
1852 pub const mask: u32 = 0x01 << offset;
1853 pub mod R {}
1854 pub mod W {}
1855 pub mod RW {
1856 #[doc = "Disable asynchronous DMA request for channel 11."]
1857 pub const EDREQ_11_0: u32 = 0;
1858 #[doc = "Enable asynchronous DMA request for channel 11."]
1859 pub const EDREQ_11_1: u32 = 0x01;
1860 }
1861 }
1862 #[doc = "Enable asynchronous DMA request in stop mode for channel 12"]
1863 pub mod EDREQ_12 {
1864 pub const offset: u32 = 12;
1865 pub const mask: u32 = 0x01 << offset;
1866 pub mod R {}
1867 pub mod W {}
1868 pub mod RW {
1869 #[doc = "Disable asynchronous DMA request for channel 12."]
1870 pub const EDREQ_12_0: u32 = 0;
1871 #[doc = "Enable asynchronous DMA request for channel 12."]
1872 pub const EDREQ_12_1: u32 = 0x01;
1873 }
1874 }
1875 #[doc = "Enable asynchronous DMA request in stop mode for channel 13"]
1876 pub mod EDREQ_13 {
1877 pub const offset: u32 = 13;
1878 pub const mask: u32 = 0x01 << offset;
1879 pub mod R {}
1880 pub mod W {}
1881 pub mod RW {
1882 #[doc = "Disable asynchronous DMA request for channel 13."]
1883 pub const EDREQ_13_0: u32 = 0;
1884 #[doc = "Enable asynchronous DMA request for channel 13."]
1885 pub const EDREQ_13_1: u32 = 0x01;
1886 }
1887 }
1888 #[doc = "Enable asynchronous DMA request in stop mode for channel 14"]
1889 pub mod EDREQ_14 {
1890 pub const offset: u32 = 14;
1891 pub const mask: u32 = 0x01 << offset;
1892 pub mod R {}
1893 pub mod W {}
1894 pub mod RW {
1895 #[doc = "Disable asynchronous DMA request for channel 14."]
1896 pub const EDREQ_14_0: u32 = 0;
1897 #[doc = "Enable asynchronous DMA request for channel 14."]
1898 pub const EDREQ_14_1: u32 = 0x01;
1899 }
1900 }
1901 #[doc = "Enable asynchronous DMA request in stop mode for channel 15"]
1902 pub mod EDREQ_15 {
1903 pub const offset: u32 = 15;
1904 pub const mask: u32 = 0x01 << offset;
1905 pub mod R {}
1906 pub mod W {}
1907 pub mod RW {
1908 #[doc = "Disable asynchronous DMA request for channel 15."]
1909 pub const EDREQ_15_0: u32 = 0;
1910 #[doc = "Enable asynchronous DMA request for channel 15."]
1911 pub const EDREQ_15_1: u32 = 0x01;
1912 }
1913 }
1914}
1915#[doc = "Channel Priority Register"]
1916pub mod DCHPRI3 {
1917 #[doc = "Channel n Arbitration Priority"]
1918 pub mod CHPRI {
1919 pub const offset: u8 = 0;
1920 pub const mask: u8 = 0x0f << offset;
1921 pub mod R {}
1922 pub mod W {}
1923 pub mod RW {}
1924 }
1925 #[doc = "Disable Preempt Ability. This field resets to 0."]
1926 pub mod DPA {
1927 pub const offset: u8 = 6;
1928 pub const mask: u8 = 0x01 << offset;
1929 pub mod R {}
1930 pub mod W {}
1931 pub mod RW {
1932 #[doc = "Channel n can suspend a lower priority channel."]
1933 pub const DPA_0: u8 = 0;
1934 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
1935 pub const DPA_1: u8 = 0x01;
1936 }
1937 }
1938 #[doc = "Enable Channel Preemption. This field resets to 0."]
1939 pub mod ECP {
1940 pub const offset: u8 = 7;
1941 pub const mask: u8 = 0x01 << offset;
1942 pub mod R {}
1943 pub mod W {}
1944 pub mod RW {
1945 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
1946 pub const ECP_0: u8 = 0;
1947 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
1948 pub const ECP_1: u8 = 0x01;
1949 }
1950 }
1951}
1952#[doc = "Channel Priority Register"]
1953pub mod DCHPRI2 {
1954 #[doc = "Channel n Arbitration Priority"]
1955 pub mod CHPRI {
1956 pub const offset: u8 = 0;
1957 pub const mask: u8 = 0x0f << offset;
1958 pub mod R {}
1959 pub mod W {}
1960 pub mod RW {}
1961 }
1962 #[doc = "Disable Preempt Ability. This field resets to 0."]
1963 pub mod DPA {
1964 pub const offset: u8 = 6;
1965 pub const mask: u8 = 0x01 << offset;
1966 pub mod R {}
1967 pub mod W {}
1968 pub mod RW {
1969 #[doc = "Channel n can suspend a lower priority channel."]
1970 pub const DPA_0: u8 = 0;
1971 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
1972 pub const DPA_1: u8 = 0x01;
1973 }
1974 }
1975 #[doc = "Enable Channel Preemption. This field resets to 0."]
1976 pub mod ECP {
1977 pub const offset: u8 = 7;
1978 pub const mask: u8 = 0x01 << offset;
1979 pub mod R {}
1980 pub mod W {}
1981 pub mod RW {
1982 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
1983 pub const ECP_0: u8 = 0;
1984 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
1985 pub const ECP_1: u8 = 0x01;
1986 }
1987 }
1988}
1989#[doc = "Channel Priority Register"]
1990pub mod DCHPRI1 {
1991 #[doc = "Channel n Arbitration Priority"]
1992 pub mod CHPRI {
1993 pub const offset: u8 = 0;
1994 pub const mask: u8 = 0x0f << offset;
1995 pub mod R {}
1996 pub mod W {}
1997 pub mod RW {}
1998 }
1999 #[doc = "Disable Preempt Ability. This field resets to 0."]
2000 pub mod DPA {
2001 pub const offset: u8 = 6;
2002 pub const mask: u8 = 0x01 << offset;
2003 pub mod R {}
2004 pub mod W {}
2005 pub mod RW {
2006 #[doc = "Channel n can suspend a lower priority channel."]
2007 pub const DPA_0: u8 = 0;
2008 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2009 pub const DPA_1: u8 = 0x01;
2010 }
2011 }
2012 #[doc = "Enable Channel Preemption. This field resets to 0."]
2013 pub mod ECP {
2014 pub const offset: u8 = 7;
2015 pub const mask: u8 = 0x01 << offset;
2016 pub mod R {}
2017 pub mod W {}
2018 pub mod RW {
2019 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2020 pub const ECP_0: u8 = 0;
2021 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2022 pub const ECP_1: u8 = 0x01;
2023 }
2024 }
2025}
2026#[doc = "Channel Priority Register"]
2027pub mod DCHPRI0 {
2028 #[doc = "Channel n Arbitration Priority"]
2029 pub mod CHPRI {
2030 pub const offset: u8 = 0;
2031 pub const mask: u8 = 0x0f << offset;
2032 pub mod R {}
2033 pub mod W {}
2034 pub mod RW {}
2035 }
2036 #[doc = "Disable Preempt Ability. This field resets to 0."]
2037 pub mod DPA {
2038 pub const offset: u8 = 6;
2039 pub const mask: u8 = 0x01 << offset;
2040 pub mod R {}
2041 pub mod W {}
2042 pub mod RW {
2043 #[doc = "Channel n can suspend a lower priority channel."]
2044 pub const DPA_0: u8 = 0;
2045 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2046 pub const DPA_1: u8 = 0x01;
2047 }
2048 }
2049 #[doc = "Enable Channel Preemption. This field resets to 0."]
2050 pub mod ECP {
2051 pub const offset: u8 = 7;
2052 pub const mask: u8 = 0x01 << offset;
2053 pub mod R {}
2054 pub mod W {}
2055 pub mod RW {
2056 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2057 pub const ECP_0: u8 = 0;
2058 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2059 pub const ECP_1: u8 = 0x01;
2060 }
2061 }
2062}
2063#[doc = "Channel Priority Register"]
2064pub mod DCHPRI7 {
2065 #[doc = "Channel n Arbitration Priority"]
2066 pub mod CHPRI {
2067 pub const offset: u8 = 0;
2068 pub const mask: u8 = 0x0f << offset;
2069 pub mod R {}
2070 pub mod W {}
2071 pub mod RW {}
2072 }
2073 #[doc = "Disable Preempt Ability. This field resets to 0."]
2074 pub mod DPA {
2075 pub const offset: u8 = 6;
2076 pub const mask: u8 = 0x01 << offset;
2077 pub mod R {}
2078 pub mod W {}
2079 pub mod RW {
2080 #[doc = "Channel n can suspend a lower priority channel."]
2081 pub const DPA_0: u8 = 0;
2082 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2083 pub const DPA_1: u8 = 0x01;
2084 }
2085 }
2086 #[doc = "Enable Channel Preemption. This field resets to 0."]
2087 pub mod ECP {
2088 pub const offset: u8 = 7;
2089 pub const mask: u8 = 0x01 << offset;
2090 pub mod R {}
2091 pub mod W {}
2092 pub mod RW {
2093 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2094 pub const ECP_0: u8 = 0;
2095 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2096 pub const ECP_1: u8 = 0x01;
2097 }
2098 }
2099}
2100#[doc = "Channel Priority Register"]
2101pub mod DCHPRI6 {
2102 #[doc = "Channel n Arbitration Priority"]
2103 pub mod CHPRI {
2104 pub const offset: u8 = 0;
2105 pub const mask: u8 = 0x0f << offset;
2106 pub mod R {}
2107 pub mod W {}
2108 pub mod RW {}
2109 }
2110 #[doc = "Disable Preempt Ability. This field resets to 0."]
2111 pub mod DPA {
2112 pub const offset: u8 = 6;
2113 pub const mask: u8 = 0x01 << offset;
2114 pub mod R {}
2115 pub mod W {}
2116 pub mod RW {
2117 #[doc = "Channel n can suspend a lower priority channel."]
2118 pub const DPA_0: u8 = 0;
2119 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2120 pub const DPA_1: u8 = 0x01;
2121 }
2122 }
2123 #[doc = "Enable Channel Preemption. This field resets to 0."]
2124 pub mod ECP {
2125 pub const offset: u8 = 7;
2126 pub const mask: u8 = 0x01 << offset;
2127 pub mod R {}
2128 pub mod W {}
2129 pub mod RW {
2130 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2131 pub const ECP_0: u8 = 0;
2132 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2133 pub const ECP_1: u8 = 0x01;
2134 }
2135 }
2136}
2137#[doc = "Channel Priority Register"]
2138pub mod DCHPRI5 {
2139 #[doc = "Channel n Arbitration Priority"]
2140 pub mod CHPRI {
2141 pub const offset: u8 = 0;
2142 pub const mask: u8 = 0x0f << offset;
2143 pub mod R {}
2144 pub mod W {}
2145 pub mod RW {}
2146 }
2147 #[doc = "Disable Preempt Ability. This field resets to 0."]
2148 pub mod DPA {
2149 pub const offset: u8 = 6;
2150 pub const mask: u8 = 0x01 << offset;
2151 pub mod R {}
2152 pub mod W {}
2153 pub mod RW {
2154 #[doc = "Channel n can suspend a lower priority channel."]
2155 pub const DPA_0: u8 = 0;
2156 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2157 pub const DPA_1: u8 = 0x01;
2158 }
2159 }
2160 #[doc = "Enable Channel Preemption. This field resets to 0."]
2161 pub mod ECP {
2162 pub const offset: u8 = 7;
2163 pub const mask: u8 = 0x01 << offset;
2164 pub mod R {}
2165 pub mod W {}
2166 pub mod RW {
2167 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2168 pub const ECP_0: u8 = 0;
2169 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2170 pub const ECP_1: u8 = 0x01;
2171 }
2172 }
2173}
2174#[doc = "Channel Priority Register"]
2175pub mod DCHPRI4 {
2176 #[doc = "Channel n Arbitration Priority"]
2177 pub mod CHPRI {
2178 pub const offset: u8 = 0;
2179 pub const mask: u8 = 0x0f << offset;
2180 pub mod R {}
2181 pub mod W {}
2182 pub mod RW {}
2183 }
2184 #[doc = "Disable Preempt Ability. This field resets to 0."]
2185 pub mod DPA {
2186 pub const offset: u8 = 6;
2187 pub const mask: u8 = 0x01 << offset;
2188 pub mod R {}
2189 pub mod W {}
2190 pub mod RW {
2191 #[doc = "Channel n can suspend a lower priority channel."]
2192 pub const DPA_0: u8 = 0;
2193 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2194 pub const DPA_1: u8 = 0x01;
2195 }
2196 }
2197 #[doc = "Enable Channel Preemption. This field resets to 0."]
2198 pub mod ECP {
2199 pub const offset: u8 = 7;
2200 pub const mask: u8 = 0x01 << offset;
2201 pub mod R {}
2202 pub mod W {}
2203 pub mod RW {
2204 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2205 pub const ECP_0: u8 = 0;
2206 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2207 pub const ECP_1: u8 = 0x01;
2208 }
2209 }
2210}
2211#[doc = "Channel Priority Register"]
2212pub mod DCHPRI11 {
2213 #[doc = "Channel n Arbitration Priority"]
2214 pub mod CHPRI {
2215 pub const offset: u8 = 0;
2216 pub const mask: u8 = 0x0f << offset;
2217 pub mod R {}
2218 pub mod W {}
2219 pub mod RW {}
2220 }
2221 #[doc = "Disable Preempt Ability. This field resets to 0."]
2222 pub mod DPA {
2223 pub const offset: u8 = 6;
2224 pub const mask: u8 = 0x01 << offset;
2225 pub mod R {}
2226 pub mod W {}
2227 pub mod RW {
2228 #[doc = "Channel n can suspend a lower priority channel."]
2229 pub const DPA_0: u8 = 0;
2230 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2231 pub const DPA_1: u8 = 0x01;
2232 }
2233 }
2234 #[doc = "Enable Channel Preemption. This field resets to 0."]
2235 pub mod ECP {
2236 pub const offset: u8 = 7;
2237 pub const mask: u8 = 0x01 << offset;
2238 pub mod R {}
2239 pub mod W {}
2240 pub mod RW {
2241 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2242 pub const ECP_0: u8 = 0;
2243 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2244 pub const ECP_1: u8 = 0x01;
2245 }
2246 }
2247}
2248#[doc = "Channel Priority Register"]
2249pub mod DCHPRI10 {
2250 #[doc = "Channel n Arbitration Priority"]
2251 pub mod CHPRI {
2252 pub const offset: u8 = 0;
2253 pub const mask: u8 = 0x0f << offset;
2254 pub mod R {}
2255 pub mod W {}
2256 pub mod RW {}
2257 }
2258 #[doc = "Disable Preempt Ability. This field resets to 0."]
2259 pub mod DPA {
2260 pub const offset: u8 = 6;
2261 pub const mask: u8 = 0x01 << offset;
2262 pub mod R {}
2263 pub mod W {}
2264 pub mod RW {
2265 #[doc = "Channel n can suspend a lower priority channel."]
2266 pub const DPA_0: u8 = 0;
2267 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2268 pub const DPA_1: u8 = 0x01;
2269 }
2270 }
2271 #[doc = "Enable Channel Preemption. This field resets to 0."]
2272 pub mod ECP {
2273 pub const offset: u8 = 7;
2274 pub const mask: u8 = 0x01 << offset;
2275 pub mod R {}
2276 pub mod W {}
2277 pub mod RW {
2278 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2279 pub const ECP_0: u8 = 0;
2280 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2281 pub const ECP_1: u8 = 0x01;
2282 }
2283 }
2284}
2285#[doc = "Channel Priority Register"]
2286pub mod DCHPRI9 {
2287 #[doc = "Channel n Arbitration Priority"]
2288 pub mod CHPRI {
2289 pub const offset: u8 = 0;
2290 pub const mask: u8 = 0x0f << offset;
2291 pub mod R {}
2292 pub mod W {}
2293 pub mod RW {}
2294 }
2295 #[doc = "Disable Preempt Ability. This field resets to 0."]
2296 pub mod DPA {
2297 pub const offset: u8 = 6;
2298 pub const mask: u8 = 0x01 << offset;
2299 pub mod R {}
2300 pub mod W {}
2301 pub mod RW {
2302 #[doc = "Channel n can suspend a lower priority channel."]
2303 pub const DPA_0: u8 = 0;
2304 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2305 pub const DPA_1: u8 = 0x01;
2306 }
2307 }
2308 #[doc = "Enable Channel Preemption. This field resets to 0."]
2309 pub mod ECP {
2310 pub const offset: u8 = 7;
2311 pub const mask: u8 = 0x01 << offset;
2312 pub mod R {}
2313 pub mod W {}
2314 pub mod RW {
2315 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2316 pub const ECP_0: u8 = 0;
2317 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2318 pub const ECP_1: u8 = 0x01;
2319 }
2320 }
2321}
2322#[doc = "Channel Priority Register"]
2323pub mod DCHPRI8 {
2324 #[doc = "Channel n Arbitration Priority"]
2325 pub mod CHPRI {
2326 pub const offset: u8 = 0;
2327 pub const mask: u8 = 0x0f << offset;
2328 pub mod R {}
2329 pub mod W {}
2330 pub mod RW {}
2331 }
2332 #[doc = "Disable Preempt Ability. This field resets to 0."]
2333 pub mod DPA {
2334 pub const offset: u8 = 6;
2335 pub const mask: u8 = 0x01 << offset;
2336 pub mod R {}
2337 pub mod W {}
2338 pub mod RW {
2339 #[doc = "Channel n can suspend a lower priority channel."]
2340 pub const DPA_0: u8 = 0;
2341 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2342 pub const DPA_1: u8 = 0x01;
2343 }
2344 }
2345 #[doc = "Enable Channel Preemption. This field resets to 0."]
2346 pub mod ECP {
2347 pub const offset: u8 = 7;
2348 pub const mask: u8 = 0x01 << offset;
2349 pub mod R {}
2350 pub mod W {}
2351 pub mod RW {
2352 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2353 pub const ECP_0: u8 = 0;
2354 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2355 pub const ECP_1: u8 = 0x01;
2356 }
2357 }
2358}
2359#[doc = "Channel Priority Register"]
2360pub mod DCHPRI15 {
2361 #[doc = "Channel n Arbitration Priority"]
2362 pub mod CHPRI {
2363 pub const offset: u8 = 0;
2364 pub const mask: u8 = 0x0f << offset;
2365 pub mod R {}
2366 pub mod W {}
2367 pub mod RW {}
2368 }
2369 #[doc = "Disable Preempt Ability. This field resets to 0."]
2370 pub mod DPA {
2371 pub const offset: u8 = 6;
2372 pub const mask: u8 = 0x01 << offset;
2373 pub mod R {}
2374 pub mod W {}
2375 pub mod RW {
2376 #[doc = "Channel n can suspend a lower priority channel."]
2377 pub const DPA_0: u8 = 0;
2378 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2379 pub const DPA_1: u8 = 0x01;
2380 }
2381 }
2382 #[doc = "Enable Channel Preemption. This field resets to 0."]
2383 pub mod ECP {
2384 pub const offset: u8 = 7;
2385 pub const mask: u8 = 0x01 << offset;
2386 pub mod R {}
2387 pub mod W {}
2388 pub mod RW {
2389 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2390 pub const ECP_0: u8 = 0;
2391 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2392 pub const ECP_1: u8 = 0x01;
2393 }
2394 }
2395}
2396#[doc = "Channel Priority Register"]
2397pub mod DCHPRI14 {
2398 #[doc = "Channel n Arbitration Priority"]
2399 pub mod CHPRI {
2400 pub const offset: u8 = 0;
2401 pub const mask: u8 = 0x0f << offset;
2402 pub mod R {}
2403 pub mod W {}
2404 pub mod RW {}
2405 }
2406 #[doc = "Disable Preempt Ability. This field resets to 0."]
2407 pub mod DPA {
2408 pub const offset: u8 = 6;
2409 pub const mask: u8 = 0x01 << offset;
2410 pub mod R {}
2411 pub mod W {}
2412 pub mod RW {
2413 #[doc = "Channel n can suspend a lower priority channel."]
2414 pub const DPA_0: u8 = 0;
2415 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2416 pub const DPA_1: u8 = 0x01;
2417 }
2418 }
2419 #[doc = "Enable Channel Preemption. This field resets to 0."]
2420 pub mod ECP {
2421 pub const offset: u8 = 7;
2422 pub const mask: u8 = 0x01 << offset;
2423 pub mod R {}
2424 pub mod W {}
2425 pub mod RW {
2426 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2427 pub const ECP_0: u8 = 0;
2428 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2429 pub const ECP_1: u8 = 0x01;
2430 }
2431 }
2432}
2433#[doc = "Channel Priority Register"]
2434pub mod DCHPRI13 {
2435 #[doc = "Channel n Arbitration Priority"]
2436 pub mod CHPRI {
2437 pub const offset: u8 = 0;
2438 pub const mask: u8 = 0x0f << offset;
2439 pub mod R {}
2440 pub mod W {}
2441 pub mod RW {}
2442 }
2443 #[doc = "Disable Preempt Ability. This field resets to 0."]
2444 pub mod DPA {
2445 pub const offset: u8 = 6;
2446 pub const mask: u8 = 0x01 << offset;
2447 pub mod R {}
2448 pub mod W {}
2449 pub mod RW {
2450 #[doc = "Channel n can suspend a lower priority channel."]
2451 pub const DPA_0: u8 = 0;
2452 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2453 pub const DPA_1: u8 = 0x01;
2454 }
2455 }
2456 #[doc = "Enable Channel Preemption. This field resets to 0."]
2457 pub mod ECP {
2458 pub const offset: u8 = 7;
2459 pub const mask: u8 = 0x01 << offset;
2460 pub mod R {}
2461 pub mod W {}
2462 pub mod RW {
2463 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2464 pub const ECP_0: u8 = 0;
2465 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2466 pub const ECP_1: u8 = 0x01;
2467 }
2468 }
2469}
2470#[doc = "Channel Priority Register"]
2471pub mod DCHPRI12 {
2472 #[doc = "Channel n Arbitration Priority"]
2473 pub mod CHPRI {
2474 pub const offset: u8 = 0;
2475 pub const mask: u8 = 0x0f << offset;
2476 pub mod R {}
2477 pub mod W {}
2478 pub mod RW {}
2479 }
2480 #[doc = "Disable Preempt Ability. This field resets to 0."]
2481 pub mod DPA {
2482 pub const offset: u8 = 6;
2483 pub const mask: u8 = 0x01 << offset;
2484 pub mod R {}
2485 pub mod W {}
2486 pub mod RW {
2487 #[doc = "Channel n can suspend a lower priority channel."]
2488 pub const DPA_0: u8 = 0;
2489 #[doc = "Channel n cannot suspend any channel, regardless of channel priority."]
2490 pub const DPA_1: u8 = 0x01;
2491 }
2492 }
2493 #[doc = "Enable Channel Preemption. This field resets to 0."]
2494 pub mod ECP {
2495 pub const offset: u8 = 7;
2496 pub const mask: u8 = 0x01 << offset;
2497 pub mod R {}
2498 pub mod W {}
2499 pub mod RW {
2500 #[doc = "Channel n cannot be suspended by a higher priority channel's service request."]
2501 pub const ECP_0: u8 = 0;
2502 #[doc = "Channel n can be temporarily suspended by the service request of a higher priority channel."]
2503 pub const ECP_1: u8 = 0x01;
2504 }
2505 }
2506}
2507pub mod tcd {
2508 #[doc = "Cluster TCD%s, containing TCD*_SADDR, TCD*_SOFF, TCD*_ATTR, TCD*_NBYTES_MLNO, TCD*_NBYTES_MLOFFNO, TCD*_NBYTES_MLOFFYES, TCD*_SLAST, TCD*_DADDR, TCD*_DOFF, TCD*_CITER_ELINKNO, TCD*_CITER_ELINKYES, TCD*_DLASTSGA, TCD*_CSR, TCD*_BITER_ELINKNO, TCD*_BITER_ELINKYES"]
2509 #[repr(C)]
2510 pub struct RegisterBlock {
2511 #[doc = "TCD Source Address"]
2512 pub TCD_SADDR: crate::RWRegister<u32>,
2513 #[doc = "TCD Signed Source Address Offset"]
2514 pub TCD_SOFF: crate::RWRegister<u16>,
2515 #[doc = "TCD Transfer Attributes"]
2516 pub TCD_ATTR: crate::RWRegister<u16>,
2517 #[doc = "TCD Minor Byte Count (Minor Loop Mapping Disabled)"]
2518 pub TCD_NBYTES_MLNO: crate::RWRegister<u32>,
2519 #[doc = "TCD Last Source Address Adjustment"]
2520 pub TCD_SLAST: crate::RWRegister<u32>,
2521 #[doc = "TCD Destination Address"]
2522 pub TCD_DADDR: crate::RWRegister<u32>,
2523 #[doc = "TCD Signed Destination Address Offset"]
2524 pub TCD_DOFF: crate::RWRegister<u16>,
2525 #[doc = "TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"]
2526 pub TCD_CITER_ELINKNO: crate::RWRegister<u16>,
2527 #[doc = "TCD Last Destination Address Adjustment/Scatter Gather Address"]
2528 pub TCD_DLASTSGA: crate::RWRegister<u32>,
2529 #[doc = "TCD Control and Status"]
2530 pub TCD_CSR: crate::RWRegister<u16>,
2531 #[doc = "TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"]
2532 pub TCD_BITER_ELINKNO: crate::RWRegister<u16>,
2533 }
2534 #[doc = "TCD Source Address"]
2535 pub mod TCD_SADDR {
2536 #[doc = "Source Address"]
2537 pub mod SADDR {
2538 pub const offset: u32 = 0;
2539 pub const mask: u32 = 0xffff_ffff << offset;
2540 pub mod R {}
2541 pub mod W {}
2542 pub mod RW {}
2543 }
2544 }
2545 #[doc = "TCD Signed Source Address Offset"]
2546 pub mod TCD_SOFF {
2547 #[doc = "Source address signed offset"]
2548 pub mod SOFF {
2549 pub const offset: u16 = 0;
2550 pub const mask: u16 = 0xffff << offset;
2551 pub mod R {}
2552 pub mod W {}
2553 pub mod RW {}
2554 }
2555 }
2556 #[doc = "TCD Transfer Attributes"]
2557 pub mod TCD_ATTR {
2558 #[doc = "Destination data transfer size"]
2559 pub mod DSIZE {
2560 pub const offset: u16 = 0;
2561 pub const mask: u16 = 0x07 << offset;
2562 pub mod R {}
2563 pub mod W {}
2564 pub mod RW {}
2565 }
2566 #[doc = "Destination Address Modulo"]
2567 pub mod DMOD {
2568 pub const offset: u16 = 3;
2569 pub const mask: u16 = 0x1f << offset;
2570 pub mod R {}
2571 pub mod W {}
2572 pub mod RW {}
2573 }
2574 #[doc = "Source data transfer size"]
2575 pub mod SSIZE {
2576 pub const offset: u16 = 8;
2577 pub const mask: u16 = 0x07 << offset;
2578 pub mod R {}
2579 pub mod W {}
2580 pub mod RW {
2581 #[doc = "8-bit"]
2582 pub const SSIZE_0: u16 = 0;
2583 #[doc = "16-bit"]
2584 pub const SSIZE_1: u16 = 0x01;
2585 #[doc = "32-bit"]
2586 pub const SSIZE_2: u16 = 0x02;
2587 #[doc = "64-bit"]
2588 pub const SSIZE_3: u16 = 0x03;
2589 #[doc = "32-byte burst (4 beats of 64 bits)"]
2590 pub const SSIZE_5: u16 = 0x05;
2591 }
2592 }
2593 #[doc = "Source Address Modulo"]
2594 pub mod SMOD {
2595 pub const offset: u16 = 11;
2596 pub const mask: u16 = 0x1f << offset;
2597 pub mod R {}
2598 pub mod W {}
2599 pub mod RW {
2600 #[doc = "Source address modulo feature is disabled"]
2601 pub const SMOD_0: u16 = 0;
2602 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2603 pub const SMOD_1: u16 = 0x01;
2604 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2605 pub const SMOD_2: u16 = 0x02;
2606 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2607 pub const SMOD_3: u16 = 0x03;
2608 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2609 pub const SMOD_4: u16 = 0x04;
2610 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2611 pub const SMOD_5: u16 = 0x05;
2612 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2613 pub const SMOD_6: u16 = 0x06;
2614 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2615 pub const SMOD_7: u16 = 0x07;
2616 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2617 pub const SMOD_8: u16 = 0x08;
2618 #[doc = "This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range."]
2619 pub const SMOD_9: u16 = 0x09;
2620 }
2621 }
2622 }
2623 #[doc = "TCD Minor Byte Count (Minor Loop Mapping Disabled)"]
2624 pub mod TCD_NBYTES_MLNO {
2625 #[doc = "Minor Byte Transfer Count"]
2626 pub mod NBYTES {
2627 pub const offset: u32 = 0;
2628 pub const mask: u32 = 0xffff_ffff << offset;
2629 pub mod R {}
2630 pub mod W {}
2631 pub mod RW {}
2632 }
2633 }
2634 #[doc = "TCD Last Source Address Adjustment"]
2635 pub mod TCD_SLAST {
2636 #[doc = "Last Source Address Adjustment"]
2637 pub mod SLAST {
2638 pub const offset: u32 = 0;
2639 pub const mask: u32 = 0xffff_ffff << offset;
2640 pub mod R {}
2641 pub mod W {}
2642 pub mod RW {}
2643 }
2644 }
2645 #[doc = "TCD Destination Address"]
2646 pub mod TCD_DADDR {
2647 #[doc = "Destination Address"]
2648 pub mod DADDR {
2649 pub const offset: u32 = 0;
2650 pub const mask: u32 = 0xffff_ffff << offset;
2651 pub mod R {}
2652 pub mod W {}
2653 pub mod RW {}
2654 }
2655 }
2656 #[doc = "TCD Signed Destination Address Offset"]
2657 pub mod TCD_DOFF {
2658 #[doc = "Destination Address Signed Offset"]
2659 pub mod DOFF {
2660 pub const offset: u16 = 0;
2661 pub const mask: u16 = 0xffff << offset;
2662 pub mod R {}
2663 pub mod W {}
2664 pub mod RW {}
2665 }
2666 }
2667 #[doc = "TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)"]
2668 pub mod TCD_CITER_ELINKNO {
2669 #[doc = "Current Major Iteration Count"]
2670 pub mod CITER {
2671 pub const offset: u16 = 0;
2672 pub const mask: u16 = 0x7fff << offset;
2673 pub mod R {}
2674 pub mod W {}
2675 pub mod RW {}
2676 }
2677 #[doc = "Enable channel-to-channel linking on minor-loop complete"]
2678 pub mod ELINK {
2679 pub const offset: u16 = 15;
2680 pub const mask: u16 = 0x01 << offset;
2681 pub mod R {}
2682 pub mod W {}
2683 pub mod RW {
2684 #[doc = "The channel-to-channel linking is disabled"]
2685 pub const ELINK_0: u16 = 0;
2686 #[doc = "The channel-to-channel linking is enabled"]
2687 pub const ELINK_1: u16 = 0x01;
2688 }
2689 }
2690 }
2691 #[doc = "TCD Last Destination Address Adjustment/Scatter Gather Address"]
2692 pub mod TCD_DLASTSGA {
2693 #[doc = "DLASTSGA"]
2694 pub mod DLASTSGA {
2695 pub const offset: u32 = 0;
2696 pub const mask: u32 = 0xffff_ffff << offset;
2697 pub mod R {}
2698 pub mod W {}
2699 pub mod RW {}
2700 }
2701 }
2702 #[doc = "TCD Control and Status"]
2703 pub mod TCD_CSR {
2704 #[doc = "Channel Start"]
2705 pub mod START {
2706 pub const offset: u16 = 0;
2707 pub const mask: u16 = 0x01 << offset;
2708 pub mod R {}
2709 pub mod W {}
2710 pub mod RW {
2711 #[doc = "The channel is not explicitly started."]
2712 pub const START_0: u16 = 0;
2713 #[doc = "The channel is explicitly started via a software initiated service request."]
2714 pub const START_1: u16 = 0x01;
2715 }
2716 }
2717 #[doc = "Enable an interrupt when major iteration count completes."]
2718 pub mod INTMAJOR {
2719 pub const offset: u16 = 1;
2720 pub const mask: u16 = 0x01 << offset;
2721 pub mod R {}
2722 pub mod W {}
2723 pub mod RW {
2724 #[doc = "The end-of-major loop interrupt is disabled."]
2725 pub const INTMAJOR_0: u16 = 0;
2726 #[doc = "The end-of-major loop interrupt is enabled."]
2727 pub const INTMAJOR_1: u16 = 0x01;
2728 }
2729 }
2730 #[doc = "Enable an interrupt when major counter is half complete."]
2731 pub mod INTHALF {
2732 pub const offset: u16 = 2;
2733 pub const mask: u16 = 0x01 << offset;
2734 pub mod R {}
2735 pub mod W {}
2736 pub mod RW {
2737 #[doc = "The half-point interrupt is disabled."]
2738 pub const INTHALF_0: u16 = 0;
2739 #[doc = "The half-point interrupt is enabled."]
2740 pub const INTHALF_1: u16 = 0x01;
2741 }
2742 }
2743 #[doc = "Disable Request"]
2744 pub mod DREQ {
2745 pub const offset: u16 = 3;
2746 pub const mask: u16 = 0x01 << offset;
2747 pub mod R {}
2748 pub mod W {}
2749 pub mod RW {
2750 #[doc = "The channel's ERQ bit is not affected."]
2751 pub const DREQ_0: u16 = 0;
2752 #[doc = "The channel's ERQ bit is cleared when the major loop is complete."]
2753 pub const DREQ_1: u16 = 0x01;
2754 }
2755 }
2756 #[doc = "Enable Scatter/Gather Processing"]
2757 pub mod ESG {
2758 pub const offset: u16 = 4;
2759 pub const mask: u16 = 0x01 << offset;
2760 pub mod R {}
2761 pub mod W {}
2762 pub mod RW {
2763 #[doc = "The current channel's TCD is normal format."]
2764 pub const ESG_0: u16 = 0;
2765 #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."]
2766 pub const ESG_1: u16 = 0x01;
2767 }
2768 }
2769 #[doc = "Enable channel-to-channel linking on major loop complete"]
2770 pub mod MAJORELINK {
2771 pub const offset: u16 = 5;
2772 pub const mask: u16 = 0x01 << offset;
2773 pub mod R {}
2774 pub mod W {}
2775 pub mod RW {
2776 #[doc = "The channel-to-channel linking is disabled."]
2777 pub const MAJORELINK_0: u16 = 0;
2778 #[doc = "The channel-to-channel linking is enabled."]
2779 pub const MAJORELINK_1: u16 = 0x01;
2780 }
2781 }
2782 #[doc = "Channel Active"]
2783 pub mod ACTIVE {
2784 pub const offset: u16 = 6;
2785 pub const mask: u16 = 0x01 << offset;
2786 pub mod R {}
2787 pub mod W {}
2788 pub mod RW {}
2789 }
2790 #[doc = "Channel Done"]
2791 pub mod DONE {
2792 pub const offset: u16 = 7;
2793 pub const mask: u16 = 0x01 << offset;
2794 pub mod R {}
2795 pub mod W {}
2796 pub mod RW {}
2797 }
2798 #[doc = "Major Loop Link Channel Number"]
2799 pub mod MAJORLINKCH {
2800 pub const offset: u16 = 8;
2801 pub const mask: u16 = 0x0f << offset;
2802 pub mod R {}
2803 pub mod W {}
2804 pub mod RW {}
2805 }
2806 #[doc = "Bandwidth Control"]
2807 pub mod BWC {
2808 pub const offset: u16 = 14;
2809 pub const mask: u16 = 0x03 << offset;
2810 pub mod R {}
2811 pub mod W {}
2812 pub mod RW {
2813 #[doc = "No eDMA engine stalls."]
2814 pub const BWC_0: u16 = 0;
2815 #[doc = "eDMA engine stalls for 4 cycles after each R/W."]
2816 pub const BWC_2: u16 = 0x02;
2817 #[doc = "eDMA engine stalls for 8 cycles after each R/W."]
2818 pub const BWC_3: u16 = 0x03;
2819 }
2820 }
2821 }
2822 #[doc = "TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)"]
2823 pub mod TCD_BITER_ELINKNO {
2824 #[doc = "Starting Major Iteration Count"]
2825 pub mod BITER {
2826 pub const offset: u16 = 0;
2827 pub const mask: u16 = 0x7fff << offset;
2828 pub mod R {}
2829 pub mod W {}
2830 pub mod RW {}
2831 }
2832 #[doc = "Enables channel-to-channel linking on minor loop complete"]
2833 pub mod ELINK {
2834 pub const offset: u16 = 15;
2835 pub const mask: u16 = 0x01 << offset;
2836 pub mod R {}
2837 pub mod W {}
2838 pub mod RW {
2839 #[doc = "The channel-to-channel linking is disabled"]
2840 pub const ELINK_0: u16 = 0;
2841 #[doc = "The channel-to-channel linking is enabled"]
2842 pub const ELINK_1: u16 = 0x01;
2843 }
2844 }
2845 }
2846}